JPH09204244A - Noise elimination circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure the normal operation of a chip by inhibiting noise generated in external signals at the time of data output from being transmitted to internal signals. SOLUTION: In an output control signal generation circuit, signals outputted from a NAND circuit 5 are divided into the two routes of a signal line 24 and the signal line 26 and inputted to the NAND circuit 32, one is delayed in a delay circuit 50 and the noise is eliminated in capacitors 25 and 27. Thus, even in the case that the noise is superimposed on the external signals at the time of the data output, the noise is not transmitted to the signals outputted from the NAND circuit 32 and influence onto output control signals OEM outputted from the output control signal generation circuit is evaded.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise elimination circuit, and more particularly to a noise elimination circuit for eliminating noise generated in an external signal input to a chip when data is output from the chip.

[0002]

2. Description of the Related Art As the chip size is reduced, it is necessary to miniaturize the wiring in the chip. here,
As the wiring becomes finer, the wiring resistance of the entire chip increases and the wiring capacitance decreases. Therefore, noise tends to occur particularly in the power supply wiring.

FIG. 8 is a block diagram showing the overall structure of a conventional semiconductor memory device having a dynamic random access memory. Here, the output control signal generation circuit 20 includes a WE buffer 10, an OE buffer 11, and a RAS.
This is a circuit that inputs an internal signal from each of the buffer 8 and the CAS buffer 9 and outputs an output control signal OEM for controlling the output buffer 19. However, from the above tendency, the noise of the power supply and the earth generated at the time of data output is generated. When it gets louder, the noise affects the internal signal,
The output control signal generating circuit 20 may malfunction and eventually cause a data output error.

FIG. 9 is a circuit diagram showing a structure of a conventional output control signal generating circuit. As shown in FIG. 9, the conventional output control signal generating circuit includes inverters 1 and 6 and a NOR circuit.
Composite gate circuit 4 including circuit 2 and gate circuit 3
And a NAND circuit 5 and a capacitor 7. Then, the external signal ext. / WE, the internal signal / WE output from the WE buffer is input, and the output signal of the inverter 1 and the external signal ext. Internal signal / RASC output from RAS buffer based on / RAS
2 is input to the NOR circuit 2. The output signal of the NOR circuit 2 and the output signal of the NAND circuit 5 are input to the gate circuit 3 included in the composite gate circuit 4, and the output signal of the gate circuit 3 and the external signal ex are input to the NAND circuit 5.
t. / CAS, the internal signal CAS output from the CAS buffer and the external signal ext. The internal signal OE output from the OE buffer based on / OE is input. Here, the output signal of the NAND circuit 5 is the inverter 6
And the output control signal OEM is output from the inverter 6.

Next, the operation of this conventional output control signal generating circuit will be described with reference to the timing chart of FIG. During the read operation, from the outside of the chip, as shown in FIG.
External signals e shown in (c), (e), and (g), respectively.
xt. / RAS, ext. / CAS, ext. / WE,
ext. / OE is input. Here, the external signal ex
t. / RAS based on the RAS buffer shown in FIG.
The low level internal signal / RASC2 shown in (b) is input to the NOR circuit 2. On the other hand, the external signal ext. /
Based on WE, the high level internal signal / WE shown in FIG. 10 (f) is input to the inverter 1 from the WE buffer, so that the NOR circuit 2 receives a low level signal. As a result, the NOR circuit 2 outputs a high level signal, and the output of the gate circuit 3 becomes a high level signal and is input to the NAND circuit 5.

The NAND circuit 5 has an external signal ex
t. Is output from the OE buffer based on / OE.
The internal signal OE shown in (h) is input. further,
In the NAND circuit 5, the external signal ext. Based on / CAS, the internal signal CAS output from the CAS buffer and shown in FIG. 10D is input. And from this, NA
The output of the ND circuit 5 becomes a low level signal. This NA
The output signal of the ND circuit 5 is input to the gate circuit 3, the polarity is inverted by the inverter 6 and the noise is removed by the capacitor 7, and then the high-level output control signal OEM shown in FIG. Is output as. As a result, FIG.
As shown in (j), data is output from the data output terminal.

[0007]

However, in the above-mentioned output control signal generation circuit, noise is generated in a plurality of external signals during data output, which in turn affects the output control signal and causes an output error. There was a problem of being lost. Specifically, for example,
External signal ext. / RAS, ext. /
A case where noise is added to CAS will be described with reference to the timing chart of FIG.

As shown in FIG. 11A, a low level external signal ext. When noise that becomes high level for a moment is added to / RAS, as shown in FIG. 11B, the internal signal / RASC output from the RAS buffer is output.
Similar noise is generated in 2. In addition, FIG.
As shown in (d), the low-level external signal ex
t. Even when / CAS has a noise that temporarily becomes a high level, noise that temporarily becomes a low level is generated in the high-level internal signal CAS. In addition, FIG.
As shown in (h), both internal signal / WE and internal signal OE have a high level as in the normal operation. In this case, the NOR circuit 2 shown in FIG.
Is a low level signal output from the inverter 1 and an internal signal / R having noise that temporarily becomes a high level.
Since ASC2 is input, its noise causes NOR
The circuit 2 outputs a low level signal for a moment. As a result, the gate circuit 3 outputs a signal in which the polarity of the output signal from the NAND circuit 5 is inverted. On the other hand, N
Since the AND circuit 5 is supplied with the internal signal CAS having noise that is at a low level for a moment, the NAND circuit 5 outputs a signal at a high level for a moment. Since this signal is inverted by the inverter 6, the signal shown in FIG.
As shown in (i), the output control signal OEM goes low for a moment. Here, when the output control signal OEM is at a low level, data is not output from the data output terminal, so that an error occurs in data output as shown in FIG. 11 (j).

The present invention has been made to solve the above problems, and ensures normal chip operation by preventing noise generated in an external signal during data output from being transmitted to the internal signal. The purpose is.

[0010]

A noise removing circuit according to a first aspect of the present invention is a noise removing circuit in an output control signal generating circuit for inputting a plurality of internal signals to generate an output control signal. And delay means. Here, the delay means generates a delay signal from a logic signal generated based on a plurality of internal signals and removes noise of the delay signal. Further, the NAND circuit receives the logic signal and the delay signal,
Generate an output control signal.

A noise removal circuit according to a second aspect is the noise removal circuit according to the first aspect, wherein the delay means includes an even number of inversion means, and each of the inversion means inverts the polarity of the logic signal. An inverter, a signal line connected between the output node of the inverter and the NAND circuit, a power supply node, a first capacitor connected between the power supply node and the signal line, a ground node, and a ground node And a second capacitor connected between the signal line and the signal line.

A noise removing circuit according to a third aspect comprises an external signal input terminal and a noise removing means. Here, the external signal input terminal inputs an external signal activated from the first logic level to the second logic level into the chip.
The noise removing means maintains the external signal input from the external signal input terminal at the second logic level based on the output control signal activated to output the data from the chip.

A noise removal circuit according to a fourth aspect is the noise removal circuit according to the third aspect, wherein the noise removal means is a delay means, a first NAND circuit, and a second NAN.
Includes D circuit. Here, the delay means generates a delay signal whose polarity is inverted from the output control signal. Also, the first N
The delay signal and the output control signal are input to the AND circuit. The second NAND circuit has a first NAN.
The signal output from the D circuit and the external signal are input.

A noise removing circuit according to a fifth aspect is the noise removing circuit according to the third aspect, wherein the noise removing means includes a signal line connected to an external signal input terminal and a switching means. Here, the switch means is connected between the signal line and the ground node, and connects the signal line and the ground node when the output control signal is activated.

A noise eliminating circuit according to a sixth aspect is the noise eliminating circuit according to the fifth aspect, further comprising a capacitor connected between an output node of the switch means and a ground node, and the switch means, When the output control signal is inactive, the signal line is disconnected from the capacitor.

A noise eliminating circuit according to a seventh aspect is the noise eliminating circuit according to the sixth aspect, further comprising a discharging means connected in parallel with the capacitance between an output node of the switching means and a ground node. The discharge means is provided to discharge the electric charge accumulated in the capacitance to the ground node when the output control signal is inactive.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

[First Embodiment] FIG. 1 is a circuit diagram showing a structure of an output control signal generating circuit including a noise removing circuit 33 according to a first embodiment of the present invention.

As shown in FIG. 1, the noise eliminating circuit 33 according to the first embodiment is provided between the output node of the NAND circuit 5 and the node C in the conventional output control signal generating circuit shown in FIG. A delay circuit 50 connected to delay the output signal of the NAND circuit 5, a NAND circuit 32 for inputting the output signal of the NAND circuit 5 and the delay signal generated by the delay circuit 50, and an output signal from the NAND circuit 32 And an inverter 31 for inverting.
The delay circuit 50 includes an even number of inverting circuits connected in series. The inverting circuit includes an inverter 29 that inverts the polarity of the output signal from the NAND circuit 5, an output node of the inverter 29, and the NAND circuit 32. Connected between the signal line 24, the power supply node 23, the capacitor 25 connected between the power supply node 23 and the signal line 24, the ground node, and connected between the ground node and the signal line 24. Capacity 2
7 is included. Here, the capacitance 2 included in the delay circuit 50
Reference numerals 5 and 27 are for absorbing the noise of the delayed signal and improving the noise removing effect on the output control signal OEM as a whole.
It is particularly useful in the case where there is a large noise width that is not removed by the logical operation of the NAND circuit 32 by delaying with a plurality of inverting circuits included in.
Note that FIG. 1 illustrates the case where two inverting circuits are connected in series, but the case where four or more even number of inverting circuits are connected in series is also considered.

Next, the operation of the output control signal generating circuit including the noise removing circuit 33 according to the first embodiment will be described with reference to FIG.
This will be described with reference to the timing chart of FIG.

As shown in FIGS. 2A and 2C, when data is output from the data output terminal, the external signal ex
t. / RAS and external signal ext. When noise that becomes high level for a moment is added to / CAS, as shown in FIG.
As shown in (d), the internal signal / RASC2 has a momentarily high level, and the internal signal CAS has a momentarily low level. Internal signal / WE
Also, the internal signal OE is maintained at the high level as in the normal operation. In this case, since the internal signal CAS is input to the NAND circuit 5, its output momentarily becomes high level due to low-level noise on the internal signal CAS. The output signal, which is at a high level for a moment, is directly input to the NAND circuit 32 via the signal line 26, delayed by the delay circuit 50, and input to the NAND circuit 32. In this case, the polarity of the signal input to the delay circuit 50 is inverted by the inverter 29 an even number of times, and the noise is absorbed by the capacitors 25 and 27.

Therefore, the output of the NAND circuit 32 is always set to the high level regardless of the noise width by shifting the noise which becomes the high level for a moment and shifting the noise temporally and absorbing the noise itself. From this, the action of the inverter 31 and the inverter 6 causes
The output control signal generation circuit can output the high-level output control signal OEM which is not affected by the noise shown in FIG. 2 (i), so that the normal data output is performed as shown in FIG. 2 (j). Secured.

Since a low level signal is input to the gate circuit 3 from the node C, the internal signal / RAS
The gate circuit 3 outputs a high-level signal regardless of the noise generated on C2.

According to the noise elimination circuit of the first embodiment described above, even if noise occurs in a plurality of external signals during data output, noise is not transmitted to the output control signal OEM.
Normal data output can be guaranteed.

[Second Embodiment] FIG. 3 is a circuit diagram showing a structure of a noise removing circuit according to a second embodiment of the present invention. As shown in FIG. 3, this noise removing circuit removes the noise of the external signal input from the external signal input terminal 60 also shown in FIG. 8 based on the output control signal OEM generated by the output control signal generating circuit. To remove it. This noise removing circuit includes an odd number of inverters 34-
An output control signal delay circuit 51 consisting of 36 connected in series,
A NAND circuit 37 for inputting the delay signal output from the output control signal delay circuit 51 and the output control signal OEM
An external signal input terminal 60 for inputting an external signal into the chip; a NAND circuit 38 for inputting a signal output from the NAND circuit 37 and an external signal input from the external signal input terminal 60; and an output from the NAND circuit 38. An inverter 39 for inverting the polarity of the signal to be generated.

Next, the operation of the noise removing circuit according to the second embodiment will be described with reference to the timing chart of FIG. As shown in FIGS. 4B and 4C, when the output control signal OEM is at the low level, the NAND circuit 37
Since a high level signal from the output control signal delay circuit 51 and a low level signal is input to the
The potential of the node D becomes high level. However, when the output control signal OEM is activated to a high level for data output, the high level output control signal OEM is directly input to the NAND circuit 37 via the signal line 40, while the output control signal delay is still delayed. A high level signal is input from the circuit 51 for a delay time (5 ns in this embodiment). Therefore, only the delay time is
Since two high level signals are input to the circuit 37, a low level signal is output and the potential of the node D becomes low level as shown in FIG. 4C. Therefore, even when the output signal OEM is activated to the high level and then the noise that temporarily becomes the high level is generated in the external signal within the delay time (5 ns) as shown in FIG. 4A. , The NAND circuit 38 includes the NAND circuit 3
Since the low-level signal is input from 7 during that period, a high-level signal is output from the NAND circuit 38. As a result, the inverter 39 outputs noise to the inside as shown in FIG. Signal that is maintained at a low level without being transmitted.

According to the noise removing circuit of the second embodiment described above, the noise generated in the external signal at the time of data output can be removed based on the output control signal activated at the time of data output. It is possible to keep the operation normal.

[Third Embodiment] FIG. 5 is a circuit diagram showing a structure of a noise removing circuit according to a third embodiment of the present invention. As shown in FIG. 5, the noise removing circuit has an external signal input terminal 60 for inputting an external signal into the chip.
And a signal line 44 connected to the external signal input terminal 60,
An N-channel MOS transistor 43 having a source connected to the ground node and a drain connected to the signal line 44, an inverter 42 having an output node connected to the gate of the N-channel MOS transistor 43, and an output node having the inverter 4 described above.
And an inverter 41 connected to the second input node and receiving the output control signal OEM.

Next, the operation of the noise removing circuit according to the third embodiment will be described with reference to the timing chart of FIG. From the external signal input terminal 60, the external signal ext. / RAS,
Or ext. / CAS, or ext. / WE, or ext. When / OE is input, when data is output from the chip, the output control signal OEM becomes high as shown in FIG. 6B. Here, at the time of data output, as shown in FIG. 6 (a), a low-level external signal (ext./RAS, etc.) may generate a noise that temporarily becomes a high level. At this time, the output control signal OEM activated to the high level is
Since the polarities are inverted twice by the inverter 41 and the inverter 42 and input to the gate of the N-channel MOS transistor 43, the N-channel MOS transistor 4
3 is on, and the signal line 44 and the ground node are connected. Therefore, the potential of the signal line 44 is pulled to the ground potential and maintained at the low level, so that noise is removed and is not transmitted to the inside, as shown in FIG. 6C.

When output control signal OEM is in a low level inactive state, N-channel MOS transistor 43 is turned off, and the potential level of signal line 44 is maintained as it is.

According to the noise eliminator according to the third embodiment described above, noise generated in the external signal at the time of data output is directly released to the ground node based on the output control signal activated at the time of data output. The operation of the chip can be maintained normally without transmitting noise to the inside.

[Fourth Embodiment] FIG. 7 is a circuit diagram showing a structure of a noise removing circuit according to a fourth embodiment of the present invention. As shown in FIG. 7, this noise removing circuit has the same configuration as the noise removing circuit according to the third embodiment, but has a capacitance connected between the source of N channel MOS transistor 43 and the ground node. 46, a P-channel MOS transistor 45 arranged in parallel with the capacitor 46, having a source connected to the node E, a drain connected to the ground node, and a gate to which the output control signal OEM is input.

Next, the operation of the noise removal circuit according to the fourth embodiment will be described. This noise removing circuit operates as shown in the timing chart of FIG. 6 as in the third embodiment, but the activated high-level output control signal OEM transmits N-channel signals through the inverters 41 and 42. M
N-channel M input to the gate of the OS transistor 43
When the OS transistor 43 is turned on, the external signal ext. / RA
S, or ext. / CAS, or ext. / WE,
Or ext. The difference is that the noise generated in / OE is removed by being absorbed by the capacitor 46. At this time, the P-channel MOS transistor 45 is off.

On the other hand, when the output control signal OEM is in the low level inactive state, the low level signal is input to the gate of the N channel MOS transistor 43 through the inverters 41 and 42, so that the N channel MOS is provided. The transistor 43 is turned off, and the signal line 44 and the capacitor 46 are electrically disconnected. Further, in this case, since a low level signal is input to the gate of the P channel MOS transistor 45, it is turned on. As a result, since the node E and the ground node are connected, it is possible to discharge the electric charge accumulated in the capacitor 46 to the ground node by absorbing noise when the output control signal OEM is in the activated high level. . In such discharge, the potential of the node E due to the electric charge remaining in the capacitor 46 is transmitted on the signal line 44 as noise at the moment when the output control signal OEM is activated to the high level again and the N-channel MOS transistor 43 is turned on. This is to prevent riding on an external signal (ext./RAS, etc.).

According to the noise eliminating circuit of the fourth embodiment, noise generated in the external signal at the time of data output can be absorbed by the capacitor and the electric charge accumulated in the capacitor is discharged to the ground node. The potential level of the external signal can be maintained by removing it, and as a result, normal operation of the chip can be ensured. Further, when the output control signal OEM is in the low level inactive state, the N-channel MOS transistor 43 is turned off, so that the input capacitance is reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an output control signal generation circuit including a noise removal circuit according to a first embodiment of the present invention.

FIG. 2 is a timing diagram showing an operation of the output control signal generation circuit shown in FIG.

FIG. 3 is a circuit diagram showing a configuration of a noise removing circuit according to a second embodiment of the present invention.

FIG. 4 is a timing diagram showing an operation of the noise removing circuit shown in FIG.

FIG. 5 is a circuit diagram showing a configuration of a noise removal circuit according to a third embodiment of the present invention.

FIG. 6 is a timing diagram showing an operation of the noise removal circuit shown in FIG.

FIG. 7 is a circuit diagram showing a configuration of a noise removing circuit according to a fourth embodiment of the present invention.

FIG. 8 is a block diagram showing an overall configuration of a conventional semiconductor memory device having a dynamic random access memory.

FIG. 9 is a circuit diagram showing a configuration of a conventional output control signal generation circuit.

FIG. 10 is a timing diagram showing an operation of the output control signal generation circuit of FIG.

FIG. 11 shows an external signal ext. / RAS, ext. / C
FIG. 10 is a timing diagram showing an operation of the output control signal generation circuit shown in FIG. 9 when noise is added to AS.

[Explanation of symbols]

1, 6, 29, 31, 34, 35, 36, 39, 41,
42 inverter, 2 NOR circuit, 3 gate circuit, 4
Composite gate circuit, 5, 32, 37, 38 NAND circuit, 23 power supply node, 7, 25, 27, 46 capacitance,
33 noise elimination circuit, 24, 26, 40, 44 signal line, 43 N channel MOS transistor, 45 P channel MOS transistor, 50 delay circuit, 51 output control signal delay circuit, 60 external signal input terminal, OEM
Output control signal.

Claims (7)

[Claims] 1. A noise elimination circuit in an output control signal generation circuit for inputting a plurality of internal signals to generate an output control signal, comprising: a NAND circuit; and a logic signal generated based on the plurality of internal signals. A delay circuit for generating a delay signal and removing noise of the delay signal, wherein the NAND circuit receives the logic signal and the delay signal to generate the output control signal,
Noise removal circuit. 2. The delay means includes an even number of inverting means, each of the inverting means being connected between an inverter for inverting the polarity of the logic signal and an output node of the inverter and the NAND circuit. A connected signal line, a power supply node, a first capacitance connected between the power supply node and the signal line, a ground node, and a second capacitance connected between the ground node and the signal line. The noise elimination circuit according to claim 1, further comprising: 3. An external signal input terminal for inputting an external signal activated from a first logic level to a second logic level into a chip, and an output control activated for outputting data from the chip. A noise removing circuit for maintaining the external signal input from the external signal input terminal at the second logic level based on a signal. 4. The noise removing means includes delay means for generating a delay signal whose polarity is inverted from that of the output control signal, and first delay signal and the output control signal.
4. The noise removing circuit according to claim 3, further comprising: a NAND circuit according to claim 1; and a second NAND circuit into which the signal output from the first NAND circuit and the external signal are input. 5. The noise removing means includes a signal line connected to the external signal input terminal and a switch means connected between the signal line and a ground node, and the switch means outputs the output signal. 4. The noise elimination circuit according to claim 3, wherein the signal line is connected to the ground node when a control signal is activated. 6. The switch further comprises a capacitor connected between the output node of the switch means and the ground node, wherein the switch means connects the signal line and the signal line when the output control signal is inactive. The capacity is separated from the capacity.
Noise removal circuit described in. 7. The discharge means is further connected in parallel with the capacitor between the output node of the switch means and the ground node, and the discharge means is provided when the output control signal is inactive. 7. The noise elimination circuit according to claim 6, wherein the electric charge accumulated in the capacitance is discharged to the ground node.