JPH09200008A - Signal generating circuit and method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily and accurately set a minimum and a maximum pulse width of an output signal. SOLUTION: A PWM circuit consisting of a triangle wave generator 3, a D/A converter 4, and a comparator 5 or the like provides an output of a signal of a pulse width corresponding to input data DAT. A D-F/F 10 expands the period of the output signal by a prescribed multiple while keeping the duty of the output signal by using a clock CKM asynchronously with the output signal and a counter 14 measures the pulse width of the expanded signal. A correction arithmetic section 16 corrects data Nx1, Nx2 to set a minimum and a maximum pulse width of the received output signal based on the measured pulse width and a comparator 19 compares the measured pulse width with the corrected data Nx1, Nx2 and an adjustment data control section 20 adjusts the pulse width of the output signal based on the result of comparison.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal generating circuit and a method thereof, for example, a signal generating circuit which outputs a signal having a pulse width corresponding to input data and a method thereof.

[0002]

2. Description of the Related Art For example, in forming a gradation image in a laser beam printer or a digital copying machine, there is a method of performing pixel modulation by PWM of a laser beam for each pixel. As the laser beam printer and the digital copying machine have become higher in speed and higher in definition, the frequency of the pixel clock has been increasing.

FIG. 1 is a diagram showing a configuration example of a high-speed PWM circuit, in which a pixel clock SC having a frequency fo input to a clock input terminal is used.
K1 is sent to the triangular wave generator 3 and the DA converter (PWDAC) 4. The triangular wave generator 3 has a rise and fall in line symmetry and generates a triangular wave (TRI) synchronized with SCK. For example, a DA converter to which 8-bit digital image data DAT2 is input
4 outputs an analog voltage (VA) according to DAT in synchronization with SCK.

The output range of this VA is the adjusted DA converter (ADJ D
The output of AC) 8 is set to the VA reference potential when DAT = '00 ', and the gain of DA converter 4 is changed by the current value of constant current source 7, and VA is set to VA when DAT =' FF '. Is set to. This constant current source 7 is an adjusted DA converter (ADJ DAC) 9
Is controlled by Further, the adjustment DA converters 8 and 9 are controlled by the adjustment data 24 and the adjustment data 25 input to the input terminals.

The triangular wave (TRI) and VA are respectively connected to the positive and negative inputs of the comparator 5, the comparator 5 compares both signals, and the comparison result is output as a PWM signal via the buffer 6.

FIG. 2 is a timing chart for explaining the operation of the high-speed PWM circuit. VA (00) set by the adjustment data 24.
And VA (FF) set by the adjustment data 25
The output VA of the DA converter 4 and the triangular wave (TRI) are compared, and the pulse width of PW (00) to PW (FF) is changed according to the value of pixel data (DAT) '00'to'FF'. A PWM signal that changes linearly in the range is output.

That is, the minimum pulse width of the PWM signal is DAT = '0
Adjust the value of adjustment data 24 so that it becomes PW (00) at 0 ', and the maximum pulse width of the PWM signal is PW at DAT =' FF '.
The value of the adjustment data 25 may be adjusted so that it becomes (FF).
In this way, by giving adjustment data from the outside,
The PWM modulation factor can be set arbitrarily.

[0008]

However, the above-mentioned technique has the following problems.

A laser beam printer or a digital copying machine is required to have a gradation of about 8 bits. Since the pixel clock has a high frequency of several tens of MHz, it is difficult to realize a high-speed PWM circuit that attempts to control 1/256 of the pixel clock cycle without using an IC. But,
There is a limit to the power supply voltage in IC integration, and it is required to use a power supply voltage of about 5V in a system that is usually used frequently. Therefore, the triangular wave (TRI) is also limited in its peak-to-peak level (VPP) to about 700 to 800 mV due to the restriction of the power supply voltage.
Assuming that the triangular wave VPP is 750 mV and the output range of the DA converter 4 is VPP, about 2.9 mV per DAT bit (= 750 mV / 256)
Will be controlled.

Further, the IC design is basically a relative design,
The relative accuracy inside the IC is very good, and the base of the transistor
-Generally, the relative error ΔVbe of the emitter-to-emitter voltage Vbe is about 3 mV and the relative error ΔR of the resistor is about 2%.

However, in the above-mentioned high-speed PWM circuit, the relative accuracy of the IC cannot be ignored in order to obtain its high gradation. In the high-speed PWM circuit described above, the pulse width of the PWM output should be determined by the relative relationship between the triangular wave (TRI) VPP, the DC offset level (VDC), and the DA converter 4 output (VA). Causes a deviation from the design value due to element variation due to a combination of a plurality of design factors.
Therefore, there is a deviation of the design value between the adjustment data and the output pulse width, and there is a disadvantage that the output pulse width of the IC must be individually measured and the adjustment data must be changed to perform the adjustment.
Also for the adjustment, the pulse width of the PWM output becomes several ns due to the high-speed pixel clock, and measurement accuracy of the order of several tens of ps is required, so an expensive measuring instrument is required, and the adjustment time and adjustment There is a problem that the number of personnel increases.

The present invention is for solving the above-mentioned problems, and the minimum and maximum pulse widths of an output signal can be set accurately and easily, and the setting can be automatically performed. An object of the present invention is to provide a signal generation circuit and its method.

[0013]

The present invention has the following configuration as one means for achieving the above object.

The signal generation circuit according to the present invention comprises a generation means for generating an output signal having a pulse width corresponding to the input data, and an expansion means for expanding the cycle of the output signal by a predetermined number while holding the duty. A measuring means for measuring the pulse width of the signal expanded by the expanding means and setting data for setting the minimum and maximum pulse widths of the output signal are inputted, and the setting data is obtained based on the pulse width obtained by the measuring means. Correcting means for correcting the pulse width, comparing means for comparing the pulse width obtained by the measuring means with the setting data corrected by the correcting means, and controlling the generating means based on the comparison result obtained by the comparing means. Adjusting means for adjusting the pulse width of the output signal.

A signal generating method according to the present invention includes a generating step of generating an output signal having a pulse width corresponding to input data, and an expanding step of expanding a cycle of the output signal to a predetermined multiple while holding a duty. A measuring step of measuring a pulse width of the signal expanded in the expanding step,
An input step of inputting setting data for setting the minimum and maximum pulse widths of the output signal, a correction step of correcting the setting data based on the pulse width obtained in the measuring step, and a pulse width obtained in the measuring step. It is characterized by comprising a comparison step of comparing the setting data corrected in the correction step and an adjustment step of adjusting the pulse width of the output signal based on the comparison result obtained in the comparison step.

The image processing apparatus according to the present invention includes a generation means for generating an output signal having a pulse width corresponding to the input data, and an expansion means for expanding the cycle of the output signal by a predetermined multiple while holding the duty. A measuring means for measuring the pulse width of the signal expanded by the expanding means and setting data for setting the minimum and maximum pulse widths of the output signal are inputted, and the setting data is obtained based on the pulse width obtained by the measuring means. Correcting means for correcting the pulse width, comparing means for comparing the pulse width obtained by the measuring means with the setting data corrected by the correcting means, and controlling the generating means based on the comparison result obtained by the comparing means. A signal generation circuit having an adjusting means for adjusting the pulse width of the output signal, and outputting a signal having a pulse width according to the input image data. It is characterized in.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an image processing apparatus according to an embodiment of the present invention will be described in detail with reference to the drawings.

[0018]

[First Embodiment] FIG. 3 shows a high speed of one embodiment according to the present invention.
FIG. 4 is a block diagram showing a configuration example of the PWM circuit, and FIG. 4 is a timing chart for explaining the operation of the high-speed PWM circuit of this embodiment. Note that, in FIG. 3, the configurations denoted by reference numerals 1 to 9, 24, and 25 are the same as those in FIG.

The switch 22 is switched to the a side in the normal operation by the control signal P1 to switch the image data (DAT) 2 to the high speed P
While the WM circuit is being adjusted, switch to the b side and select the output Da of the pseudo pixel data switching unit 21 to select the DA converter (PWD
Send to AC) 4. The pseudo pixel data switching unit 21 controls the control signal P3 =
Data is Da = '00 'when' 0 'and Da when P3 =' 1 '.
= 'FF' is output.

The PWM signal output from the buffer 6 is input to DF / F10 which is a time axis expansion means. A clock signal CKM (frequency f1 = fo (1 ± 1 / N)) that has a frequency difference between the pixel clock SCK of frequency fo and fo / N and is asynchronous with SCK is input to the clock terminal of DF / F10. . For example, when N = 1000, the PWM signal (QPWM) expanded in the time axis becomes a signal in which the duty ratio of the PWM signal is preserved and the cycle is expanded 1000 times in the time axis.

The QPWM is sent to the terminal a of the switch 12 and its output is input to the halving frequency divider 11 connected to the terminal b of the switch 12. The switch 12 has a control signal P2.
The side b is selected when P2 = '0' and the side a is selected when P2 = '1', and the selected signal S1 is sent to the count operation control terminal of the counter 14.

The counter 14 counts CKM during the period of S1 = '1' after being reset by S1 = '1', and when S1 transits from '1' to '0', the count value at that time is changed. S1 = '0'
Hold during the period. Count value of counter 14
NP represents the pulse width of the time-base stretched pulse QPWM ('1' period) or the period obtained by dividing QPWM in half ('1' period), that is, one cycle of the QPIC measured in the CKM cycle. The output Np of the counter 14 is latched by the latch unit 15 at the rising edge of the control signal P2, becomes a latch output Nt, and is input to the correction calculation unit 16. After latching, the counter 14 is reset.

The correction calculator 16 is configured to output the minimum pulse width PW (0
The adjustment data Nx1 for setting 0) and the adjustment data Nx2 for setting the maximum pulse width PW (FF) are input, and the design value No of the frequency difference between SCK and CKM is stored inside. SCK cycle To N
and the duty ratio of the pulse width you want to set is D
If U1 (%) and DU2 (%) are set, the adjustment data Nx1 and Nx2 are as follows. Nx1 = No ・ DU1 / 100 Nx2 = No ・ DU2 / 100… (1)

The set values Nx1 and Nx2 are determined relative to No, but it is difficult to set No to exactly 1000, for example, 10
Even if it is possible to set it to 00, considering environmental changes and aging changes,
It is very difficult to guarantee the frequency difference.

Therefore, the period of the QPICT signal is counted by counting the '1' period of the QPIC, which is obtained by dividing the QPWM by two, and the count result is latched from Nt to SCK and C
The deviation amount (deviation between No and Nt) of the frequency difference of KM from the design value is obtained, and the adjustment data Nx1 and Nx2 are corrected with the result. The corrected adjustment data Nx11 and Nx21 are as follows. Nx11 = Nx1 ・ Nt / No Nx21 = Nx2 ・ Nt / No… (2)

When the control signal P3 = '0', the correction calculator 16
Nx11 is output as the set value Nx when N3 is P1 = '1'. The set value Nx is input to the negative input terminal of the comparator 19, and the count value Np of the counter 14 is input to the positive input terminal of the comparator 19. When the control signal P2 = '1', the comparator 19 compares the count value Np of the counter 14 with the set value Nx, and when Np> Nx, outputs the control signal P4 = '1'. The control signal P3 is also set to "1" at the rising edge of P4.

As described above, the control signal P3 switches the output Nx of the correction calculation unit 16 to the minimum pulse width setting value Nx11 or the maximum pulse width setting value Nx21, and outputs the pseudo pixel data output Da of the pseudo pixel data switching unit 21. Switch to '00'or'FF'.
Further, the control signals P3 and P4 are input to the adjustment data control unit 20.

The adjustment data control unit 20 controls the control signal P3 = '0'.
In this case, the adjustment data 24 of the adjustment DA converter 8 for setting the minimum pulse width is incremented from '00' by 1 every time the falling edge of QPICT is input via the inverter 17. Then, when P3 = '0' and at the rising edge of P4, the adjustment data 24 to be sent to the adjustment DA converter 8 is latched.

If P3 = '1', the adjustment data control unit
20 increases the adjustment data 25 of the adjustment DA converter 9 for setting the maximum pulse width from "00" by 1 each time the falling edge of QPICT is input via the inverter 17. Then, when P3 = '1' and at the rising edge of P4, the adjustment data 25 to be sent to the adjustment DA converter 9 is latched.

As described above, the adjustment data 24 and 25 can be corrected to set appropriate minimum and maximum pulse widths.

FIG. 5 is a timing chart for explaining the time axis expansion operation by the DF / F 10, and shows an example in which the time axis is expanded 12 times.

The PWM signal input to the data terminal D of the DF / F 10 has a frequency fo (cycle To) and a duty ratio of 5 to 6, for example. The clock CKM input to the clock terminal of DF / F10 has a frequency f1 (cycle T1), for example. PWM and CK
Since M is asynchronous, as shown in Fig. 5, the relative phase of PWM and CKM has a phase difference at the timing when both phases match.
After that, the phase difference becomes 0 for each clock, PWM and CK.
Shift by the cycle difference of M.

To extend the time axis 12 times by the DF / F operation, if the difference between the cycles of PWM and CKM is dt (= T1-T0), T1 = 12.dt
And T1 = N · dt when the time axis is extended N times. Therefore, the frequency f1 of the clock CKM for time extension is obtained by the following equation. f1 = fo (N-1) / N… (3) fo-f1 = fo / N… (4)

As described above, the time base expansion is performed by PWM and CKM.
It is performed by time management of the period difference dt. As shown in Figure 5,
The duty of QPWM with time axis extension is 5 · T1 vs. 6 · T1, and the duty before time axis extension is saved.

However, the time axis extension is as described above.
Strictly speaking, since the period difference dt is managed by time, an error of dt occurs with respect to the period N · T1 of the time-extended QPWM. The dDU obtained by converting this error into a duty is as follows. dDU = dt / (N ・ T1) = dt / (N ・ N ・ dt) = 1 / (N ^ 2)… (5) where N ^ 2 represents the square of N

Therefore, the larger the resolution N of the time axis expansion becomes, the smaller the error becomes.

In the present embodiment, if 8-bit gradation is applied to the PWM signal, at least time-axis expansion resolution of 9 bits or more is required. In addition, since the duty of the time-expanded QPWM is preserved and the time is managed for each CKM cycle by the DF / F operation, the QPWM
Items related to time (phase) such as pulse width of can be easily measured by counting with CKM.

As described above, according to the present embodiment, in the high-speed PWM circuit made into an IC, when the deviation of the design value generated between the adjustment data and the output pulse width is individually adjusted, it is automatically adjusted. In addition, since the output pulse width can be measured, the adjustment data can be changed, and accurate adjustment can be performed, an expensive measuring instrument is not required, and the adjustment time and the number of adjustment personnel are not increased.

[0039]

Second Embodiment Hereinafter, an image processing apparatus according to a second embodiment of the present invention will be described. In the second embodiment,
The same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the above-described first embodiment, the adjustment system that requires the second clock CKM for time extension in addition to the pixel clock required for PWM has been described. When included in the circuit, the cost increase by adding the second clock generator,
There is a problem such as noise that occurs when asynchronous clocks whose frequencies are close to each other interfere with each other.

Therefore, in the second embodiment, the clock CKM is created from the pixel clock SCK to solve problems such as cost increase and noise. Therefore, the difference between the first embodiment and the second embodiment is that the CKM
Since it is only the part for creating CKM, only the configuration for creating CKM will be described below.

FIG. 6 is a block diagram showing a configuration example for creating a CKM in this embodiment, and FIG. 7 is a timing chart for explaining the operation thereof.

The frequency divider 23 inputs the pixel clock SCK,
The halved output (CK2) is input to the second triangular wave generating section 24 having the same configuration as the triangular wave generating section 3. The triangular wave generator 24 is shown in FIG.
As shown in, the triangular wave TRI2 is generated in synchronism with the triangular wave TRI and having a cycle twice that of TRI. Output of triangular wave generator 24 TRI2
Is input to the positive input terminal of the comparator 25.

Further, the negative input terminal of the comparator 25 is
A switch that is connected to the other end of a capacitor C1 whose one end is grounded and that is switched by a control signal P4
26 is connected. The switch 26 has a control signal P4 = '0'.
In the case of, the reference voltages V1 and C1 are connected, and in the case of P4 = '1', the constant current source 27 supplying the current I1 and C1 are connected. Here, the reference voltage V1 is a voltage equal to or lower than the lower peak voltage of the triangular wave TRI2.

At P4 = '0', the terminal voltage of C1 is V1 and the voltage of the negative input terminal of the comparator 25 is Vx = V1.
Then, when P4 = '1', charging of C1 by the current I1 is started, and the voltage Vx rises according to the following equation. Vx = (I1 / C1) T (6) where T is time

The comparator 25 compares the triangular wave TRI2 with the voltage Vx and outputs the comparison output CKM. Comparator 25
The rising edge of the output CKM of
As Vx rises in accordance with the charging of, triangular wave TRI2 is linearly shifted from the lower peak to the upper peak every two SCK cycles. FIG. 8 is a diagram for explaining this shift amount. This shift amount dt is expressed as follows: VPP2 is the peak-to-peak level of the triangular wave TRI2, and N is the ratio of dt to the SCK cycle To.
There is the following relationship: dt = (To / VPP2) ・ dVx = To / N… (7) dVx = (2To + dt) ・ I1 / C1… (8)

If the ratio of the shift amount dt to the SCK cycle, that is, the time base expansion rate N is calculated from these relationships, the relationship of the following equation is obtained. N = 0.5 ・ (VPP2 ・ C1 / To / Io-1)… (9)

For example, fo = 20 MHz (To = 50 ns), VPP2 = 750 m
When V, C1 = 10nF and I1 = 0.1mA, N = 749.5 is obtained.
If the circuit is designed so as to obtain the required time-axis expansion rate N by the equation (9), even if the circuit is not strictly matched, the correction of the set value described in the first embodiment automatically sets the desired set value. Can be adjusted.

In this embodiment, instead of using the asynchronous clock, the second triangular wave TRI2 is generated from the pixel clock SCK, and the slope of TRI2 is compared with the linearly changing potential Vx to expand the time axis. It realizes the necessary phase shift. It is obvious that the same effect can be obtained if this slope is obtained by the first-order time constant, and the slope is not limited to the triangular wave.
Further, the comparison voltage Vx described in this embodiment is also the reference voltage V1.
The same effect can be obtained by making the voltage higher than the upper peak voltage and discharging C1 to lower Vx as shown in FIG.

[0050]

[Other Embodiments] Even if the present invention is applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), an apparatus (for example, a copying machine) Machine, facsimile machine, etc.).

[0051]

As described above, according to the present invention,
It is possible to provide a signal generation circuit and its method for accurately and easily setting the minimum and maximum pulse widths of an output signal and automatically performing the same setting.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a high-speed PWM circuit,

FIG. 2 is a timing chart explaining the operation of the high-speed PWM circuit,

FIG. 3 is a block diagram showing a configuration example of a high-speed PWM circuit according to an embodiment of the present invention,

FIG. 4 is a timing chart for explaining the operation of the high-speed PWM circuit of this embodiment,

FIG. 5 is a timing chart explaining a time axis expansion operation by DF / F,

FIG. 6 is a block diagram showing a configuration example of creating a CKM in the second embodiment according to the present invention;

7 is a timing chart for explaining the operation of the circuit shown in FIG.

FIG. 8 is a diagram explaining a shift amount of CKM,

9 is a diagram showing another method of creating the comparison voltage Vx shown in FIG.

Claims (9)

[Claims] 1. A generating means for generating an output signal having a pulse width corresponding to input data, an expanding means for expanding a cycle of the output signal to a predetermined multiple while holding a duty, and an expanding means for expanding the output signal. Measuring means for measuring the pulse width of the signal, and correction means for inputting setting data for setting the minimum and maximum pulse widths of the output signal, and correcting the setting data based on the pulse width obtained by the measuring means, A comparing means for comparing the pulse width obtained by the measuring means with the setting data corrected by the correcting means, and a pulse width of the output signal by controlling the generating means on the basis of the comparison result obtained by the comparing means. A signal generation circuit comprising: an adjusting unit for adjusting. 2. When the frequency of the output signal is fo and the predetermined multiple is N times, the expansion means expands the cycle based on a clock signal having a frequency difference of fo / N from the frequency of the output signal. The signal generation circuit according to claim 1, wherein 3. The expanding means is a D-flip-flop that expands the cycle of the output signal input to a data input terminal based on the clock signal input to a clock terminal. The signal generation circuit described in item 2. 4. The clock signal is generated by generating a triangular wave signal synchronized with the output signal, generating a reference signal whose voltage rises or falls at a predetermined slope, and comparing the triangular wave signal with the reference signal. 3. The signal generation circuit according to claim 2, further comprising a generation unit that generates 5. The measuring means includes a selecting means for selecting and measuring either the signal expanded by the expanding means or a signal obtained by dividing the frequency of the signal. The signal generation circuit described in 1. 6. The signal generation circuit according to claim 5, wherein the correction unit performs the correction based on a measurement result of the divided signal by the measurement unit. 7. The signal generation circuit according to claim 5, wherein the comparison means performs the comparison based on a measurement result of the non-divided signal by the measurement means. 8. An image processing apparatus comprising the signal generating circuit according to claim 1, and outputting a signal having a pulse width according to input image data. 9. A generating step of generating an output signal having a pulse width corresponding to input data, a decompressing step of decompressing a cycle of the output signal to a predetermined multiple while holding a duty, and decompressing in the decompressing step. A measuring step of measuring a pulse width of a signal, an input step of inputting setting data for setting a minimum and maximum pulse width of the output signal, and a correcting step of correcting the setting data based on the pulse width obtained in the measuring step. A comparison step of comparing the pulse width obtained in the measurement step with the setting data corrected in the correction step, and an adjustment step of adjusting the pulse width of the output signal based on the comparison result obtained in the comparison step. A method of generating a signal, comprising: