JPH09198881A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory with reduced power consumption by preventing current from flowing to a memory cell other than that accessed. SOLUTION: An address signal is applied to an NMOS memory cell through word lines WLN0, WLN1, WLN2 and WLN3 connected respectively to outputs X0, X2, X4 and X6 of an X decoder 3. On the other hand, an address signal is applied to a PMOS memory cell through word lines WLP0, WLP1, WLP2 and WLP3 connected respectively to outputs X1, X3, X5 and X7 of the X coder 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a memory with reduced power consumption and faster access time of memory cells.

[0002]

2. Description of the Related Art FIG. 15 shows a conventional semiconductor memory device R
The circuit block diagram of OM (READ ONLY MEMORY) 100 is shown.
In FIG. 15, a ROM 100 is an example of a ROM including a gate isolation type CMOS gate array, and includes a memory cell including an NMOS transistor (NMOS memory cell) and a memory cell including a PMOS transistor (PMOS memory cell). It is divided into and.

For NMOS memory cells, word lines W connected to the outputs X0 to X1 of the X decoder 1 respectively.
An address signal is applied via LN0 to WLN3.
On the other hand, since it is necessary to invert the address signal (word line logic) for the PMOS memory cell, the outputs X0 to X1 of the X decoder 1 are respectively supplied to the inverter circuits IVX0 to IVX0.
IVX3 is connected to form word lines WLP0 to WLP3. The X decoder 1 has address input terminals A2 and A3.
And X address signals XA1, X
A2 is given.

Word lines WLN0 to WLN3 and bit line B
A memory cell column composed of L0 and BL2 and an NMOS transistor is called a first column and a second column, and word lines WLP0 to WLP3 and bit lines BL1 and BL3.
The memory cell columns constituted by the PMOS transistors and the PMOS transistors are referred to as third and fourth columns.

Here, the bit lines BL0 and BL2 are N
The source electrodes of the MOS transistors C0 and C2 are connected, and the drain electrodes of the NMOS transistors C0 and C2 are commonly connected to the input of the inverting sense amplifier SA1.

The bit lines BL1 and BL3 are PM
The drain electrodes of the OS transistors C1 and C3 are connected, and the source electrodes of the PMOS transistors C1 and C3 are commonly connected to the input of the inverting sense amplifier SA2.

NMOS transistors C0, C2 and P
The MOS transistors C2 and C3 operate as a column selector CS. The input of the inverting sense amplifier SA1 is connected to the power supply potential VDD via the pull-up resistor R1, and the inverting sense amplifier SA2 is connected to the ground potential GND via the pull-down resistor R2.

The gate electrodes of the NMOS transistors C0 and C2 are connected to the outputs Y0 and Y2 of the Y decoder 3 for designating the Y address, and the gate electrodes of the PMOS transistors C1 and C3 are Y for designating the Y address.
Inverter circuit IVY is applied to outputs Y1 and Y3 of decoder 2.
1 and IVY3, respectively. In addition,
The Y decoder 2 is connected to address input terminals YA1 and YA0 which give Y address signals YA1 and YA2.

In the first column, memory cells are designated as M00, M10, M20, and M30 from the left side in the figure, and in the second column, memory cells are designated as M00 from the left side in the figure.
02, M12, M22, M32, and in the third column, memory cells are arranged from the left side of the drawing with M01, M11,
In the fourth column, M21, M31, and memory cells M03, M13, M23, and M33 from the left side in the figure.
And

In FIG. 15, an inverting sense amplifier SA is provided.
1 and the output of the inverting sense amplifier SA2 are selectors S
It is connected to EL and the output data DO is output from the selector SEL.
Is output.

In FIG. 15, the NMOS transistor N1
~ N8 source electrodes are commonly connected to GND, NM
The drain electrodes of the OS transistors N2 and N3 are commonly connected to the bit line BL0, and the NMOS transistors N5 and N6 and N7 and N8 are commonly connected to the bit line B.
L2.

Then, the PMOS transistors P1 to P8
Source electrodes of P are commonly connected to the power supply potential VDD, and P
The drain electrodes of the MOS transistors P2 and P3 are commonly connected to the bit line BL1, and the drain electrodes of the PMOS transistors P5 and P6, P7 and P8 are commonly connected to the bit line BL3.

This is a gate isolation type CMO.
This is a connection method that makes full use of the characteristics of the ROM configured by the basic cells of the S gate array.

FIG. 16A shows a circuit diagram of a memory cell portion extracted from the ROM 100, and FIG. 16B shows a layout diagram when the circuit is realized by a basic cell of a gate isolation type CMOS gate array. . FIG.
In FIG. 6B, the gate electrodes of the NMOS transistors N1 to N8 are arranged in the upper stage, and the gate electrodes of the PMOS transistors P1 to P8 are arranged in the lower stage.

Source / drain regions are formed in the lower layer outside the end portion along the longitudinal direction of the gate electrode. Although source / drain electrodes are formed on the source / drain regions, the illustration is omitted for simplicity.

Therefore, if the lower left side of the gate electrode of the NMOS transistor N1 is taken as the drain region in the figure,
The source region is on the right side of the lower layer of the gate electrode, and at the same time, it is also the source region of the NMOS transistor N5.
Therefore, in FIG. 16A, the NMOS transistor N
The configuration in which the source electrode of No. 1 and the source electrode of the NMOS transistor N5 are commonly connected to the GND is shown in FIG.
A contact hole CH is provided in a common source region with
This is achieved by forming the GND wiring which is the first layer wiring (first aluminum) on the contact hole. Also, N
In FIG. 16B, the configuration in which the gate electrode of the MOS transistor N5 and the gate electrode of the NMOS transistor N1 are connected to the word line WLN0 is NM.
The gate electrodes of the OS transistors N1 and N5 are connected to the first layer wiring (first aluminum) through the contact hole CH, and the first layer wiring (first aluminum) is through hole TH.
Via the word line WL which is the second layer wiring (second aluminum)
It is connected to N0.

Further, in FIG. 16B, the drain region of the NMOS transistor N1 is connected to the bit line BL0 through the contact hole CH. Incidentally, the connection of the other parts is similarly made by using the contact hole CH and the through hole TH, and the description thereof will be omitted.

Here, the contact hole CH is an opening hole formed in the insulating layer for connecting the electrode and the semiconductor region to the wiring, and the through hole TH is between the wirings, for example, the first layer wiring (first layer wiring). This is an opening hole formed in the insulating layer for connecting between the aluminum) and the second layer wiring (second aluminum). In FIG. 16B, the contact hole CH is shown by a white square, and the through hole TH is shown by a square having an X mark.

As described above, the connection method in which the common wirings are integrated is a connection method utilizing the characteristics of the ROM constituted by the basic cells of the gate isolation type CMOS gate array.

Further, since the electrode and the semiconductor region and the wiring are connected through the contact hole CH, the arrangement of the contact hole CH can be changed to change the connection between the electrode and the semiconductor region and the wiring. The gate isolation type C does not need to change the layout.
RO composed of basic cells of MOS gate array
This is a feature of M.

Here, as shown in FIG. 15, the memory cell M
The gate electrodes of 00, M02, and M12 are word lines WLN
Since it is connected to 0 and WLN1, it is turned on when the corresponding word line is selected. As a result, the input of the inverting sense amplifier SA1 becomes "L", that is, 0, and the output becomes "H", that is, 1.

Further, the memory cells M01, M11, M2
1, the gate electrodes of M33 are word lines WLP0 to WLP3.
Since each of them is connected to, the corresponding word line is turned on when the corresponding word line is selected. As a result, the input of the inverting sense amplifier SA2 becomes "H", that is, 1
The output is "L", that is, 0. The memory cell M
When 31, M03, M13 and M33 are accessed, the output of the inverting sense amplifier SA2 becomes 1.

Therefore, in the circuit configuration shown in FIG. 15, the memory cells M00, M02, M12, M31, M0.
The output data DO becomes 1 when 3, M13 and M33 are accessed, and the output data DO becomes 0 when other memory cells are accessed.

In the ROM 100 described above, the NMOS
The word line for the memory cell and the word line for the PMOS memory cell are activated at the same time. For example, when the output X0 of the X decoder 1 becomes active, the word line WLN
0 and WLP0 both become active and the memory cell M
The transistors 00, M02, and M01 are simultaneously turned on. At this time, the column selector CS changes the bit line BL
If 1 is selected, that is, the third column, the memory cell M01 will be accessed, and the current naturally flows through the PMOS transistor P1. However, the bit line not selected by the column selector CS is selected. BL
If 0 is in the charging state, NMO of memory cell M00
A discharge current flows through the S transistor N1. If the bit line BL0 is in the charged state, the memory cell M02
A discharge current flows through the NMOS transistor N5.

[0025]

Since the conventional semiconductor memory device is configured as described above, the discharge current flows in the memory cell of the conductive channel opposite to the memory cell being accessed, and the power is wasted. Was sometimes consumed.

The present invention has been made to solve the above problems, and prevents a current from flowing in a memory cell other than the memory cell being accessed, thereby reducing the power consumption of the semiconductor memory device. I will provide a.

[0027]

According to a first aspect of the present invention, there is provided a semiconductor memory device comprising: an N-type column in which N-type memory cells having N-channel transistors as transmission gates are arranged; and P-channel transistors as transmission gates. And a P-type column in which P-type memory cells are arranged and N for accessing the N-type memory cells.
Type memory cell word line, a P-type memory cell word line for accessing the P-type memory cell, and an X decoder for designating the X address of the N-type memory cell and the P-type memory cell In the device, the X-decoder has a first output terminal for outputting a "high potential" enable signal and a second output terminal for outputting a "low potential" enable signal, and the N-type memory cell word The line is connected to the first output terminal, and the P-type memory cell word line is connected to the second output terminal.

A semiconductor memory device according to a second aspect of the present invention is an N-type column in which N-type memory cells having N-channel transistors as transmission gates are arranged,
A P-type column in which P-type memory cells having a P-channel transistor as a transmission gate are arranged;
-Type memory cell word line for accessing the P-type memory cell, and P for accessing the P-type memory cell
In a semiconductor memory device including a word line for N-type memory cell and an X decoder for designating an X address of the N-type memory cell and the P-type memory cell, an output terminal of the X-decoder and the word line for N-type memory cell And a P-type memory cell word line, which receives a signal output from the output terminal of the X decoder and selectively outputs it as a "low potential" enable signal or a "high potential" enable signal. Means are provided, the N-type memory cell word line is connected to the transmission means so that the "high potential" enable signal is provided, and the P-type memory cell word line is connected to the "low potential" enable signal. Is connected to the transmission means.

In the semiconductor memory device according to a third aspect of the present invention, the transmission means has one electrode connected to the output terminal of the X decoder and the other electrode connected to the word line for the N-type memory cell. And an N-channel transistor for a transmission gate that functions as a transmission gate, an inverter circuit whose input is connected to the output terminal of the X decoder, one electrode connected to the output of the inverter circuit, and the other electrode connected to the P electrode.
For a transmission gate that is connected to a word line for a memory cell and functions as a transmission gate
A channel transistor, and the N-channel transistor for transmission gate and the P-channel transistor for transmission gate are controlled to operate complementarily.

In a semiconductor memory device according to a fourth aspect of the present invention, the transmission means has an inverter circuit having an input connected to an output terminal of the X decoder and one electrode connected to an output of the inverter circuit. , The other electrode is connected to the N-type memory cell word line, and one electrode is connected to an N-channel transistor for a transmission gate that functions as a transmission gate and the output terminal of the X decoder, and the other electrode is connected to the P electrode.
For a transmission gate that is connected to a word line for a memory cell and functions as a transmission gate
A channel transistor, and the N-channel transistor for transmission gate and the P-channel transistor for transmission gate are controlled to operate complementarily.

A semiconductor memory device according to a fifth aspect of the present invention is an N-type column in which N-type memory cells having N-channel transistors are arranged, and a P-type in which P-type memory cells having P-channel transistors are arranged. A column, a shared word line for sharing access to the N-type memory cell and the P-type memory cell, an X decoder for designating an X address of the N-type memory cell and the P-type memory cell, and the X
It is inserted between the output terminal of the decoder and the shared word line, receives the output signal output from the output terminal of the X decoder, and selectively serves as a "low potential" enable signal or a "high potential" enable signal. And a transmission means for outputting.

According to a sixth aspect of the present invention, in the semiconductor memory device, the N-type column comprises a first N-type memory cell in which one electrode of the N-channel transistor is connected to a first bit line. And a second column constituted by a second N-type memory cell in which one electrode of the N-channel transistor is connected to a second bit line, the P-type column Is a first P-channel transistor in which one electrode of the P-channel transistor is connected to a third bit line.
Type memory cell, and a fourth column configured by a second P type memory cell in which one electrode of the P channel transistor is connected to a fourth bit line. , The shared word line includes a first shared word line that shares access to the first N-type memory cell and the first P-type memory cell, the second N-type memory cell and the second P-type memory cell. Second shared access to memory cells
And a shared word line for controlling the transmission means by a control signal given from the outside.

A semiconductor memory device according to a seventh aspect of the present invention is an N-type column in which N-type memory cells having N-channel transistors as transmission gates are arranged,
A P-type column in which P-type memory cells having a P-channel transistor as a transmission gate are arranged;
Shared word line that shares access to the P-type memory cell and the P-type memory cell, an X decoder that specifies the X address of the N-type memory cell and the P-type memory cell, and the X-axis
It is inserted between the output terminal of the decoder and the shared word line, receives the output signal output from the output terminal of the X decoder, and selectively serves as a "low potential" enable signal or a "high potential" enable signal. An N-type column has a first bit line to which one electrode of the N-channel transistor is connected, and the P-type column has one electrode of the P-channel transistor. It has a second bit line connected.

In the semiconductor memory device according to claim 8 of the present invention, the transmission means has one electrode connected to the output terminal of the X decoder, the other electrode connected to the shared word line, and a transmission gate. Serving as an N-channel transistor for transmission gate, an inverter circuit having an input connected to the output terminal of the X decoder, one electrode connected to the output of the inverter circuit, and the other electrode connected to the shared word line And a transmission gate P-channel transistor functioning as a transmission gate, and the transmission gate N-channel transistor and the transmission gate P-channel transistor are controlled to operate complementarily.

According to a ninth aspect of the present invention, in the semiconductor memory device, the transmission means has an inverter circuit having an input connected to an output terminal of the X decoder and one electrode connected to an output of the inverter circuit. , The other electrode is connected to the shared word line, and one electrode is connected to the transmission gate N-channel transistor that functions as a transmission gate and the output terminal of the X decoder, and the other electrode is connected to the shared word line And a transmission gate P-channel transistor functioning as a transmission gate, and the transmission gate N-channel transistor and the transmission gate P-channel transistor are controlled to operate complementarily.

A semiconductor memory device according to a tenth aspect of the present invention is an N-type column in which N-type memory cells having N-channel transistors are arranged, and a P-type in which P-type memory cells having P-channel transistors are arranged. A column, a shared word line that shares access to the N-type memory cell and the P-type memory cell, the N-type memory cell and P
An X-decoder for designating the X-address of a memory cell, and an output signal which is inserted between the output terminal of the X-decoder and the shared word line and output from the output terminal of the X-decoder. The control signal and the output signal, "low potential" enable signal or "high potential"
And a gate circuit that selectively outputs as an enable signal.

In the semiconductor memory device according to claim 11 of the present invention, the gate circuit is an exclusive NOR circuit that fully swings its output from a power supply potential to a ground potential, and the control signal is the N-type. It is an inversion signal of a column selection signal that determines selection / non-selection of one of a column and a P-type column.

According to a twelfth aspect of the present invention, in the semiconductor memory device, the gate circuit is an exclusive OR circuit that fully swings its output from a power supply potential to a ground potential, and the control signal is the N-type. This is a column selection signal for determining whether to select one of the column and the P-type column.

[0039]

BEST MODE FOR CARRYING OUT THE INVENTION

<A. First Embodiment><A-1. Configuration of ROM 1000> FIG. 1 shows the ROM 1000 as the first embodiment of the semiconductor memory device according to the present invention.
The circuit block diagram of is shown. In FIG. 1, a ROM 1000 is an example of a ROM including a gate isolation type CMOS gate array, and includes a memory cell (NMOS memory cell) including an NMOS transistor and a PMOS.
It is divided into a memory cell (PMOS memory cell) including a transistor. Here, the NMOS transistor and the PMOS transistor function as a transmission gate.

An address signal is applied to the NMOS memory cell via word lines WLN0, WLN1, WLN2, WLN3 connected to the outputs X0, X2, X4, X6 of the X decoder 1, respectively. On the other hand, for the PMOS memory cells, the outputs X1, X3, X of the X decoder 1
5, word lines WLP0 and WL connected to X7, respectively
An address signal is applied via P1, WLP2 and WLP3.

The X decoder 1 has an address input terminal A
0, A2, A3, and X address signals XA0, XA1, XA2 are given from the respective terminals.

Word lines WLN0 to WLN3 and bit line B
A memory cell column composed of L0 and BL2 and an NMOS transistor is called a first column and a second column, and word lines WLP0 to WLP3 and bit lines BL1 and BL3.
The memory cell columns constituted by the PMOS transistors and the PMOS transistors are referred to as third and fourth columns.

Here, the bit lines BL0 and BL2 are N
The source electrodes of the MOS transistors C0 and C2 are connected, and the drain electrodes of the NMOS transistors C0 and C2 are commonly connected to the input of the inverting sense amplifier SA1.

The bit lines BL1 and BL3 are PM
The drain electrodes of the OS transistors C1 and C3 are connected, and the source electrodes of the PMOS transistors C1 and C3 are commonly connected to the input of the inverting sense amplifier SA2.

NMOS transistors C0, C2 and P
When one of the MOS transistors C1 and C3 is in the on state, the other is in the off state, and operates as a column selector CS that selects a column connected to the transistor in the on state. The input of the inverting sense amplifier SA1 is connected to the power supply potential VDD via the pull-up resistor R1, and the inverting sense amplifier SA2 is connected to the ground potential GND via the pull-down resistor R2.

The gate electrodes of the NMOS transistors C0 and C2 are connected to the outputs Y0 and Y2 of the Y decoder 3 that specifies the Y address, and the gate electrodes of the PMOS transistors C1 and C3 are the Y electrodes that specify the Y address.
Inverter circuit IVY is applied to outputs Y1 and Y3 of decoder 2.
1 and IVY3, respectively. In addition,
The Y decoder 2 is connected to the address input terminals A1 and A0, and the Y address signals YA1 and YA2 are supplied from the respective terminals.
Has been given.

In the first column, the memory cells are designated as M00, M10, M20, and M30 from the left side in the figure, and in the second column, the memory cells are designated as M00 from the left side in the figure.
02, M12, M22, M32, and in the third column, memory cells are arranged from the left side of the drawing with M01, M11,
In the fourth column, M21, M31, and memory cells M03, M13, M23, and M33 from the left side in the figure.
And

In FIG. 1, an inverting sense amplifier SA1
And the output of the inverting sense amplifier SA2 is the selector SE
Output data DO is output from the selector SEL connected to L.

The selector SEL is an inverting sense amplifier S.
A switching device that allows only one of the outputs of A1 and the inverting sense amplifier SA2 to pass, and switching control is performed using an address signal YA0 supplied to the Y decoder 2.

The NMOS memory cell is connected to the inverting sense amplifier SA1 and the PMOS memory cell is connected to the inverting sense amplifier SA2.
This is because it becomes necessary to change the characteristics of the sense amplifier.

Next, the connection state of the transistors in each memory cell will be described. In the first column of the ROM 1000 shown in FIG. 1, the gate electrode of the NMOS transistor N1 of the memory cell M00 is connected to the word line WLN0 (ON / OFF controllable connection), and the gate electrodes of the other NMOS transistors are connected to GND. (Connected to fixed OFF).

On the other hand, in the second column, the gate electrode of the NMOS transistor N5 of the memory cell M02 is connected to the word line WLN0 (ON / OFF controllable connection).
Then, the gate electrode of the NMOS transistor N6 of the memory cell M12 is connected to the word line WLN1 (ON / OFF controllable connection), and the gate electrode of the NMOS transistor of another memory cell is connected to GND (OFF fixed). ing.

In the third column, memory cell M31
The gate electrode of the PMOS transistor P4 of
It is connected to DD (fixed to OFF), and the gate electrode of the PMOS transistor of another memory cell is connected to a word line (connectable to ON / OFF control).

In the fourth column, memory cell M33
The gate electrode of the PMOS transistor P8 of the word line W
It is connected to LP3 (connectable to ON / OFF control), and the gate electrodes of PMOS transistors of other memory cells are connected to the power supply potential VDD (fixed to OFF).

<A-2. Device Operation> Here, the operation of the Y decoder 2 and the switching operation of the selector SEL will be described. The Y decoder 2 is a device that receives two address signals YA0 and YA1 and outputs signals to the outputs Y0 to Y3. FIG. 2 shows a truth table of the signals of the outputs Y0 to Y3 with respect to the address signals YA0 and YA1.

In FIG. 2, when the address signals YA0 and YA1 are both 0, the output Y0 is 1, and the others are 0.
It is. Address signal YA0 is 1, address signal YA1
Is 0, the output Y1 is 1, and the others are 0. When the address signal YA0 is 0 and YA1 is 1, the output Y2 is 1.
And the others are 0. Address signals YA0 and YA
When both 1s are 1, the output Y3 is 1, and the others are 0s.

Therefore, when the first column is selected, that is, when the output Y0 is 1, the address signal YA0 is 0. When the first column is selected, it is necessary to pass the output of the inverting sense amplifier SA1. Therefore, when the address signal YA0 becomes 0, the output of the inverting sense amplifier S13 is passed. Switch the signal path. This is the same when the second column is selected.

On the other hand, when the third column is selected, that is, when the output Y1 is 1, the address signal YA0 is 1
It is. When the third column is selected, it is necessary to pass the output of the inverting sense amplifier SA2. Therefore, when the address signal YA0 becomes 1, the output of the inverting sense amplifier SA2 is passed. Switch the signal path. This is the same when the fourth column is selected.

Next, the operation of the X decoder 3 will be described. The X decoder 3 has three address signals XA0 and XA.
1 and XA2 and outputs signals to outputs X0 to X7. FIG. 3 shows address signals XA0, XA1, and XA2.
7 shows a truth table of the signals of outputs X0 to X7 with respect to.

In FIG. 3, address signals XA0, XA
When 1 and XA2 are all 0, outputs X0, X1, X3, X
5, X7 is 1, and the others are 0. Address signal XA
When 0 is 1 and the others are 0, the outputs X3, X5, and X7 are 1, and the others are 0. Address signal XA1 is 1, other 0 is 0
, The outputs X1, X2, X3, X5, and X7 are 1, and the others are 0. Address signals XA0 and XA1 are 1,
When XA2 is 0, outputs X1, X5, X7 are 1,
Others are 0. Further, the address signal XA2 is 1 and the others are 0.
, The outputs X1, X3, X4, X5, and X7 are 1, and the others are 0. Address signals XA0 and XA2 are 1,
When XA1 is 0, outputs X1, X3, X7 are 1,
Others are 0. Address signals XA1 and XA2 are 1, XA
When 0 is 0, outputs X1, X3, X5, X6, and X7 are 1
And the others are 0. Address signals XA0, XA1,
When XA2 is all 1, the outputs X1, X3, and X5 are 1, and the others are 0.

The operation of the X decoder 3 is closely related to the operation of the Y decoder 2, and when the first and second columns are selected, that is, the outputs Y0, Y2 of the Y decoder 2 are 1.
In this case, the address signal YA0 is 0, any one of the outputs X0, X2, X4, and X6 of the X decoder 3 becomes 1, and the word lines WLN0, WLN1, WLN2, and WLN.
Any one of 3 becomes active. That is, the outputs X0, X2, X4, and X6 of the X decoder 3 are "High enable".

When the third and fourth columns are selected, that is, when the outputs Y1 and Y3 of the Y decoder 2 are 1, the address signal YA0 is 1, and the X decoder 3
One of the outputs X1, X3, X5, and X7 of 0 is set to 0, and the inverted output is performed to output the word lines WLP0 and WLP.
1, WLP2, WLP3 become active. The outputs X1, X3, X5, and X7 of the X decoder 3 are "Low enable".

<A-3. Characteristic Effects> As described above, according to the first embodiment of the semiconductor memory device of the present invention, the word line for the PMOS memory cell is activated and the bit line BL1 or BL3 is selected. In that case, that is, when the PMOS memory cell is being accessed, the word line for the NMOS memory cell does not become active.

For example, in the circuit configuration shown in FIG. 1, when the word line WLP0 becomes active, the word line W
Since LN0 does not become active, memory cell M00
The NMOS transistors N1 and N5 of the memory cells M2 and M02 are not turned on at the same time, and even if the bit lines BL0 and BL2 are in the charged state, the memory cell M
00 and M02 NMOS transistors N1 and N
No discharge current flows through 5.

Further, the word line for the NMOS memory cell becomes active, and the bit line BL0 or BL
When 2 is selected, that is, when accessing the NMOS memory cell, the word line for the PMOS memory cell is not activated.

Therefore, it is possible to prevent the current from flowing in the memory cell of the channel different from the memory cell being accessed and reduce the power consumption.

In the first embodiment of the semiconductor memory device according to the present invention described above, the ROM is composed of the gate isolation type CMOS gate array, but it is composed of the oxide film isolation type gate array. ROM
May be This also applies to other embodiments described below.

Further, in the above description, one bit data output DO (j) is realized by one basic cell, but one bit data output DO (j) is used by using a plurality of basic cells. ) Can be realized. In this case, the configurations of the column selector and the Y decoder are expanded.

<B. Second Embodiment><B-1. Configuration of ROM 2000> FIG. 4 shows a ROM 2000 as a second embodiment of the semiconductor memory device according to the present invention.
The circuit block diagram of is shown. Note that, in FIG. 4, the same components as those of the ROM 1000 described with reference to FIG. 1 are denoted by the same reference numerals, and redundant description will be omitted.

In FIG. 4, word lines WLN0 to WLN3 for the NMOS memory cells and outputs X0 to X0 of the X decoder 1 are used.
N channel transmission gate T between X3 and
GN0 to TGN3 are interposed, word lines WLP0 to WLP3 for MOS memory cells and inverter circuits IVX0 to IVX0.
P-channel transmission gates TGP0 to TGP3 are inserted between the output of IVX3 and the output.

The X decoder 1 has an address input terminal A
2 and A3, and X address signals XA0 and XA1 are given from the respective terminals.

N-channel transmission gate TG
The gates of N0 to TGN3 and the P channel transmission gates TGP0 to TGP3 are configured to be supplied with gate signals of the same logic, and the gate signals are supplied from the output of the inverter circuit IVPN. The input of the inverter circuit IVPN is connected to the address signal terminal, and the output of the inverter circuit IVPN is an inverted signal of the address signal YA0 given to the Y decoder 2.

<B-2. Device operation> When any of the outputs X0 to X3 of the X decoder 1 is 1, the inverter circuit I
Inverted by VX0-IVX3, the word line for the PMOS memory cell can be activated. At the same time, the word line for the NMOS memory cell can be activated. However, when the bit line BL1 or BL3 is selected, that is, when the PMOS memory cell is being accessed, the address signal YA0 is 1 and the output of the inverter circuit IVPN as described with reference to FIG. Is 0.

Therefore, since the P channel transmission gates TGP0 to TGP3 are turned on and all the N channel transmission gates TGN0 to TGN3 are turned off, one of the word lines WLP0 to WLP3 for the PMOS memory cell becomes active. , Word lines WLN0 to WLN for NMOS memory cells
3 does not change. That is, the previous state is held by the capacity of the word line.

For example, when accessing the memory cell M01, only the output X0 of the X decoder 1 becomes 1, the bit line BL1 is selected, and the P channel transmission gates TGP0 to TGP3 are turned on,
The word line WLP0 becomes active and the memory cell M0
A current will flow through the first PMOS transistor P1. Since the output X0 of the X decoder 1 is 1, the word line WLN0 can be activated, but all the N channel transmission gates TGN0 to TGN3 are OFF.
Since it is in the state, NM of the memory cells M00 and M02
The OS transistors N1 and N5 are not turned on at the same time, and even if the bit line BL0 and the bit line BL2 are in the charged state, the discharge current does not flow in the NMOS transistors N1 and N5 of the memory cells M00 and M02.

When any of the outputs X0 to X3 of the X decoder 1 is 1, it is inverted by the inverter circuits IVX0 to IVX3 and the word line for the PMOS memory cell can be activated. At the same time, the word line for the NMOS memory cell can be activated.
However, when the bit line BL0 or BL2 is selected, that is, when the NMOS memory cell is being accessed, the address signal YA0 is 0 and the output of the inverter circuit IVPN as described with reference to FIG. Is 1.

Therefore, since the N channel transmission gates TGN0 to TGN3 are turned on and all the P channel transmission gates TGP0 to TGP3 are turned off, any one of the word lines WLN0 to WLN3 for the NMOS memory cell becomes active. , Word lines WLP0 to WLP for PMOS memory cells
3 does not change. That is, the previous state is held by the capacity of the word line.

<B-3. Characteristic Effects> As described above, according to the second embodiment of the semiconductor memory device of the present invention, current is prevented from flowing in the memory cell of a channel different from the memory cell being accessed, and consumption is prevented. The power can be reduced.

When the PMOS memory cell is being accessed, the word line WLN for the NMOS memory cell is used.
Since 0 to WLN3 are electrically disconnected from the X decoder 1 by the N channel transmission gates TGN0 to TGN3, the load capacity of the X decoder 1 is smaller than that of the conventional ROM 100 described with reference to FIG. Become. As a result, the inverter circuits IVX0 to IVX1
The signal change speed of the outputs X0 to X3 of the X decoder 1 given to VX3 becomes faster. Therefore, there is also an effect that the access time to the PMOS memory cell becomes faster than that of the conventional ROM 100.

<C. Third Embodiment><C-1. Configuration of ROM 3000> FIG. 5 shows a ROM 3000 as a third embodiment of the semiconductor memory device according to the present invention.
The circuit block diagram of is shown. In FIG. 5, the same components as those of the ROM 1000 described with reference to FIG. 1 and the ROM 2000 described with reference to FIG. 4 are designated by the same reference numerals, and duplicate description will be omitted.

In FIG. 5, the X decoder 4 is an inverted output type decoder, and outputs a logic opposite to the output of the X decoder 1 shown in FIG. Therefore, since it is necessary to invert the address signal (word line logic) for the NMOS memory cell, the inverter circuits IVX0 to IVX3 are connected to the outputs X0 to X1 of the X decoder 4 to connect the word line W, respectively.
It is set to LN0 to WLN3. On the other hand, the outputs X0 to X1 of the X decoder 1 are directly applied as address signals to the PMOS memory cells. The X decoder 4 is connected to the address input terminals A2 and A3, and the X address signals XA0 and XA1 are supplied from the respective terminals.

Then, the word lines WLN0 to WLN3 for the NMOS memory cells and the inverter circuits IVX0 to IVX are used.
N-channel transmission gates TGN0 to TGN3 are inserted between the outputs of the X decoder 3 and the outputs of the X decoder 1, and P between the outputs X0 to X3 of the X decoder 1 and the word lines WLP0 to WLP3.
Channel transmission gates TGP0 to TGP3
Is inserted.

<C-2. Device operation> If any of the outputs X0 to X3 of the X decoder 1 is 0, the word line for the PMOS memory cell can be activated. At the same time, the word lines for the NMOS memory cells can be activated by being inverted by the inverter circuits IVX0 to IVX3. However, when the bit line BL1 or BL3 is selected, that is, when the PMOS memory cell is being accessed, the address signal YA0 is 1 and the output of the inverter circuit IVPN as described with reference to FIG. Is 0.

Therefore, since the P channel transmission gates TGP0 to TGP3 are in the ON state and all the N channel transmission gates TGN0 to TGN3 are in the OFF state, one of the word lines WLP0 to WLP3 for the PMOS memory cell becomes active. , Word lines WLN0 to WLN for NMOS memory cells
3 does not change. That is, the previous state is held by the capacity of the word line.

For example, when accessing the memory cell M01, only the output X0 of the X decoder 1 becomes 0, the bit line BL1 is selected, and the P channel transmission gates TGP0 to TGP3 are turned on.
The word line WLP0 becomes active and the memory cell M0
A current will flow through the first PMOS transistor P1. Since the output X0 of the X decoder 1 is 0, it can be inverted by the inverter circuit IVX0 to activate the word line WLN0, but since all the N-channel transmission gates TGN0 to TGN3 are in the OFF state, the memory cells M00 and M02 are The NMOS transistors N1 and N5 are not turned on at the same time, and even if the bit line BL0 and the bit line BL2 are in the charged state, the discharge current does not flow in the NMOS transistors N1 and N5 of the memory cells M00 and M02.

When any of the outputs X0 to X3 of the X decoder 1 is 1, the inverter circuits IVX0 to IVX are provided.
Inverted by 3, the word line for the NMOS memory cell can be activated. At the same time, PMO
The word line for the S memory cell can also be activated. However, when the bit line BL0 or BL2 is selected, that is, when the NMOS memory cell is being accessed, the address signal YA0 is 0 and the output of the inverter circuit IVPN as described with reference to FIG. Is 1.

Therefore, since the N-channel transmission gates TGN0 to TGN3 are turned on and all the P-channel transmission gates TGP0 to TGP3 are turned off, any one of the word lines WLN0 to WLN3 for the NMOS memory cell becomes active. , Word lines WLP0 to WLP for PMOS memory cells
3 does not change. That is, the previous state is held by the capacity of the word line.

<C-3. Characteristic Effects> As described above, according to the third embodiment of the semiconductor memory device of the present invention, it is possible to prevent current from flowing in a memory cell of a channel different from that of the memory cell being accessed, and to reduce consumption. The power can be reduced.

In the ROM 3000 according to the present invention, generally, the final output stage of the X-decoder of a small-scale ROM is often composed of a NAND circuit. Therefore, the ROM 3000 using the inverted output type X decoder 4 has an NA
The output of the ND circuit can be used as the output of the X decoder, and it can be said that the configuration is suitable for a small-scale ROM.
Generally, the final output stage of a small-scale ROM X decoder is often composed of an inverter circuit that inverts the output of the NAND circuit. This is because the inverter circuit is used as a word line driver, and the X decoder 1 of the ROM 2000 described as the second embodiment of the present invention corresponds to this.

When the PMOS memory cell is being accessed, the word line WLN for the NMOS memory cell is used.
Since 0 to WLN3 are electrically isolated from the X decoder 1 by the N-channel transmission gates TGN0 to TGN3, the load capacity of the X decoder 1 is reduced and the access time to the PMOS memory cell is the same as that of the conventional ROM 100. The ROM2 described in the second embodiment of the present invention has the effect of being faster than the ROM2.
The same as 000.

<D. Fourth Embodiment><D-1. Configuration of ROM 4000> FIG. 6 shows a ROM 4000 as a fourth embodiment of the semiconductor memory device according to the present invention.
The circuit block diagram of is shown. In FIG. 6, the same components as those of the ROM 1000 described with reference to FIG. 1 and the ROM 2000 described with reference to FIG. 4 are designated by the same reference numerals, and duplicate description will be omitted.

In FIG. 6, the word line WL common to the NMOS memory cell and the PMOS memory cell is used.
Address signals are provided through 0, WL1, WL2, and WL3.

Therefore, in the ROM 4000, the word lines WL0 to WL3, the bit lines BL0 and BL2, and NM.
A memory cell column composed of OS transistors is referred to as a first and second column, and a memory cell column composed of word lines WL0 to WL3, bit lines BL1 and BL3 and PMOS transistors is referred to as third and fourth columns. I call it.

Then, N-channel transmission gates TGN0 to TGN3 are interposed between the word lines WL0 to WL3 and the outputs X0 to X3 of the X decoder 1 and, in parallel with them, inverter circuits IVX0 to IVX.
P-channel transmission gates TGP0 to TGP3 are inserted between the output of X3 and the output of X3.

<D-2. Device operation> When any of the outputs X0 to X3 of the X decoder 1 is 1, the inverter circuit I
Inverted by VX0 to IVX3, the word line can be activated for the PMOS memory cell.
At the same time, the word line can be activated for the NMOS memory cell. However, the bit line BL1
Or if BL3 is selected, ie PMO
When the S memory cell is being accessed, the address signal YA0 is 1 and the output of the inverter circuit IVPN is 0 as described with reference to FIG.

Therefore, since the P channel transmission gates TGP0 to TGP3 are in the ON state and all the N channel transmission gates TGN0 to TGN3 are in the OFF state, the word lines WL0 to WL3 are in the N state.
It is active for only one of the MOS memory cells and not for the NMOS memory cells.

For example, when accessing the memory cell M01, only the output X0 of the X decoder 1 becomes 1, the bit line BL1 is selected, and the P channel transmission gates TGP0 to TGP3 are turned on,
The word line WL0 becomes active with respect to the memory cell M01, and a current flows through the PMOS transistor P1. Since the output X0 of the X decoder 1 is 1, the word line WL0 can be activated also for the memory cells M00 and M02, but since all the N-channel transmission gates TGN0 to TGN3 are in the OFF state, the memory cell M00 and Even if the bit line BL0 and bit line BL2 are in a charged state without the NMOS transistors N1 and N5 of M02 being turned on at the same time, no discharge current flows through the NMOS transistors N1 and N5 of the memory cells M00 and M02. .

When any of the outputs X0 to X3 of the X decoder 1 is 1, it is inverted by the inverter circuits IVX0 to IVX3, and the word line can be activated for the PMOS memory cell. At the same time, the word line can be activated for the NMOS memory cell. However, when the bit line BL0 or BL2 is selected, that is, when the NMOS memory cell is being accessed, the address signal YA0 is 0 and the inverter circuit IVPN is used as described with reference to FIG.
Output is 1.

Therefore, since N channel transmission gates TGN0 to TGN3 are turned on and all P channel transmission gates TGP0 to TGP3 are turned off, one of word lines WL0 to WL3 is active only for the NMOS memory cell. , And is not active for PMOS memory cells.

When the PMOS memory cell is being accessed, the word lines WLN0 to WN for the NMOS memory cell are used.
LN3 is an N-channel transmission gate TGN
The load capacitance of the X decoder 1 is smaller than that of the conventional ROM 100 described with reference to FIG. 15 because it is electrically separated from the X decoder 1 by 0 to TGN3. As a result, the inverter circuits IVX0 to IVX3
The signal change speeds of the outputs X0 to X3 of the X decoder 1 given to the are increased. Therefore, there is also an effect that the access time to the PMOS memory cell becomes faster than that of the conventional ROM 100.

Here, FIG. 7A shows a circuit diagram of a memory cell portion extracted from the ROM 4000, and FIG. 7B shows a layout when the circuit is realized by a basic cell of a gate isolation type CMOS gate array. The figure is shown.

As shown in FIG. 7A, in the first column, the gate electrode of the NMOS transistor N1 of the memory cell M00 is connected to the word line WL0 (ON / OFF controllable connection), and the other NMOS transistor is connected. The gate electrode of is connected to GND (fixed to OFF).

On the other hand, in the second column, the gate electrode of the NMOS transistor N5 of the memory cell M02 is connected to the word line WL0 (ON / OFF controllable connection),
The gate electrode of the NMOS transistor N6 of the memory cell M12 is connected to the word line WL1 (ON / OFF controllable connection), and the gate electrodes of the NMOS transistors of the other memory cells are connected to GND (fixed OFF). .

In the third column, the memory cell M31
The gate electrode of the PMOS transistor P4 of
It is connected to DD (fixed to OFF), and the gate electrode of the PMOS transistor of another memory cell is connected to a word line (connectable to ON / OFF control).

In the fourth column, the memory cell M33
The gate electrode of the PMOS transistor P8 of the word line W
It is connected to L3 (connectable to ON / OFF control), and the gate electrodes of the PMOS transistors of other memory cells are connected to the power supply potential VDD (fixed to OFF).

Then, the NMOS transistors N1 to N8
Source electrodes are commonly connected to GND, drain electrodes of NMOS transistors N2 and N3 are commonly connected to bit line BL0, and NMOS transistors N5 and N6, N7 and N8 are commonly connected to bit line BL2. ing.

The source electrodes of the PMOS transistors P1 to P8 are commonly connected to the power supply potential VDD, and PM
The drain electrodes of the OS transistors P2 and P3 are commonly connected to the bit line BL1, and the drain electrodes of the PMOS transistors P5 and P6, P7 and P8 are commonly connected to the bit line BL3. This is a connection method that takes advantage of the characteristics of a ROM that is composed of basic cells of a gate isolation type CMOS gate array.

In FIG. 7B, the gate electrodes of the NMOS transistors N1 to N8 are arranged in the upper stage, and the gate electrodes of the PMOS transistors P1 to P8 are arranged in the lower stage.

Source / drain regions are formed in the lower layer outside the end portion along the longitudinal direction of the gate electrode. Although source / drain electrodes are formed on the source / drain regions, the illustration is omitted for simplicity.

Therefore, if the lower left side of the gate electrode of the NMOS transistor N1 is taken as the drain region in the figure,
The source region is on the right side of the lower layer of the gate electrode, and at the same time, it is also the source region of the NMOS transistor N5.
Therefore, in FIG. 16A, the NMOS transistor N
The configuration in which the source electrode of No. 1 and the source electrode of the NMOS transistor N5 are commonly connected to the GND is shown in FIG.
A contact hole CH is provided in a common source region with
This is achieved by forming the GND wiring which is the first layer wiring (first aluminum) on the contact hole. Also, N
In the configuration shown in FIG. 16B, the gate electrode of the MOS transistor N5 and the gate electrode of the NMOS transistor N1 are connected to the word line WL0.
The gate electrodes of the S transistors N1 and N5 are connected to the first layer wiring (first aluminum) via the contact hole CH, and the first layer wiring (first aluminum) is connected to the second layer wiring (first aluminum) via the through hole TH. 2 aluminum) word line WL0
It is achieved by being connected to.

Further, in FIG. 16B, the drain region of the NMOS transistor N1 is connected to the bit line BL0 by the contact hole CH. Incidentally, the connection of the other parts is similarly made by using the contact hole CH and the through hole TH, and the description thereof will be omitted.

Here, the contact hole CH is an opening hole formed in the insulating layer for connecting the electrode and the semiconductor region to the wiring, and the through hole TH is between the wirings, for example, the first layer wiring (first layer wiring). This is an opening hole formed in the insulating layer for connecting between the aluminum) and the second layer wiring (second aluminum). In FIG. 7B, the contact hole CH is shown by a white square and the through hole TH is shown by a square having a cross mark.

As described above, the gate isolation type C
ROM realized by basic cell of MOS gate array
In the layout of 4000, the gate electrode of the NMOS transistor N5 and the upper part of the gate electrode of the PMOS transistor P5, the gate electrode of the NMOS transistor N2 and the upper part of the gate electrode of the PMOS transistor P2, the gate electrode of the NMOS transistor N7 and the PM.
No word line is provided above the gate electrode of the OS transistor P7, the gate electrode of the NMOS transistor N4, and the gate electrode of the PMOS transistor P4.

Therefore, this region can be used for other purposes such as penetrating the signal line of the random logic on the LSI element.

<D-3. Characteristic Effects> As described above, according to the fourth embodiment of the semiconductor memory device of the present invention, a current is prevented from flowing in a memory cell of a channel different from that of the memory cell being accessed, and consumption is prevented. The power can be reduced.

In addition, an NMOS memory cell and a PMOS
Since a common word line is used for the memory cells, the number of word lines is halved compared to the conventional ROM 100, and the area conventionally used for word line wiring is used for other purposes. Therefore, the area of the memory cell region can be reduced and the device can be miniaturized.

<D-4. Modification> In addition, R described above
In the OM4000, the configuration in which the X decoder 1 is used is shown, but the inverted output type X decoder 4 described with reference to FIG. 5 may be used. In that case, since it is necessary to invert the address signal (word line logic) for the NMOS memory cell, the inverter circuits IVX0 to IVX3 are connected to the outputs X0 to X1 of the X decoder 4 to connect the word line W, respectively.
It is set to LN0 to WLN3. On the other hand, the outputs X0 to X1 of the X decoder 1 are directly applied to the PMOS memory cells as address signals.

<E. Fifth Embodiment><E-1. Structure of ROM 5000> FIG. 8 shows a ROM 5000 as a fifth embodiment of the semiconductor memory device according to the present invention.
The circuit block diagram of is shown. Note that, in FIG. 8, the same components as those of the ROM 1000 described with reference to FIG. 1 and the ROM 2000 described with reference to FIG. 4 are denoted by the same reference numerals, and redundant description will be omitted.

In FIG. 8, the output X0 of the X decoder 5,
X1, X2, X3, X4, X5, X6, and X7 have transmission gate circuits B0, B1, B2, and
B3, B4, B5, B6, and B7 are connected, and word lines WL0, WL1, WL2, WL3, WL4, WL5, and W are connected to the transmission gate circuits B0 to B7, respectively.
L6 and WL7 are connected.

The X decoder 5 has an address input terminal A
1, A2, A3, and X address signals XA0, XA1, XA2 are given from the respective terminals.

The structure of the transmission gate circuit is
The transmission gate circuit B6 will be described as an example. As shown in FIG. 8, in the transmission gate circuit B6, an N-channel transmission gate TGN6 is interposed between the output X6 of the X decoder 5 and the word line WL6, and in parallel with this, the word line WL6 and the inverter circuit. A P-channel transmission gate TGP6 is inserted between the output of the IVX6 and the output. This structure is the same in other transmission gate circuits.

The gates of the N-channel transmission gates TGN0 to TGN3 and the P-channel transmission gates TGP0 to TGP3 are configured to be supplied with gate signals of the same logic, and the gate signals are output from the output of the inverter circuit IVPN. Given. The input of the inverter circuit IVPN is connected to the address signal terminal A0, and the output of the inverter circuit IVPN is an inverted signal of the address signal YA0 given to the Y decoder 2.

Here, the memory cell columns composed of the word lines WL0 to WL7, the bit lines BL0 and BL2, and the NMOS transistors are referred to as the first and second columns,
Word lines WL0 to WL7 and bit lines BL1 and BL3
The memory cell columns constituted by the PMOS transistors and the PMOS transistors are referred to as third and fourth columns.

Next, the connection state of the transistors in each memory cell will be described. In the first column of the ROM 5000 shown in FIG. 8, the gate electrode of the NMOS transistor N1 of the memory cell M00 is connected to the word line WL0 (ON / OFF controllable connection), and the gate electrodes of the other NMOS transistors are connected to GND. (Connected to fixed OFF).

On the other hand, in the second column, the gate electrode of the NMOS transistor N5 of the memory cell M02 is connected to the word line WL1 (ON / OFF controllable connection),
The gate electrode of the NMOS transistor N6 of the memory cell M12 is connected to the word line WL3 (ON / OFF controllable connection), and the gate electrode of the NMOS transistor of another memory cell is connected to GND (OFF fixed connection). .

In the third column, memory cell M01
The gate electrode of the NMOS transistor P1 of the word line W
Connected to L0 (connectable to ON / OFF control), and connected the gate electrode of the NMOS transistor P2 of the memory cell M11 to word line WL2 (connected to ON / OFF controllable).
Then, the gate electrode of the NMOS transistor P3 of the memory cell M21 is connected to the word line WL5 (ON / OFF controllable connection), and the gate electrode of the PMOS transistor P4 of the memory cell M31 is connected to the power supply potential VDD (OFF fixed connection). )doing.

In the fourth column, memory cell M33
The gate electrode of the PMOS transistor P8 of the word line W
L7 is connected (ON / OFF controllable connection), and the gate electrodes of the PMOS transistors of other memory cells are connected to the power supply potential VDD (fixed to OFF).

Then, the NMOS transistors N1 to N8
Source electrodes are commonly connected to GND, drain electrodes of NMOS transistors N2 and N3 are commonly connected to bit line BL0, and NMOS transistors N5 and N6, N7 and N8 are commonly connected to bit line BL2. ing.

The source electrodes of the PMOS transistors P1 to P8 are commonly connected to the power supply potential VDD, and PM
The drain electrodes of the OS transistors P2 and P3 are commonly connected to the bit line BL1, and the drain electrodes of the PMOS transistors P5 and P6, P7 and P8 are commonly connected to the bit line BL3. This is a connection method that takes advantage of the characteristics of a ROM that is composed of basic cells of a gate isolation type CMOS gate array.

Here, FIG. 9A shows a circuit diagram of a memory cell portion extracted from the ROM 5000, and FIG. 9B shows a layout when the circuit is realized by a basic cell of a gate isolation type CMOS gate array. The figure is shown. In FIG. 9B, NMOS transistors N1 to N
Each gate electrode of 8 is formed in an array on the upper stage, and PM
The gate electrodes of the OS transistors P1 to P8 are arranged in the lower stage.

Source / drain regions are formed in the lower layer outside the end portion along the longitudinal direction of the gate electrode. Although source / drain electrodes are formed on the source / drain regions, the illustration is omitted for simplicity.

Therefore, if the left side of the lower layer of the gate electrode of the NMOS transistor N1 is used as the drain region in the figure,
The source region is on the right side of the lower layer of the gate electrode, and at the same time, it is also the source region of the NMOS transistor N5.
Therefore, in FIG. 9A, the NMOS transistor N1
9 and the source electrode of the NMOS transistor N5 are commonly connected to GND.
In (b), the contact hole CH is provided in the common source region of the NMOS transistors N1 and N5, and
This is achieved by forming a GND wiring, which is a layer wiring (first aluminum), on the contact hole.

Here, in the configuration in which the gate electrode of the NMOS transistor N1 is connected to the word line WL0, in FIG. 9B, the gate electrode of the NMOS transistor N1 is connected to the first layer wiring via the contact hole CH. First layer wiring (first aluminum) connected to (first aluminum)
Is the second layer wiring (second aluminum) through the through hole TH
This is achieved by the configuration connected to the word line WL0.

The structure in which the gate electrode of the NMOS transistor N5 is connected to the word line WL1 is
In FIG. 9B, the gate electrode of the NMOS transistor N5 is connected to the first layer wiring (first aluminum) via the contact hole CH, and the first layer wiring (first aluminum) is connected to the through hole TH. This is achieved by a structure connected to the word line WL1 which is the second layer wiring (second aluminum).

In FIG. 9B, the drain region of the NMOS transistor N1 is connected to the bit line BL0 by the contact hole CH. Incidentally, the connection of the other parts is similarly made by using the contact hole CH and the through hole TH, and the description thereof will be omitted.

<E-2. Device operation> First, the X decoder 5
Will be described. The X decoder 5 receives the three address signals XA0, XA1 and XA2 and outputs X0 to X7.
10 is a device for outputting a signal to the address signal X.
The truth table of the signals of outputs X0 to X7 for A0, XA1, and XA2 is shown.

In FIG. 10, address signals XA0, XA
When all of A1 and XA2 are 0, the output X0 is 1, and the others are 0. When the address signal XA0 is 1 and the others are 0, the output X1 is 1 and the others are 0. Address signal XA
If 1 is 1 and the other 0 is 0, the output X2 is 1 and the others are 0.
It is. Address signal XA0, XA1 is 1, XA2 is 0
, The output X3 is 1, and the others are 0. When the address signal XA2 is 1 and the others are 0, the output X4 is 1 and the others are 0. When the address signals XA0 and XA2 are 1 and XA1 is 0, the output X5 is 1 and the others are 0. When the address signals XA1 and XA2 are 1 and XA0 is 0, the output X6 is 1 and the others are 0. When the address signals XA0, XA1 and XA2 are all 1, the output X7 is 1, and the others are 0.

The operation of the X decoder 5 is closely related to the operation of the Y decoder 2 described with reference to FIG. 2, and when the first and third columns are selected, that is, the Y decoder 2 is selected.
If the outputs Y0 and Y1 of 1 are 1, the address signal YA1
Is 0, and the outputs X0, X2, X4, X of the X decoder 5 are
Any one of 6 becomes 1.

When the second and fourth columns are selected, that is, when the outputs Y2 and Y3 of the Y decoder 2 are 1, the address signal YA1 is 1 and the X decoder 5 is used.
One of the outputs X1, X3, X5, and X7 becomes 1.

As described above, the ROM according to the present invention
In 5000, the word lines WL0 to WL7 are made independent, and the transmission gate circuits B0 to B are respectively provided.
Since 7 is connected, one word line may be connected to each of the NMOS transistor and the PMOS transistor. However, one word line is 2
It is configured so as not to be connected to one NMOS transistor or two PMOS transistors.

For example, when accessing the memory cell M00, only the output X0 of the X decoder 5 becomes 1, the bit line BL0 is selected, and the N-channel transmission gates TGN0 to TGN7 are turned on,
The word line WL0 becomes active with respect to the memory cell M00, and a current flows through the NMOS transistor N1. For the memory cell M02, the word line WL1
Is not active, the gate does not turn on, and no discharge current flows even if the bit line BL2 is in a charged state. Moreover, since the output X0 of the X decoder 5 is 1, the word line WL0 is not activated for the memory cell M01.

When accessing the memory cell M02, only the output X1 of the X decoder 5 becomes 1, the bit line BL2 is selected, and the N-channel transmission gates TGN0 to TGN7 are turned on.
The word line WL1 becomes active with respect to the memory cell M02, and a current flows through the NMOS transistor N5. Moreover, since the output X1 of the X decoder 5 is 1, the word line WL0 is not activated for the memory cell M01.

As described above, the ROM 5000 according to the present invention
In the above, since the transistors of the memory cells of the same channel are not turned on at the same time, current can be prevented from flowing to the memory cells other than the memory cell being accessed, and the power consumption can be reduced.

<E-3. Characteristic Functions and Effects> As described above, according to the fifth embodiment of the semiconductor memory device of the present invention, the transistors of the memory cells of the same channel are not turned on at the same time. Current can be prevented from flowing to the memory cells other than the above, and power consumption can be reduced.

<F. Sixth Embodiment><F-1. Configuration of ROM 6000> FIG. 11 shows a ROM 600 as a sixth embodiment of the semiconductor memory device according to the present invention.
The circuit block diagram of 0 is shown. Note that in FIG. 11, the same components as those of the ROM 1000 described with reference to FIG. 1 and the ROM 5000 described with reference to FIG. 8 are denoted by the same reference numerals, and redundant description will be omitted.

In FIG. 11, the output X of the X decoder 6
0, X1, X2, X3, X4, X5, X6, X7,
Transmission gate circuits B0, B1, B respectively
2, B3, B4, B5, B6, B7 are connected, and word lines WL0, WL1, WL2, WL3, WL4, WL are connected to the transmission gate circuits B0-B7, respectively.
5, WL6, WL7 are connected.

The X decoder 6 has an address input terminal A
1, A2, A3, and X address signals XA0, XA1, XA2 are given from the respective terminals.

The gates of the N-channel transmission gates TGN0 to TGN3 and the P-channel transmission gates TGP0 to TGP3 are configured to be supplied with gate signals of the same logic, and the gate signals are output from the output of the inverter circuit IVPN. Given. The input of the inverter circuit IVPN is connected to the address signal terminal A0, and the output of the inverter circuit IVPN is a signal input from the signal terminal A0, that is, an inverted signal of the column selection signal (or Y address signal).

Word lines WL0 to WL7 and bit line BL0
A memory cell column composed of a memory cell and an NMOS transistor is referred to as a first column and a second column in order from the top, and the word line WL0
The memory cell columns composed of WL7, bit line BL1, and PMOS transistor are referred to as the third and fourth columns in order from the top.

The bit line BL0 is connected to the source electrode of the NMOS transistor C0, and the drain electrode of the NMOS transistor C0 is connected to the input of the inverting sense amplifier SA1.

The bit line BL1 is connected to the drain electrode of the PMOS transistor C1, and the source electrode of the PMOS transistor C1 is commonly connected to the inverting sense amplifier S.
It is connected to the input of A2.

NMOS transistor C0 and PMOS
The transistor C1 operates as a column selector CS.

In addition, NMOS transistors C0 and C
The gate electrode of 1 is connected to the output of the inverter circuit IVA0, and the input of the inverter circuit IVA0 is connected to the address signal terminal A0.

The inverter circuit IVA0 may be omitted by supplying the control signal to the column selector CS from the inverter circuit IVPN.

<F-2. Device operation> The operation of the X decoder 6 is governed by the value of the address signal XA0, and when the first and second columns are selected, that is, when the output of the inverter circuit IVA0 is 1, the address input terminal A0 is 0. However, the address signal XA0, that is, the address input terminal A1 becomes 0 or 1, and any one of the outputs X0 to X7 of the X decoder 6 becomes 1.

When the third and fourth columns are selected, that is, when the output of the inverter circuit IVA0 is 0, the address input terminal A0 is 1, but the address signal XA0, that is, the address input terminal A1 is 0. Alternatively, it becomes 1, and any one of the outputs X0 to X7 of the X decoder 6 becomes 1.

As described above, the ROM according to the present invention
In 6000, the word lines WL0 to WL7 are made independent, and the transmission gate circuits B0 to B are respectively provided.
Since 7 is connected, one word line may be connected to each of the NMOS transistor and the PMOS transistor. However, one word line is 2
It is configured so as not to be connected to one NMOS transistor or two PMOS transistors.

For example, when accessing the memory cell M00, the address signal XA0 becomes 0 and only the output X0 of the X decoder 6 becomes 1. At this time, the bit line BL
0 and BL2 are simultaneously selected, the N-channel transmission gates TGN0 to TGN7 are turned on, the word line WL0 becomes active with respect to the memory cell M00, and a current flows through the NMOS transistor N1. For the memory cell M02, the word line W
Since L1 is not active, the gate does not turn on and no current flows. Moreover, since the output X0 of the X decoder 6 is 1, the word line WL0 is not activated for the memory cell M01.

When the memory cell M02 is accessed, the address signal XA0 becomes 1 and the X decoder 6
Only the output X1 of 1 becomes 1. At this time, the bit line BL0
And BL2 are simultaneously selected, the N-channel transmission gates TGN0 to TGN3 are turned on,
The word line WL1 becomes active with respect to the memory cell M02, and a current flows through the NMOS transistor N5. For the memory cell M00, the word line WL0
Is not active, the gate does not turn on and no current flows.

Thus, the ROM 6000 according to the present invention
In the above, since the transistors of the memory cells of the same channel are not turned on at the same time, current can be prevented from flowing to the memory cells other than the memory cell being accessed, and the power consumption can be reduced.

Further, one bit line is provided for each of the NMOS memory cell and one bit line for the PMOS memory cell, and the number of bit lines can be reduced by half.

Here, FIG. 12A shows a circuit diagram of a memory cell portion extracted from the ROM 6000, and FIG. 12B shows a layout when the circuit is realized by a basic cell of a gate isolation type CMOS gate array. The figure is shown. In FIG. 12A, the NMOS transistor N1
And a drain electrode of N3 are commonly connected to the bit line BL0, an NMOS transistor N5
And a drain electrode of N6 are commonly connected to the bit line BL0, an NMOS transistor N7
The configuration in which the drain electrodes of N8 and N8 are commonly connected to the bit line BL0 is as shown in FIG.
A contact hole CH is provided in the common drain region of each of the NMOS transistors N2 and N3, N5 and N6, N7 and N8, and is a first layer wiring (first aluminum) GND.
This is achieved by forming a wiring on the contact hole.

This is the same in the PMOS memory cell region as well, and the PMOS transistors P2, P3 and P5 are provided.
And P6 and P7 and P8 have common contact regions CH in the common source regions, and the first layer wiring (first aluminum)
It is achieved by forming the GND wiring on the contact hole.

<F-3. Characteristic Effects> As described above, according to the sixth embodiment of the semiconductor memory device of the present invention, the transistors of the memory cells of the same channel are not turned on at the same time. Current can be prevented from flowing to the memory cells other than the above, and power consumption can be reduced.

Further, since the number of bit lines can be reduced by half, the region which has been conventionally used for bit line wiring can be used for other purposes, for example, other wirings can be penetrated or CMOS gates can be used. Reduce the cell area of the array
It is possible to downsize the device.

<G. Seventh Embodiment><G-1. Configuration of ROM 7000> FIG. 13 shows a semiconductor memory device according to a seventh embodiment of the present invention, in which a ROM 700
The circuit block diagram of 0 is shown. Note that, in FIG. 13, the same components as those of the ROM 4000 described with reference to FIG. 6 are designated by the same reference numerals, and redundant description will be omitted.

In FIG. 13, word lines WL0 to WL3
And the outputs X0 to X3 of the X decoder 1 are provided with exclusive NOR circuits XNOR0 to XNOR3.

Exclusive NOR circuit XNOR0-X
One input of each NOR3 is connected to the outputs X0 to X3 of the X decoder 1, and the other input is connected to the output of the inverter circuit IVPN.

An exclusive OR circuit may be used instead of the exclusive NOR circuit. In that case, the inverter circuit IVPN becomes unnecessary.

<G-2. Device operation> When the first and second columns are selected by the Y decoder 2 operation described with reference to FIG. 3, that is, the outputs Y0 and Y2 of the Y decoder 2
Is 1, the address signal YA0 is 0, and therefore the output of the inverter circuit IVPN is 1. On the other hand, when the second and third columns are selected, that is, when the outputs Y1 and Y3 of the Y decoder 2 are 1, the address signal YA0 is 1, so that the output of the inverter circuit IVPN is 0.

For example, when the first and second columns are selected, the output of the inverter circuit IVPN is 1, and X
If any of the decoders X0 to X3 is 1, the word line becomes active for the NMOS memory cell and PM
It is not active for OS memory cells.

When the third and fourth columns are selected, the output of the inverter circuit IVPN is 0, and if any of the X decoders X0 to X3 is 1, the word line corresponds to the PMOS memory cell. Become active and NMO
It is not active for S memory cells.

For example, when the memory cell M01 is accessed, only the output X0 of the X decoder 1 becomes 1 and the bit line BL1 is selected and the inverter circuit IVPN is selected.
Of the memory cell M01.
Becomes active for the PMOS transistor P1
An electric current will flow through. Since the output of the inverter circuit IVPN is 0, the word line WL0 is the memory cell M0.
0, M02 are not active and memory cell M
00 and M02 NMOS transistors N1 and N
5 does not turn on at the same time, and bit line BL0
Even if the bit line BL2 is in the charged state, no discharge current flows in the NMOS transistors N1 and N5 of the memory cells M00 and M02.

Here, the exclusive NOR circuit XNO
For R0 to XNOR3, by using an exclusive NOR circuit with a full swing output, the output of which swings fully from the power supply voltage VDD to the ground voltage GND (0V), the transistors of the NMOS memory cell and the PMOS memory cell are configured. The ON resistance becomes low, and high-speed reading becomes possible.

<G-3. Characteristic Effects> As described above, according to the seventh embodiment of the semiconductor memory device of the present invention, it is possible to prevent a current from flowing in a memory cell of a channel different from that of the memory cell being accessed, thereby reducing power consumption. It can be reduced.

By using the exclusive swing circuit of full swing output, the ON resistance of the transistors forming the NMOS memory cell and the PMOS memory cell is lowered, and high-speed reading is possible.

Further, the NMOS memory cell and the PMOS
Since a common word line is used for the memory cells, the number of word lines is halved compared to the conventional ROM 100, and the area conventionally used for word line wiring is used for other purposes. Therefore, the area of the memory cell region can be reduced and the device can be miniaturized.

<H. Modifications of Embodiment> Modifications of the first to seventh embodiments of the semiconductor memory device according to the present invention described above will be described below with reference to FIG.

In the first to seventh embodiments of the semiconductor memory device according to the present invention, the example in which the present invention is applied to the ROM is shown.
The present invention is not applied only to ROM, but to RAM
(RANDOM ACCESS MEMORY) and FIFO (FIRST-IN FIR
It is also applicable to writable memory such as ST-OUT) memory.

FIG. 14A shows the NMOS transistor N1.
1 shows the structure of a writable memory with 0s. FIG.
In (a), the NMOS transistor N10 has a gate electrode connected to the word line WL, a drain electrode connected to the bit line BL, and a data holding means DH connected to the source electrode. In this way, the word line WL and the bit line BL
NM functioning as a transmission gate by
Needless to say, the present invention can be applied to any configuration in which the OS transistor N10 is accessed and data is written and read via the NMOS transistor N10. The description of the data holding means DH and the writing means (write word line or write bit line) for the data holding means DH will be omitted.

FIG. 14B shows the structure of a writable memory having one PMOS transistor P10. In FIG. 14B, the PMOS transistor P10 functioning as a transmission gate has a gate electrode connected to the word line WL and a source electrode connected to the bit line BL,
Data holding means DH is connected to the drain electrode. It goes without saying that the present invention can be applied to such a configuration as well.

FIG. 14C shows the NMOS transistor N2.
2 shows the configuration of a writable memory with 0 and N30. In FIG. 14C, the NMOS transistor N20 functioning as a transmission gate has a word line WL connected to a gate electrode, a bit line BL connected to a drain electrode, and a source electrode connected to an NMOS transistor N30. The source electrode is connected to the ground potential GND, and the gate electrode is connected to the data holding means DH. It goes without saying that the present invention can be applied to such a configuration as well.

FIG. 14D shows the PMOS transistor P2.
2 shows the structure of a writable memory with 0 and P30. In FIG. 14D, the PMOS transistor P20 functioning as a transmission gate has a gate electrode connected to the word line WL, a source electrode connected to the bit line BL, and a PMOS transistor P30 connected to the drain electrode. The drain electrode is connected to the power supply potential VDD, and the gate electrode is connected to the data holding means DH. It goes without saying that the present invention can be applied to such a configuration as well.

[0184]

According to the semiconductor memory device of the first aspect of the present invention, the X decoder outputs the first output terminal for outputting the "high potential" enable signal and the "low potential" enable signal. A second output terminal, the word line for N-type memory cells is connected to the first output terminal, and the word line for P-type memory cells is connected to the second output terminal. The word line and the P-type memory cell word line can be activated independently. Therefore, when an N-type memory cell is being accessed, by operating the X decoder so that only the N-type memory cell word line is activated, a channel (conductivity type) different from that of the memory cell being accessed. It is possible to prevent a current from flowing through the memory cell of 1) and reduce power consumption.

According to a second aspect of the semiconductor memory device of the present invention, a transmission means is provided between the output terminal of the X decoder and the N-type memory cell word line and the P-type memory cell word line. By connecting the N-type memory cell word line so that a “high potential” enable signal is applied and connecting the P-type memory cell word line so that a “low potential” enable signal is applied, In the word line for the memory cell and the word line for the P-type memory cell,
A "high potential" enable signal and a "low potential" enable signal can be selectively applied, respectively. Therefore,
When the N-type memory cell is being accessed, by operating the X decoder so that only the N-type memory cell word line is activated, a current is supplied to a memory cell of a channel different from the memory cell being accessed. Can be prevented from flowing and power consumption can be reduced.

According to the semiconductor memory device of the third aspect of the present invention, the "high potential" enable signal and the "low potential" enable signal are respectively supplied to the N-type memory cell word line and the P-type memory cell word line. And a p-type memory cell is accessed when the n-type memory cell is accessed, and an n-type memory is accessed when the p-type memory cell is accessed. Since the cell can be electrically isolated from the X decoder, the load capacity of the X decoder can be reduced and the access time to the memory cell can be speeded up.

According to the semiconductor memory device of the fourth aspect of the present invention, when the X decoder is an inverting output type decoder, that is, when it is a small scale memory,
It is possible to obtain a realistic configuration of the transmission means for selectively applying the "high potential" enable signal and the "low potential" enable signal to the N-type memory cell word line and the P-type memory cell word line, respectively, and to obtain the N-type memory cell word line. When accessing a memory cell, the P-type memory cell
When the P-type memory cell is being accessed, the N-type memory cell can be electrically isolated from the X-decoder, so that the load capacity of the X-decoder is reduced and the access time to the memory cell is reduced. It can speed up.

According to the fifth aspect of the semiconductor memory device of the present invention, the N-type memory cell and the P-type memory cell are accessed by the shared word line, and the output terminal of the X decoder and the shared word line are connected. By providing the transmission means in, the "high potential" enable signal and the "low potential" enable signal can be selectively applied.
Therefore, it is possible to prevent current from flowing in the memory cell of a channel different from that of the memory cell being accessed, reduce power consumption, and reduce the number of word lines in half. The region used for the line wiring can be used for other purposes, and the area of the memory cell region can be reduced to downsize the device.

According to the semiconductor memory device of the sixth aspect of the present invention, since the transmission means is controlled by the control signal given from the outside, any one of the first to fourth columns is used by using the control signal. By selecting
A "low potential" enable signal or a "high potential" enable signal can be applied to the first shared word line and the second shared word line according to the selected column. Therefore, the transistors of the memory cells of the same channel are not turned on at the same time, so that current can be prevented from flowing to the memory cells other than the memory cell being accessed and the power consumption can be reduced.

According to the seventh aspect of the semiconductor memory device of the present invention, the N-type memory cell and the P-type memory cell are accessed by the shared word line, and between the output terminal of the X decoder and the shared word line. By providing the transmission means in, the "high potential" enable signal and the "low potential" enable signal can be selectively applied.
Therefore, current can be prevented from flowing to the memory cell of a channel different from the memory cell being accessed, and power consumption can be reduced. Since one electrode of the N-channel transistor of the N-type column is connected to the first bit line and one electrode of the P-channel transistor of the P-type column is connected to the second bit line, The number can be halved, the area that was conventionally used for bit line wiring can be used for other purposes, and the area of the memory cell area can be reduced to miniaturize the device. It will be possible.

According to the semiconductor memory device of the eighth aspect of the present invention, the realistic configuration of the transmission means for selectively applying the "high potential" enable signal and the "low potential" enable signal to the shared word line, respectively. And the P-type memory cell is electrically disconnected from the X decoder when the N-type memory cell is accessed, and the N-type memory cell is electrically disconnected from the X decoder when the P-type memory cell is accessed. Since the load capacity of the X decoder can be reduced, the access time to the memory cell can be shortened.

According to the semiconductor memory device of the ninth aspect of the present invention, when the X decoder is an inverting output type decoder, that is, when it is a small-scale memory,
A practical configuration of transmission means for complementarily providing the "high potential" enable signal and the "low potential" enable signal to the shared word line is obtained, and
When the N-type memory cell is accessed, the P-type memory cell is accessed. When the P-type memory cell is accessed, the N-type memory cell is accessed.
Since the memory cell can be electrically isolated from the X decoder, the load capacity of the X decoder can be reduced and the access time to the memory cell can be speeded up.

According to the semiconductor memory device of the tenth aspect of the present invention, a gate circuit is provided between the output terminal of the X decoder and the shared word line, and the output signal output from the output terminal of the X decoder is provided. , It selectively outputs to the shared word line as the "high potential" enable signal or the "low potential" enable signal, so that the current is prevented from flowing to the memory cell of the channel different from the memory cell being accessed, and the consumption is prevented. The power can be reduced.

According to the eleventh aspect of the semiconductor memory device of the present invention, since the gate circuit is an exclusive NOR circuit that fully swings its output from the power supply potential to the ground potential, an N-type memory cell and a P-type memory cell are provided. The ON resistance of the transistor forming the memory cell becomes low, and high-speed reading is possible. Further, since the common word line is used for the N-type memory cell and the P-type memory cell,
Since the number of word lines is halved, the area that was previously used for word line wiring can be used for other purposes, and the area of the memory cell area can be reduced to downsize the device. It becomes possible to do.

According to the twelfth aspect of the semiconductor memory device of the present invention, the gate circuit is an exclusive OR circuit that swings its output fully from the power supply potential to the ground potential. The ON resistance of the transistor forming the P-type memory cell becomes low, and high-speed reading becomes possible. Further, since the common word line is used for the N-type memory cell and the P-type memory cell,
Since the number of word lines is halved, the area that was previously used for word line wiring can be used for other purposes, and the area of the memory cell area can be reduced to downsize the device. It becomes possible to do.

[Brief description of drawings]

FIG. 1 is a first embodiment of a semiconductor memory device according to the present invention;
2 is a circuit configuration diagram illustrating FIG.

FIG. 2 is a diagram illustrating an operation of a Y decoder.

FIG. 3 is a diagram for explaining the operation of the X decoder.

FIG. 4 is a second embodiment of the semiconductor memory device according to the present invention.
It is a circuit diagram explaining.

FIG. 5 is a third embodiment of the semiconductor memory device according to the present invention.
It is a circuit diagram explaining.

FIG. 6 is a fourth embodiment of the semiconductor memory device according to the present invention.
It is a circuit diagram explaining.

FIG. 7 is a fourth embodiment of the semiconductor memory device according to the present invention.
FIG. 6 is a diagram illustrating a layout of FIG.

FIG. 8 is a fifth embodiment of the semiconductor memory device according to the present invention.
It is a circuit diagram explaining.

FIG. 9 is a fifth embodiment of the semiconductor memory device according to the present invention.
FIG. 6 is a diagram illustrating a layout of FIG.

FIG. 10 is a diagram illustrating the operation of the X decoder.

FIG. 11 is a circuit diagram illustrating a sixth embodiment of the semiconductor memory device according to the present invention.

FIG. 12 is a diagram for explaining the layout of the sixth embodiment of the semiconductor memory device according to the present invention.

FIG. 13 is a circuit diagram illustrating a seventh embodiment of a semiconductor memory device according to the present invention.

FIG. 14 is a diagram illustrating a modification of the first to seventh embodiments of the semiconductor memory device according to the present invention.

FIG. 15 is a circuit diagram illustrating a conventional semiconductor memory device.

FIG. 16 is a diagram illustrating a layout of a conventional semiconductor memory device.

[Explanation of symbols]

CH contact hole, TH through hole, B0
B7 Transmission gate circuit.

Claims (12)

[Claims] 1. An N-type column in which N-type memory cells having N-channel transistors as transmission gates are arranged, a P-type column in which P-type memory cells having P-channel transistors as transmission gates are arranged, and the N-type column. An N-type memory cell word line for accessing the memory cell, a P-type memory cell word line for accessing the P-type memory cell, and an X address of the N-type memory cell and the P-type memory cell are designated. In the semiconductor memory device, the X decoder has a first output terminal for outputting a “high potential” enable signal and a second output terminal for outputting a “low potential” enable signal. , The N-type memory cell word line is connected to the first output terminal, and the P-type memory cell word line is the second output terminal. The semiconductor memory device characterized in that it is connected to the force terminal. 2. An N-type column in which N-type memory cells having N-channel transistors as transmission gates are arranged, a P-type column in which P-type memory cells having P-channel transistors as transmission gates are arranged, and the N-type. An N-type memory cell word line for accessing the memory cell, a P-type memory cell word line for accessing the P-type memory cell, and an X address of the N-type memory cell and the P-type memory cell are designated. In the semiconductor memory device, the output terminal of the X decoder is inserted between the output terminal of the X decoder and the word line for the N-type memory cell and the word line for the P-type memory cell. Receives the output signal and selectively outputs it as a "low potential" enable signal or a "high potential" enable signal The N-type memory cell word line is connected to the transmission means so that the "high potential" enable signal is given, and the P-type memory cell word line is the "low potential". A semiconductor memory device connected to the transmission means so that an enable signal is applied. 3. The transmission means has one electrode connected to an output terminal of the X decoder, and the other electrode connected to the N-type memory cell word line,
An N-channel transistor for a transmission gate that functions as a transmission gate, an inverter circuit whose input is connected to the output terminal of the X decoder, one electrode connected to the output of the inverter circuit, and the other electrode of which is the P-type memory. A transmission gate P-channel transistor connected to a cell word line and functioning as a transmission gate, wherein the transmission gate N-channel transistor and the transmission gate P-channel transistor are controlled to operate complementarily. Item 2. The semiconductor memory device according to item 2. 4. The transmission means includes an inverter circuit having an input connected to an output terminal of the X decoder, and one electrode connected to an output of the inverter circuit, the other electrode connected to the word for the N-type memory cell. A transmission gate N-channel transistor connected to a line and functioning as a transmission gate, and one electrode connected to the output terminal of the X decoder, and the other electrode connected to the P-type memory cell word line,
3. The semiconductor memory device according to claim 2, further comprising: a transmission gate P-channel transistor that functions as a transmission gate, wherein the transmission gate N-channel transistor and the transmission gate P-channel transistor are controlled to operate complementarily. 5. An N-type column in which N-type memory cells having N-channel transistors as transmission gates are arranged, a P-type column in which P-type memory cells having P-channel transistors as transmission gates are arranged, and said N-type A shared word line that shares access to the memory cell and the P-type memory cell, an X decoder that specifies the X address of the N-type memory cell and the P-type memory cell, an output terminal of the X decoder, and the shared word line And a transmission means that is interposed between the X-decoder and the output terminal of the X-decoder and selectively outputs the output signal as a "low potential" enable signal or a "high potential" enable signal. . 6. The N-type column includes a first column including a first N-type memory cell in which one electrode of the N-channel transistor is connected to a first bit line, and the N-channel transistor. A second column composed of a second N-type memory cell having one electrode connected to a second bit line, the P-type column is configured such that one electrode of the P-channel transistor is A third column composed of the first P-type memory cell connected to the third bit line, and a second P-type memory cell in which one electrode of the P-channel transistor is connected to the fourth bit line And a fourth column constituted by, wherein the shared word line shares a first shared word line that shares access to the first N-type memory cell and the first P-type memory cell, and A second N-type memory cell and a second Of and a second common word line to share access to the P-type memory cell, the control signal supplied from the outside, the semiconductor memory device according to claim 5, wherein the controlling the transmission means. 7. An N-type column in which N-type memory cells having N-channel transistors as transmission gates are arranged, a P-type column in which P-type memory cells having P-channel transistors as transmission gates are arranged, and said N-type A shared word line that shares access to the memory cell and the P-type memory cell, an X decoder that specifies the X address of the N-type memory cell and the P-type memory cell, an output terminal of the X decoder, and the shared word line And a transmission means for receiving an output signal output from the output terminal of the X decoder and selectively outputting it as a “low potential” enable signal or a “high potential” enable signal. The type column has a first bit line to which one electrode of the N-channel transistor is connected. The P-type column, a semiconductor memory device having a second bit line in which one of the electrodes of the P-channel transistor is connected. 8. The transmission means includes an N-channel transistor for a transmission gate, one electrode of which is connected to an output terminal of the X decoder and the other electrode of which is connected to the shared word line, and which functions as a transmission gate. An inverter circuit having an input connected to the output terminal of the X decoder, and one electrode connected to the output of the inverter circuit, the other electrode connected to the shared word line, and a P channel for a transmission gate that functions as a transmission gate 8. The semiconductor memory device according to claim 5, further comprising a transistor, wherein the transmission gate N-channel transistor and the transmission gate P-channel transistor are controlled to operate in a complementary manner. 9. The transmission means has an inverter circuit having an input connected to an output terminal of the X decoder, one electrode connected to an output of the inverter circuit, and the other electrode connected to the shared word line. A transmission gate N-channel transistor functioning as a transmission gate, and one electrode connected to the output terminal of the X decoder, the other electrode connected to the shared word line, and a transmission gate P-channel functioning as a transmission gate 8. The semiconductor memory device according to claim 5, further comprising a transistor, wherein the transmission gate N-channel transistor and the transmission gate P-channel transistor are controlled to operate in a complementary manner. 10. An N-type column in which N-type memory cells having N-channel transistors are arranged, a P-type column in which P-type memory cells having P-channel transistors are arranged, said N-type memory cell and P-type memory A shared word line that shares access to a cell, an X decoder that specifies an X address of the N-type memory cell and the P-type memory cell, and an interposed between an output terminal of the X decoder and the shared word line. A gate circuit that receives an output signal output from the output terminal of the X decoder and a control signal given from the outside, and selectively outputs the output signal as a "low potential" enable signal or a "high potential" enable signal A semiconductor memory device comprising: 11. The gate circuit is an exclusive NOR circuit that fully swings its output from a power supply potential to a ground potential, and the control signal selects or deselects one of the N-type column and the P-type column. 11. The semiconductor memory device according to claim 10, wherein the semiconductor memory device is an inversion signal of a column selection signal for determining. 12. The gate circuit is an exclusive OR circuit that fully swings its output from a power supply potential to a ground potential, and the control signal selects or deselects one of the N-type column and the P-type column. 11. The semiconductor memory device according to claim 10, which is a column selection signal for determining.