JPH09191131A - Optical assembly - Google Patents

Optical assembly

Info

Publication number
JPH09191131A
JPH09191131A JP361196A JP361196A JPH09191131A JP H09191131 A JPH09191131 A JP H09191131A JP 361196 A JP361196 A JP 361196A JP 361196 A JP361196 A JP 361196A JP H09191131 A JPH09191131 A JP H09191131A
Authority
JP
Japan
Prior art keywords
optical
semiconductor element
mount substrate
optical semiconductor
terrace
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP361196A
Other languages
Japanese (ja)
Inventor
Koji Yoshida
幸司 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP361196A priority Critical patent/JPH09191131A/en
Publication of JPH09191131A publication Critical patent/JPH09191131A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Light Receiving Elements (AREA)
  • Led Device Packages (AREA)
  • Led Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve the accuracy of securing an optical semiconductor element on a mount board to be mounted with an optical element in the direction of bonding, and prevent a metal alloy for bonding from flowing out to the light receiving surface or light emitting surface of the semiconductor element, by forming a step on the mount board in the position where the optical semiconductor element is to be secured. SOLUTION: A terrace 4 is formed on a silicon substrate 3 by etching, and a lower clad layer is formed. The lower clad layer is polished to the level of the terrace 4, and then a core layer is deposited. A pattern is formed, and recesses 5 of step structure, a waveguide 8 and a mating mark 7 are formed. An upper clad layer is formed, and then the terrace 4 is exposed. An optical semiconductor element 1 is fixed on the terrace 4 for alignment. Because of the presence of the recesses 5 for joining, a metal alloy film 6 for bonding stays within the recesses 5, and is prevented from flowing out to the end faces of semiconductor elements to be mounted. The semiconductor elements 2 are secured in an element mounting sections, and are connected with each other using a gold wire.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は光加入者システム，
光インタコネクトシステム等に適用する低コスト光モジ
ュール，光アセンブリに関する。BACKGROUND OF THE INVENTION The present invention relates to an optical subscriber system,
The present invention relates to a low-cost optical module and optical assembly applied to an optical interconnect system and the like.

【０００２】[0002]

【従来の技術】従来の技術は、回路実装学会誌Ｖol.１
０ Ｎo.５(１９９５）において伊藤らの報告がある。
光半導体モジュールは、光通信システムを構成する基本
デバイスであり、これらは、発光素子であるレーザダイ
オード（ＬＤ），受光素子であるフォトダイオードと光
ファイバ、あるいは光導波路、これらを光学的に結合さ
せるレンズ、及びこれらを固定し実装する基板から構成
される。この中で、光半導体素子とマウント基板を固定
する場合には、マウント基板上に電極パターンを形成
し、かつ光半導体素子の裏面にも金属膜による電極パタ
ーンを形成し固着する。2. Description of the Related Art The conventional technology is Vol.
0 No. 5 (1995) reported by Ito et al.
An optical semiconductor module is a basic device that constitutes an optical communication system. These are a laser diode (LD) which is a light emitting element, a photodiode which is a light receiving element and an optical fiber, or an optical waveguide, and these are optically coupled. It is composed of a lens and a substrate for fixing and mounting these. Among these, when fixing the optical semiconductor element and the mount substrate, an electrode pattern is formed on the mount substrate, and an electrode pattern made of a metal film is also formed and fixed on the back surface of the optical semiconductor element.

【０００３】光半導体素子を光導波路または光ファイバ
に低損失に光結合させる場合、光軸に対して１μｍ以下
の位置合わせの精度が必要となる。マウント基板に対し
て平行な方向に対しては、合わせマークをマウント基板
及び光半導体素子に形成し、近赤外光を透過させ、同時
に合わせマークを観察し、位置合わせを行う方法やソル
ダの表面張力を利用したセルフアライメント等の方法が
低コスト実装方法として提案されている。マウント基板
に対して垂直な方向に対しては、基板側にスタンドオ
フ，半導体素子側にノッチを設けてそれらを接触させて
高さ方向の位置合わせを行う方法が提案されている。When the optical semiconductor element is optically coupled to the optical waveguide or the optical fiber with low loss, the alignment accuracy of 1 μm or less with respect to the optical axis is required. In the direction parallel to the mount substrate, a method of forming alignment marks on the mount substrate and the optical semiconductor element, transmitting near-infrared light, observing the alignment marks at the same time, and performing alignment, and the surface of the solder Methods such as self-alignment using tension have been proposed as low-cost mounting methods. In the direction perpendicular to the mount substrate, a method has been proposed in which standoffs are provided on the substrate side and notches are provided on the semiconductor element side and they are brought into contact with each other to perform alignment in the height direction.

【０００４】[0004]

【発明が解決しようとする課題】本発明の目的は、マウ
ント基板に垂直な方向、すなわち、半導体素子とマウン
ト基板を接合する方向の固定精度の改善と固定のための
金属合金の半導体素子の受／発光面への流出を防ぐ光ア
センブリ構造を提案することにある。SUMMARY OF THE INVENTION An object of the present invention is to improve the fixing accuracy in the direction perpendicular to the mount substrate, that is, in the direction of joining the semiconductor device and the mount substrate, and to receive the semiconductor element of a metal alloy for fixing. / To propose an optical assembly structure that prevents outflow to the light emitting surface.

【０００５】[0005]

【課題を解決するための手段】上記目的を達成するため
に、光半導体素子を搭載するマウント基板上の光半導体
素子を固定する位置に段差構造を形成した。その段差構
造の上段に光半導体素子を直接接触させ、固定のための
金属膜は、段差構造の下段にのみ接合させる。このよう
に、固定位置を決定するための段と接合するための段と
を分けて形成することにより、光半導体素子の固定精度
を向上させることが可能となる。また、段があるため
に、溶融し段に広がった金属合金が光半導体素子端面に
流出することを防ぐことも可能となる。In order to achieve the above object, a step structure is formed at a position where an optical semiconductor element is mounted on a mount substrate on which the optical semiconductor element is mounted. The optical semiconductor element is brought into direct contact with the upper step of the step structure, and the metal film for fixing is bonded only to the lower step of the step structure. Thus, by separately forming the step for determining the fixing position and the step for joining, it is possible to improve the fixing accuracy of the optical semiconductor element. Further, since there are steps, it is possible to prevent the metal alloy melted and spread in the steps from flowing out to the end surface of the optical semiconductor element.

【０００６】[0006]

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

（実施例１）本発明の実施例を図１に示す。この実施例
の製造方法は、先ず、エッチングによりシリコン基板３
にテラス４を形成し、火炎堆積法により下部クラッド層
を形成する。次に堆積したクラッド膜をテラスの高さま
で研磨した後、コア層を堆積し、ドライエッチングでパ
ターン形成を行い、段差構造の凹部５，導波路８，合わ
せマーク７を形成する。上部クラッド層を再び火炎堆積
法によって形成した後、ドライエッチングでＳｉテラス
部を露出させる。シリコンと石英のエッチングレートの
差により、エッチングは半導体素子が接触するシリコン
表面で停止する。一方凹部の深さ(２μｍ〜８μｍ）
は、エッチングレートが毎分０.１〜１μｍ程度に制御
できるため、時間管理で再現性よく制御することが可能
である。次に、電子ビーム蒸着法によりチタン，白金，
金からなる電極１０を形成し、パタニングする。固定の
ための金属合金膜６（ＡｕＳｎ薄膜）は、光半導体素子
電極上に蒸着法により下部の段の容積より大きくならな
いような厚さ(３μｍ〜９μｍ)で形成する。(Embodiment 1) An embodiment of the present invention is shown in FIG. In the manufacturing method of this embodiment, first, the silicon substrate 3 is etched by etching.
The terrace 4 is formed on the substrate 4 and the lower clad layer is formed by the flame deposition method. Next, after polishing the deposited clad film to the height of the terrace, a core layer is deposited and a pattern is formed by dry etching to form a recess 5, a waveguide 8 and an alignment mark 7 having a step structure. After the upper clad layer is formed again by the flame deposition method, the Si terrace portion is exposed by dry etching. Due to the difference in etching rate between silicon and quartz, etching stops at the silicon surface with which the semiconductor element is in contact. On the other hand, the depth of the recess (2 μm to 8 μm)
Since the etching rate can be controlled to about 0.1 to 1 μm per minute, it can be controlled with good reproducibility by time management. Next, titanium, platinum, and
The electrode 10 made of gold is formed and patterned. The metal alloy film 6 (AuSn thin film) for fixing is formed on the optical semiconductor element electrode by vapor deposition with a thickness (3 μm to 9 μm) that is not larger than the volume of the lower step.

【０００７】光半導体素子１は、赤外光透過法により半
導体素子と基板に形成した合わせマーク７を赤外線カメ
ラによって同時に観測し平面方向の位置合わせを行った
後、加重を加えつつ加熱し、光半導体素子１を位置固定
用の段４に固定する。光半導体素子とマウント基板の基
板に垂直な方向の位置は、位置固定用の段４と光半導体
素子の接触面で決定される。また、固定のための金属合
金膜６は、接合用の段５があるため、その内に留まり、
光半導体素子端面への流出は防がれる。次に、同様な方
法で半導体素子２を素子搭載部に固着する。さらに、そ
れぞれの半導体素子を金ワイヤ９で接続し、電気的接続
をとり、実施例１を完成する。In the optical semiconductor element 1, the alignment marks 7 formed on the semiconductor element and the substrate are simultaneously observed by an infrared camera by the infrared light transmission method and aligned in the plane direction. The semiconductor element 1 is fixed to the step 4 for fixing the position. The position of the optical semiconductor element and the mount substrate in the direction perpendicular to the substrate is determined by the contact surface between the step fixing step 4 and the optical semiconductor element. Further, the metal alloy film 6 for fixing remains in the step 5 for joining,
Outflow to the end surface of the optical semiconductor element is prevented. Next, the semiconductor element 2 is fixed to the element mounting portion by the same method. Further, the respective semiconductor elements are connected by the gold wires 9 and electrically connected to complete the first embodiment.

【０００８】（実施例２）次に、図２を用いて他の実施
例を説明する。この実施例の製造方法は、先ずシリコン
の異方性エッチングにより側壁が（１１１）面となるＶ
溝１１を形成する。次にパターン形成を行い、段差構造
の凹部５，合わせマーク７を形成する。凹部の深さ(２
μｍ〜８μｍ）は、エッチングレートが毎分０.１〜１
μｍ程度に制御できるため、時間管理で再現性よく制御
することが可能である。次に、電子ビーム蒸着法により
チタン，白金，金からなる電極１０を形成し、パタニン
グする。固定のための金属合金膜６（ＡｕＳｎ薄膜）
は、光半導体素子電極上に蒸着法により下部の段の容積
より大きくならないような厚さ（３μｍ〜９μｍ）で形
成する。(Second Embodiment) Next, another embodiment will be described with reference to FIG. In the manufacturing method of this embodiment, first, V is formed by anisotropic etching of silicon so that the side wall becomes a (111) plane.
The groove 11 is formed. Next, pattern formation is performed to form the recess 5 and the alignment mark 7 having a step structure. Depth of recess (2
(μm to 8 μm) has an etching rate of 0.1 to 1 per minute.
Since it can be controlled to about μm, it can be controlled with good reproducibility by time management. Next, the electrode 10 made of titanium, platinum and gold is formed by the electron beam evaporation method and patterned. Metal alloy film 6 (AuSn thin film) for fixing
Is formed on the electrodes of the optical semiconductor device by vapor deposition so as to have a thickness (3 μm to 9 μm) not larger than the volume of the lower step.

【０００９】光半導体素子１は、赤外光透過法により半
導体素子と基板に形成した合わせマーク７を赤外線カメ
ラによって同時に観測し平面方向の位置合わせを行った
後、加重を加えつつ加熱し、光半導体素子を位置固定用
の段４に固定する。光半導体素子１とマウント基板３の
基板に垂直な方向の位置は、位置固定用の段４と光半導
体素子１の接触面で決定される。また、固定のための金
属合金膜６は、接合用段５があるため、その内に留ま
り、光半導体素子端面への流出は防がれる。さらに、光
半導体素子１を金ワイヤ９で接続し、電気的接続をと
る。最後に光ファイバ１１を接着剤で固定し実施例２を
完成する。In the optical semiconductor element 1, the alignment marks 7 formed on the semiconductor element and the substrate are simultaneously observed by an infrared camera by the infrared light transmission method and aligned in the plane direction, and then heated while applying a load to light. The semiconductor element is fixed to the step fixing step 4. The position of the optical semiconductor element 1 and the mount substrate 3 in the direction perpendicular to the substrate is determined by the contact surface between the position fixing step 4 and the optical semiconductor element 1. Further, since the metal alloy film 6 for fixing is present in the joining step 5 because of the joining step 5, outflow to the end face of the optical semiconductor element is prevented. Further, the optical semiconductor element 1 is connected with a gold wire 9 to establish electrical connection. Finally, the optical fiber 11 is fixed with an adhesive to complete the second embodiment.

【００１０】[0010]

【発明の効果】本発明により、光半導体素子の搭載位置
精度が０.２ μｍ以下に抑えられる。特に、固定位置を
決める上段の高さは、光導波路のコア層と一致している
ため、結果として光半導体素子と光導波路又は光ファイ
バの結合損失のばらつきを0.2ｄＢ以下にすることがで
きる。また、ソルダの光半導体素子端面への流出も防ぐ
ことができることから、結果として歩留りを向上させる
ことができ、デバイスの低価格化に対しても大きな効果
を発揮することができる。According to the present invention, the mounting position accuracy of the optical semiconductor element can be suppressed to 0.2 μm or less. In particular, since the height of the upper stage that determines the fixed position matches the core layer of the optical waveguide, the variation in the coupling loss between the optical semiconductor element and the optical waveguide or the optical fiber can be 0.2 dB or less as a result. Further, since the solder can be prevented from flowing out to the end face of the optical semiconductor element, the yield can be improved as a result, and a great effect can be exerted also in reducing the cost of the device.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第一の実施例の光アセンブリの平面図
および断面図。FIG. 1 is a plan view and a sectional view of an optical assembly according to a first embodiment of the present invention.

【図２】本発明の第二の実施例の光アセンブリの平面図
および断面図。FIG. 2 is a plan view and a sectional view of an optical assembly according to a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１…光半導体素子、２…光半導体素子、３…マウント基
板、４…位置固定用段、５…接合用段、６…金属合金
膜、７…位置合わせ用合わせマーク、８…光導波路、９
…金ワイヤ、１０…電極、１１…Ｖ溝、１２…光ファイ
バ。DESCRIPTION OF SYMBOLS 1 ... Optical semiconductor element, 2 ... Optical semiconductor element, 3 ... Mount substrate, 4 ... Position fixing step, 5 ... Joining step, 6 ... Metal alloy film, 7 ... Alignment mark for alignment, 8 ... Optical waveguide, 9
... gold wire, 10 ... electrode, 11 ... V groove, 12 ... optical fiber.

Claims (9)

【特許請求の範囲】[Claims] 【請求項１】表面に光導波路が形成されたマウント基板
と、前記マウント基板上に搭載された少なくとも一つの
光半導体素子と他の半導体素子を有し、前記光半導体素
子に設けられた電極パターンと前記マウント基板に設け
られた電極パターンとを金属合金を介して固定してなる
光半導体装置において、前記マウント基板上の前記光半
導体素子を固定する位置に段差構造を形成したことを特
徴とする光アセンブリ。1. An electrode pattern provided on the optical semiconductor element, comprising a mount substrate having an optical waveguide formed on a surface thereof, at least one optical semiconductor element and another semiconductor element mounted on the mount substrate. In an optical semiconductor device in which an electrode pattern provided on the mount substrate is fixed via a metal alloy, a step structure is formed at a position on the mount substrate where the optical semiconductor element is fixed. Light assembly. 【請求項２】表面に光ファイバを固定するためのＶ溝が
形成されたマウント基板と、前記Ｖ溝に固定される光フ
ァイバと、前記マウント基板上に搭載された少なくとも
一つの光半導体素子と他の半導体素子を有し、前記光半
導体素子に設けられた電極パターンと前記マウント基板
に設けられた電極パターンとを金属合金を介して固定し
てなる光半導体装置において、前記マウント基板上の前
記光半導体素子を固定する位置に段差構造を形成したこ
とを特徴とする光アセンブリ。2. A mount substrate having a V groove formed on its surface for fixing an optical fiber, an optical fiber fixed to the V groove, and at least one optical semiconductor element mounted on the mount substrate. An optical semiconductor device having another semiconductor element, wherein the electrode pattern provided on the optical semiconductor element and the electrode pattern provided on the mount substrate are fixed via a metal alloy, An optical assembly, wherein a step structure is formed at a position where an optical semiconductor element is fixed. 【請求項３】請求項１または２において、段の上面と光
半導体素子に位置合わせのためのインデックスを形成し
た光アセンブリ。3. The optical assembly according to claim 1, wherein an index for alignment is formed on the upper surface of the step and the optical semiconductor element. 【請求項４】前記半導体素子が光導波路構造よりなり、
また発光作用を有し、その光軸高さが±３ミクロン以内
で前記マウント基板上の前記光導波路の光軸高さと一致
している請求項１，２または３に記載の光アセンブリ。4. The semiconductor element has an optical waveguide structure,
4. The optical assembly according to claim 1, which has a light emitting function, and whose optical axis height is within. +-. 3 .mu.m and which matches the optical axis height of the optical waveguide on the mount substrate. 【請求項５】半導体素子が光導波路構造よりなり、また
受光作用を有し、その光軸高さが±３ミクロン以内でマ
ウント基板上の光導波路の光軸高さと一致している請求
項１，２，３または４に記載の光アセンブリ。5. The semiconductor element has an optical waveguide structure and has a light-receiving function, and its optical axis height is within ± 3 μm and is equal to the optical axis height of the optical waveguide on the mount substrate. , 2, 3 or 4 optical assembly. 【請求項６】前記発光素子に接続する前記光導波路と前
記受光素子に接続する前記光導波路が光学的に結合する
請求項１，２，３，４または５に記載の光アセンブリ。6. The optical assembly according to claim 1, wherein the optical waveguide connected to the light emitting element and the optical waveguide connected to the light receiving element are optically coupled. 【請求項７】搭載した前記光半導体素子の搭載された溝
が蓋により覆われた請求項１，２，３，４，５または６
に記載の光アセンブリ。7. A groove for mounting the mounted optical semiconductor element is covered with a lid.
The optical assembly described in. 【請求項８】搭載した前記光半導体素子の搭載された溝
の内、前記光導波路経路が樹脂により埋めこまれた請求
項１，２，３，４，５，６または７に記載の光アセンブ
リ。8. The optical assembly according to claim 1, wherein the optical waveguide path is filled with resin in a groove in which the mounted optical semiconductor element is mounted. . 【請求項９】請求項１，２，３，４，５，６，７または
８に記載の光アセンブリを用いた光伝送モジュール。9. An optical transmission module using the optical assembly according to claim 1, 2, 3, 4, 5, 6, 7 or 8.
JP361196A 1996-01-12 1996-01-12 Optical assembly Pending JPH09191131A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP361196A JPH09191131A (en) 1996-01-12 1996-01-12 Optical assembly

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP361196A JPH09191131A (en) 1996-01-12 1996-01-12 Optical assembly

Publications (1)

Publication Number Publication Date
JPH09191131A true JPH09191131A (en) 1997-07-22

Family

ID=11562296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP361196A Pending JPH09191131A (en) 1996-01-12 1996-01-12 Optical assembly

Country Status (1)

Country Link
JP (1) JPH09191131A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999012216A1 (en) * 1997-08-28 1999-03-11 Hitachi, Ltd. Semiconductor photodetector and optical transmitting device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999012216A1 (en) * 1997-08-28 1999-03-11 Hitachi, Ltd. Semiconductor photodetector and optical transmitting device

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