JPH09191082A - Improved bipolar scr triggering for esd protection of high speed bipolar/bismuth-carbon-mos circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a small silicon region and eliminate impedance to be added to a signal line almost completely by a method wherein a small shunt capacitance value and a small series resistance value are provided for input and output pins. SOLUTION: A small collector resistance value is obtained for a vertical N-P-N transistor which are built up on a structure 50 by an N+-type layer 54. P-type layers 56a and 56b are extended to the surface of the structure 50 to define isolation regions and an N-type well 58 is formed between the isolation regions. The N-type well 58 functions as the collector region of the N-P-N transistor. An N+-type region 76 is extended from the surface of the structure 50 to the inside of the N-type well 58 and hence functions as an N-P-N base contactor. A P+-type anode region 62 is formed in the N-P-N transistor N-type well 58 to form a P-N-P SCR structure. A P-N-P structure is defined by the P+-type anode region 62, the N-type well region 58, a P-type base region 66 and an N+-type region 68.

Description

Detailed Description of the Invention

[0001]

[0001] The present invention generally relates to
Regarding electronic circuits. More specifically, the present invention provides an electrostatic discharge (ele) for bipolar / BiCMOS circuits.
ctrostatic discharge, ESD)
Regarding the protection circuit.

[0002]

The use of electrostatic discharge (ESD) protection circuits to protect input and output circuits from electrostatic discharge (ESD) is well known. That is, such a protection circuit is disclosed in prior art US Pat. No. 5,268,588 and US Pat.
243, US Pat. No. 5,077,591, US Pat. No. 5,060,037, US Pat. No. 5,012,31.
7, US Pat. No. 5,225,702, and US Pat. No. 5,290,724. All of these patents are Texas Instruments Incorporated, the assignee of the present invention.
have been transferred to Trumps Incorporated). E for Bipolar / BiCMOS technology
The SD protection circuit is the collector of the NPN output transistor.
Base-junction and emitter-coupled logic (emitterc)
an emitter of an open logic (ECL) device
It is necessary to be able to protect the pull-down NMOS transistor in the CMOS output buffer as well as the base junction. The operation of this protection circuit allows it to turn on at voltages below the trigger and hold voltages of their associated devices. The ESD protection circuit also
For it to be effective, the contributing capacitance value should be as small as possible, and the required surface area should be as small as possible.

Many ESD protection circuits use a two-step protection scheme for circuit inputs, as shown in the prior art of FIG. Typically, a large ESD current pulse passes through the primary clamp device. This primary clamp device clamps the pad voltage. However, this clamped voltage is still too high for the circuit to receive, so the secondary clamping device clamps the voltage to a safe value. A current limiting device limits the current so that the secondary clamping device does not receive excessive voltage.

Current technology BiCMOS process is ESD
NPN device or SCR (sili) for protection circuit
con controlled rectifier,
Silicon controlled rectifier) device. SCR devices designed for bipolar circuits typically use NPN.
It exhibits a higher trigger voltage than a transistor and a hold voltage that is comparable or even lower. Complementary oxide semiconductor (complementary oxide semiconductor)
Protecting both input and output circuits from damage due to electrostatic discharge becomes increasingly difficult as the process of developing (CMOS, CMOS) processes into transistors with shorter channel lengths and gate oxides.

High speed submicron bipolar / BiC
In the application to the MOS circuit, severe restrictions are required regarding the ESD protection circuit. The most important requirement is to have a small shunt capacitance value and a small series resistance value for the input and output pins. This is ES
This means that the silicon area required in the D protection circuit must be as small as possible, and that the impedance contribution to the signal path is virtually absent. The trigger voltage (V _t ) and clamp voltage (V _clamp ) are also the voltage at which the protected circuit "turns on" (ie,
Operating voltage) or less. NPN transistor ESD protection schemes have some limitations for such devices. FIG. 2 shows a 0.6 μm process and a 0.
7 is a graph of a pulse current / voltage characteristic curve of an NPN transistor having a width of 100 μm in an 8 μm process. Where V
_{The clamp} is 1.3 amps for the 0.6 μm process and 10
Volts, and 13 volts at 1.3 amps for a 0.8 μm process. In advanced submicron technology, emitter coupled logic
ledlogic, ECL) devices, and bipolar /
These levels are too high to protect the MOS input and output buffers. This high clamp voltage of the NPN structure is due to its high hold voltage ( _Vh ) and on-resistance. In the sub-micron bipolar / BiCMOS process, the protective NPN structure is
In order to carry a large ESD current, avalanche
Can work in mode. For a given step, the setting of BV _ceo (collector-emitter junction breakdown, base "open") thus sets the lower limit of the clamp voltage V _clamp . The clamp voltage can be lowered by decreasing the on-resistance value. By using a large NPN structure and a high capacitance load, it is possible to achieve a reduction in ON resistance value. However, such a scheme cannot be applied to high speed submicron bipolar / BiCMOS processes. This is because large shunt capacitance values create electrical "short circuit" paths for high frequency signal inputs and outputs.

Considering the above-mentioned drawbacks, in application to a high-speed circuit, it is desired to obtain a circuit structure capable of a BSCR protection circuit having a high-performance ESD characteristic which meets the above-mentioned demands of a small trigger voltage and a hold voltage. To be done. Of particular advantage is that a bipolar SCR protection circuit can be obtained that can be manufactured in sub-micron BiCMOS without the use of additional masks for circuit manufacture.

[0007]

SUMMARY OF THE INVENTION The present invention provides a high speed (eg 900M) for bipolar / BiCMOS circuits.
Silicon controlled rectifier (SC) with the advantage of being used in sub-micron ESD protection circuits at (Hz to 2 GHz and above) and having low trigger and hold voltages.
A bipolar structure such as R) is obtained. This bipolar structure is characterized by having a small shunt capacitance value and a small series resistance value for the input and output pins, which results in a small silicon area and almost no impedance added to the signal path. There may be no or no ESD protection circuit. According to one preferred feature of the present invention, rather than to a P-type substrate as in the prior art, a bipolar / BiCMO
The SCR is assembled in the N-type well of the S device.
Furthermore, a P + type anode implant can be obtained which can be achieved without additional patterning steps with a mask.

One preferred feature of the present invention is the use of Zener diodes in combination with resistors to control BSCR operation by PNP transistors. The voltage at which this Zener diode turns on is N
It is chosen to be comparable to the emitter-base breakdown voltage of the PN structure. This voltage ensures that the ESD protection circuit is not triggered under normal circuit operation.
Only slightly higher than the power supply voltage. A forward diode string can optionally be added in series with the zener diode to increase the trigger voltage of the circuit, especially if the power supply voltage exceeds the zener breakdown voltage. During ESD, the pad voltage is
When the breakdown voltage is exceeded, the zener diode breaks down and current flows through the associated (polysilicon) resistor, thereby causing a bipolar SCR.
Trigger the NPN structure of In this way BSCR
Is activated and a large ESD current flows from the associated protected circuit.

[0009]

Further features and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings. In the accompanying drawings, like reference numerals in different drawings represent corresponding parts. Dimensions of structures in the accompanying drawings may be exaggerated to clearly show the structure.

It should be noted that the process steps and structures described below do not constitute a complete process for manufacturing integrated circuits. The present invention can be implemented in conjunction with currently used integrated circuit manufacturing techniques. Many commonly used steps are included in the present invention as necessary to understand the present invention. The figures herein and cross-sectional views of a portion of an integrated circuit being manufactured are not necessarily drawn to scale and may be exaggerated to understand features of the invention. .

The ESD circuit of the present invention provides a relatively small shunt capacitance value (typically less than 0.5 pF) and a resistance value near zero at the input and output pads of the circuit. This is desirable for current and future protection schemes for submicron bipolar / BiCMOS circuits. The operation of the ESD protection circuit obtained by the present invention protects the pull-down NMOS transistor in the CMOS output buffer, the collector-base junction in the NPN output transistor, and the emitter-base junction in the ECL output. can do. By operating such an ESD protection circuit,
It can be turned on at a voltage that is typically lower than the trigger voltage of each of these devices, and is characterized by a lower hold voltage than the on-voltage of these devices, ie the operating voltage. As explained below, the reduction of the on-voltage and the hold voltage is obtained by the operation of the trigger element. This trigger element can optionally be integrated with the BSCR to create a protection circuit.

3A and 3B show 0.8 μm BiC.
100μm wide bipolar SC manufactured by MOS process
FIG. 5 is a cross-sectional view of an example of R (“BSCR”). This one
A 00 μm wide BSCR is indicated generally by the reference numeral 50. The circuit 50 has a P-type substrate 52. The P-type substrate 52 underlies the buried N + -type layer 54. The N + type layer 54 provides a small collector resistance value for a vertical NPN transistor assembled on this structure, as described in detail below. The ends of the buried N + type layer 54 are surrounded by P type layers 56A and 56B, respectively. P-type layers 56A and 56B also include P-type substrate 5
It is also the edge of 2. P-type layers 56A and 56B extend to the surface to define isolation regions, and N-type well regions 58 are created between these isolation regions. This N-well serves as the collector region of the NPN transistor, as described below. P-type layer 56A
Oxide layers 60A and 60B are created in a conventional manner on and 56B, respectively. The P + type anode diffusion layer 62 is formed during the process of forming the base P + type implantation region 64, which is formed in the shallow P type base implantation region 66. A shallow N + type region 68 is created in the P type base region 66. Shallow N + type region 68 is covered with a layer 70 of polysilicon. An oxide layer 72 is created between the P-type base region 66 and the P + -type anode region 62. An oxide layer is similarly created between the P + type anode region 62 and the N + type region 76. N + type region 76 extends from the surface of structure 50 into N type well region 58 such that N + type region 76 acts as an NPN base contact.

Diffusion of P + type anode region 62 occurs during the process of forming P + type base implant region 64. P + type anode region 62 is created in NPN transistor N type well 58, thereby forming a PNPN SCR structure. This P + type anode implant region has advantages.
It does not require an additional masking step associated with this step. The PNPN structure is defined by a P + type anode region 62, an N type well region 58, a P type base region 66 and an N + type region 68. This bipolar PNPN structure includes an NPN transistor 80 and a PN
It can be handled as a transistor pair with the P-transistor 82. FIG. 4 shows a schematic diagram thereof. PNP transistor 82 is represented by P + type anode region 62, N type well region 58, and P type base region 66. NP
N-transistor 80 is represented by N-type well region 58, P-type base region 66, and N + -type poly-emitter region 68. The polysilicon layer 70 is an emitter layer,
This allows the shallow N + type region 68 to be created by diffusion. N + type region 76 serves as the collector contact for the NPN transistor. P + type area 62
Serves as the anode of the SCR.

Comparing FIG. 3 and FIG. 4, the shallow P +
It can be seen that the shaped base region 64 serves both as the base of the NPN transistor 80 and as the collector of the PNP transistor 82. Polysilicon region 70 and N + type region 68 therebelow form the emitter of NPN transistor 80. The P + type anode region 62 serves as an emitter of the PNP transistor 82. N + type region 76 acts as a collector contact for NPN transistor 80. In the circuit schematic of FIG. 4, R _N-well
Is a resistor for the N-type well 58, and is an R- _embedded N +
Is a buried N + layer resistor 88, R _bp is the base resistor 90 of the PNP transistor, and R _bn is the base resistor 92 of the NPN transistor 80. When the collector (C _NPN ) is shorted to the emitter E _PNP , as is typical in conventional SCR configurations, the trigger voltage V _t is about 24 volts, as shown in FIG. Such a high trigger voltage, as is typical for conventional SCR circuits, requires the use of a protection circuit that presents both a secondary ESD protection device and a series resistor. However, the requirement to add a series resistor in the signal path is a requirement for high speed submicron bipolar / Bi
It prevents the use of such SCR circuits in CMOS circuit applications. FIG. 5 also shows that when the collector C _NPN is shorted to the emitter E _PNP , with the exception of having a low on-resistance paired with the on-resistance of the NPN transistor, as shown in FIG. The same 7 volt BV _ceo hold voltage as the conventional NPN transistor is supplied to the bipolar SCR. Therefore, it can be seen that, with respect to the trigger voltage (V _t ) and the hold voltage (V _h ), the illustrated bipolar SCR structure does not significantly improve the conventional NPN transistor.

Although both NPN transistor 80 and PNP transistor 82 provide a low on resistance "turned on", the high BV _ceo hold voltage indicates that there is no regenerative SCR effect. Regenerative SCR
Is turned on when the PNP transistor 82 is the NPN.
It needs to be biased by the collector current of transistor 80 and vice versa. When the NPN collector (C _NPN ) is shorted to the PNP emitter (E _PNP ), the low base-emitter resistance of the PNP transistor 82 is due to the small _{deep N + type} diffusion resistance R _{deep N +} . This requires additional current from the avalanche NPN collector-base junction to hold the PNP transistor in the "on" state. For the same given current, NPN transistor 8
An increase in the emitter-base resistance value of either the zero or PNP transistor 82 results in a base-emitter voltage _Vbe.
, And consequently a large collector current will flow in the bipolar transistor. This large collector current in the bipolar transistor eliminates the need for an additional current source by producing avalanche operation and allows the generation of regenerative SCR action. Therefore, the hold voltage can be reduced from BV _ceo to a small value. When a current is applied, the high resistance value causes the NPN transistor 80 or PN
P "turn on" further vigorously one of the transistors 82 that enables, as a result, a low holding voltage V _h is obtained. The effect of this resistor enhancement by the external PNP base-emitter resistor 90 (FIG. 4) between the NPN collector and PNP emitter is shown in FIG. Further, the hold voltage (V _h ) decreases as the resistance value R increases.

As explained above, there are two basic requirements for achieving the preferred bipolar SCR protection circuit. One requirement is a low trigger voltage (V _t ), and the other requirement is a regenerative SCR.
Low hold voltage (V _h ) resulting from the action. The structure and circuitry of the bipolar SCR design shown in FIGS. 3 and 4, respectively, allows the base of NPN transistor 80 to be externally biased. With such external bias, the operation of NPN transistor 80 provides an additional device for controlling the BSCR. As explained above, the main interest in using bipolar SCRs is the trigger voltage (V _t ) and the hold voltage (V _t ).
With respect to _h ), a major advantage over the case of using NPN transistors is that BSCR cannot be obtained. The main reason the hold voltage is substantially the same between the BSCR and the NPN transistor is to keep the PNP transistor 82 in the "on" state because
Base avalanche breakdown is required. Both the NPN and PNP transistors "turn on", which results in a low on resistance in the circuit, but in the absence of added current from the avalanche collector-base junction, a regenerative SCR effect. Does not happen. In order to lower the hold voltage, it is required that the NPN transistor be turned on “more reliably”, which causes a larger current to flow in the _N-type well resistor (RN well), and the base-emitter of the PNP transistor 82. It is possible to increase the voltage and thereby turn on the PNP transistor "more reliably". This can _be achieved by increasing the base-emitter resistance value ( _Rbe ). In this case, the current forced through the base-emitter resistor forward biases the NPN transistor 80, and can turn the transistor 80 "on" if collector-base avalanche action does not occur. This operation of the NPN transistor reduces the trigger voltage V _t . Another feature of the present invention provides that the Zener diode facilitates current biasing, as described below with respect to the schematic shown in FIG.

FIG. 6 is a bipolar SCR ESD fabricated 0.8 μm by BiCMOS technology according to the present invention.
It is a figure of a protection circuit. The circuit shown in FIG. 6 includes an NPN Zener diode 100 and a 1 KΩ polysilicon resistor 1
It is similar to the circuit shown in FIG. 4, except that 02 and are incorporated into the circuit. Zener diode 100
Are formed by the base-emitter junction of the NPN transistor 80. The voltage at which the Zener diode 100 turns on is the breakdown voltage of the base-emitter of the NPN transistor. This breakdown voltage is
Just above the power supply voltage is required for a given process so that the ESD protection circuit is not triggered during normal circuit operation. An optional forward diode string (not shown) in series with zener diode 100 may be optionally provided to increase the circuit's trigger voltage, especially for zener breakdown voltages below the supply voltage. preferable. During a period of ESD, when the pad voltage exceeds the Zener breakdown voltage, Zener diode 100 will break down and the current will be 1KΩ polysilicon resistor 10.
2 to trigger the bipolar SCR NPN transistor, thereby turning “on” the BSCR and turning on the large E
SD current flows.

FIG. 7 shows the current of the protection circuit shown in FIG.
It is a graph of a voltage characteristic. In this case, the deep N + type collector diffusion region (N + type region 76 in FIG. 3B) is rather a diffusion region that penetrates the N type well layer 58 until it reaches the deep buried N + type layer 54 shown in FIG. 3A. , N-type well layer 58 is replaced by a shallow N + type diffusion region extending only into the N-type well layer 58. This shallow diffusion region enhances the SCR action by increasing the resistance value of the base-emitter of the PNP transistor 82.

FIG. 7 shows that the trigger voltage (V _t ) can be lowered to 7 volts, and the hold voltage (V _h ).
Clearly shows that can be lowered to about 1.7 volts. This circuit also has an E of up to 2 amps.
The SD current can be handled, while the clamp voltage can be maintained at about 7 volts. The result of the ESD test,
The circuit with a 100 μm wide BSCR exhibited an ESD threshold voltage of 6.7 kilovolts and an ESD efficiency of 3.2 volts / μm ² (expressed in ESD volts per unit area of protection circuit). On the other hand, an NPN transistor manufactured by a substantially similar process has a voltage of 2.3 V / μ.
It only showed an efficiency of m ² . Thus, the structure of the present invention achieves an increase in ESD efficiency of approximately 40%. In other words, the bipolar SCR of the present invention allows a 40% reduction in capacitance load for a given ESD threshold voltage. In addition, as shown in the current / voltage characteristic graph of FIG. 7, this circuit provides ESD up to about 2 amps without any damage.
Can handle electric current. At a current of 2 amps,
The clamp voltage is about 7 volts. On the other hand, both the hold voltage and the trigger voltage of the NPN transistor manufactured by the same process are considerably high.
About 8 and 18 volts. Therefore, it can be seen that the degree of voltage reduction described above provides a significantly greater level of circuit protection than previously obtained.

Although the present invention has been described with respect to the illustrated embodiments, the above description is not meant to limit the scope of the invention to the embodiments. It will be immediately apparent to those skilled in the art, given the above description, that various other embodiments of the invention are possible. Therefore, it should be understood that all such modified embodiments are included in the scope of the present invention.

With respect to the above description, the following items are further disclosed. (1) (a) a first semiconductor layer 52 made of a semiconductor member of the first conductivity type, and (b) disposed on at least a part of the first semiconductor layer 52 and opposite to the first semiconductor layer. Second semiconductor layer 54 made of a conductive type member of
(C) A third semiconductor layer 58, which is disposed on at least a part of the second semiconductor layer 54 and is made of a member having the same conductivity type as that of the second semiconductor layer 54, and (d).
At least two laterally spaced first implant regions 62 and 64 disposed adjacent to the third semiconductor layer 58 and having a common conductivity type;
A second implant region 66 disposed between the at least two first implant regions 62 and 64; and (f) contacting at least a portion of the second implant region 66 and opposite the second implant region. A third implant region 68 having a conductivity type;
(G) The third implantation region 68 is laterally spaced apart from the third implantation region 68, has the same conductivity type as the second implantation region, and has the first implantation region 62, the second implantation region 66, and the second implantation region 66. A structure for protecting the circuit from electrostatic discharge having a third implant region 68 and a fourth implant region 76 which together define the third semiconductor layer 58 define a bipolar silicon controlled rectifier. (2) In the structure according to item 1, one of the first implantation regions 62 and 64 serves as an anode of the silicon controlled rectifier, and the other region of the first implantation region. Is the base of NPN transistor 80 and PN
Plays a role as a collector of the P-transistor 82,
The structure. (3) The structure according to item 2, wherein the third injection region 68 constitutes an emitter of the NPN transistor. (4) The structure according to the item (2), further including a resistor connected to the PNP transistor. (5) The structure according to item 4, wherein the resistor is connected between the collector of the NPN transistor 80 and the emitter of the PNP transistor 82. (6) In the structure according to the item (2), the current bias device 1 electrically connected to the NPN transistor 80.
The structure further comprising 00. (7) The structure according to item 6, wherein the current bias device includes a Zener diode. (8) The structure according to item 7, further comprising a resistor 102 connected to the Zener diode. (9) The structure according to item 7, wherein the Zener diode 100 is further formed by a base-emitter junction of the NPN transistor 80. (10) The structure of claim 6, further comprising a forward diode array connected to the current bias device. (11) In the structure according to item 1, at least two stacked body regions 56a, 56b which are in contact with the first semiconductor layer 52 and the second semiconductor layer 54 and are arranged at intervals in the lateral direction. The structure further comprising: (12) In the structure according to item 11, the space is defined between the second semiconductor layer 54 and the stacked body regions 56a and 56b arranged at intervals in the lateral direction, and the third semiconductor layer 54 is formed. The structure having a semiconductor layer 58, wherein an isolation region is defined. (13) (a) A first semiconductor layer 52 made of a semiconductor member of the first conductivity type, and (b) disposed on at least a part of the first semiconductor layer 52 and opposite to the first semiconductor layer. Second semiconductor layer 5 made of a conductive type member of
4 and (c) a third semiconductor layer 58, which is disposed on at least a part of the second semiconductor layer 54 and is made of a member having the same conductivity type as that of the second semiconductor layer 54, and (d)
At least two laterally spaced first implant regions 62 and 64 disposed adjacent to the third semiconductor layer 58 and having a common conductivity type;
A second implant region 66 disposed between the at least two first implant regions 62 and 64; and (f) the second implant region 66.
A third implant region 68 contacting at least a portion of implant region 66 and having a conductivity type opposite to said second implant region.
And (g) is disposed laterally spaced from the third implantation region 68, has the same conductivity type as the second implantation region, and has the same conductivity type as the first implantation regions 62, 64. One area serves as the anode of the silicon controlled rectifier,
And the other region of the first implant region serves as the base of the NPN transistor 80 and the collector of the PNP transistor 82. (H) a current bias device 100 incorporated in one of the transistors 80, 82.
A structure that protects circuits from electrostatic discharge. (14) The structure according to the item 13, wherein the current bias device 100 has a Zener diode connected to a base-emitter junction of the NPN transistor 80. (15) In the structure according to item 13, the current bias device 100 has a Zener diode formed by a base-emitter junction of the NPN transistor 80, and is connected in series to the Zener diode. The structure further comprising a resistor 102. (16) Silicon control according to the present invention has the advantage of being used in submicron ESD protection circuits at high speed (eg, 900 MHz to 2 GHz or higher) for bipolar / BiCMOS circuits and having low trigger and hold voltages. A bipolar structure such as a rectifier (SCR) is obtained. This bipolar structure is characterized by having a small shunt capacitance value and a small series resistance value with respect to the input and output pins, so that it has a small silicon area and little impedance is added to the signal path. There may be no or no ESD protection circuit. According to one preferred feature of the invention, the SCR is assembled in the N-well of a bipolar / BiCMOS device, rather than on a P-substrate as in the prior art. One preferred feature of the present invention is the use of Zener diodes in combination with resistors to control BSCR operation by NPN transistors. The voltage at which the Zener diode turns on is chosen to be comparable to the emitter-base breakdown voltage of the NPN structure. This voltage is only slightly higher than the power supply voltage so that the ESD protection circuit will not be triggered under normal circuit operation. A forward diode string can optionally be added in series with the zener diode to increase the trigger voltage of the circuit, especially if the power supply voltage exceeds the zener breakdown voltage. During a period of ESD, when the pad voltage exceeds the zener breakdown voltage, the zener diode breaks down and current flows through the associated (polysilicon) resistor, thereby causing the bipolar SCR NPN. Trigger a structure. In this way the BSCR operates and a large ESD current flows from the associated protected circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram of a conventional ESD protection circuit.

FIG. 2 is a graph of current-voltage characteristics of a 100 μm wide NPN structure in a 0.6 μm and 0.8 μm BiCMOS process.

FIG. 3 is a cross-sectional view of yet another ESD protection circuit structure according to the present invention, where A is a diagram of one embodiment and B is a diagram of another embodiment.

FIG. 4 is a schematic diagram of the ESD protection circuit shown in FIG. 3A.

5 is a graph showing the resistor dependence of the current-voltage characteristic curve of the bipolar SCR device shown in FIG. 3A.

FIG. 6 is a schematic diagram of another bipolar SCR protection circuit using an NPN Zener diode and a resistor.

7 is a graph of large current / voltage characteristics of the bipolar SCR ESD protection circuit shown in FIG.

[Explanation of symbols]

 52 first semiconductor layer 54 second semiconductor layer 58 third semiconductor layer 62, 64 first implantation region 66 second implantation region 68 third implantation region 76 fourth implantation region 90 resistor

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Thomas A. Brothoss 1201 Ashland Drive, Richardson, Texas, United States

Claims (1)

[Claims] 1. A first semiconductor layer 52 made of a semiconductor member of the first conductivity type, and (b) the first semiconductor layer 5.
A second semiconductor layer 54 disposed on at least a portion of 2 and made of a member having a conductivity type opposite to that of the first semiconductor layer; and (c) on at least a portion of the second semiconductor layer 54. A third semiconductor layer 58 disposed and made of a member of the same conductivity type as the second semiconductor layer 54;
(D) At least two first implantation regions 62 and 64 which are arranged adjacent to the third semiconductor layer 58 and have a common conductivity type and which are arranged at intervals in the lateral direction;
(E) The at least two first implantation regions 62 and 64
A second implant region 66 disposed between, and (f) a third implant region 6 in contact with at least a portion of the second implant region 66 and having a conductivity type opposite to the second implant region 6.
And (g) are laterally spaced from the third implantation region 68, have the same conductivity type as the second implantation region, and have the first implantation region 62 and the second implantation region. A structure for protecting the circuit from electrostatic discharge, comprising: 66, a third implant region 68, and a fourth implant region 76, which together define the third semiconductor layer 58 to define a bipolar silicon controlled rectifier.