JPH0918620A - Facsimile equipment - Google Patents

Abstract

PURPOSE: To reduce the cost of the facsimile equipment having a memory transmission function. CONSTITUTION: A memory 10 storing code data outputted from a coding/ decoding circuit 2 and compressed voice data outputted from a DSP 9 is made up of a DRAM 11 and a PROM 12. An address whose head address is fixed is given to the DRAM 11 and an address with a changeable offset address added thereto is given the PROM 12. Since the address position of the PROM 12 to which compressed voice data and code data are written is shifted by changing the offset address, use of a memory cell of a specific address at a high frequency at a specific address is avoided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a facsimile apparatus having a memory transmission function of temporarily storing image data obtained by reading an original in a memory, reading the image data from the memory and transmitting the image data.

[0002]

2. Description of the Related Art In ordinary facsimile communication, image data obtained by reading an original is subjected to a compression process by encoding, so that the communication speed changes depending on the amount of information of the original. Therefore, in order to read the document at a constant speed, a memory transmission function is required in which the image data obtained by reading the document is temporarily stored in a memory and then transmitted while being read from this memory.

FIG. 3 is a block diagram showing the configuration of a facsimile apparatus having a memory transmission function. The image processing circuit 1 performs various processes such as sample hold and distortion correction on an image signal obtained from a line sensor that reads a document, and further performs analog / digital conversion to generate image data. The encoding / decoding circuit 2 compresses the data amount by encoding the image data input from the image processing circuit 1 according to a predetermined rule, generates encoded data, and stores it in the memory 3. Further, the encoding / decoding circuit 2 includes a modem 5
The original image data is reproduced by decoding the coded data demodulated in (4) and is supplied to a printing system such as a printer as print data. The memory 3 is composed of a RAM (Random Access Memory), and stores the code data generated by the coding / decoding circuit 2 for each page for up to several tens of pages. For example, when a 4-Mbit DRAM is used, the code data of an A4 size document (about 200 Kbits / page) can store up to about 20 pages. The address generation circuit 4 supplies a write address that changes in a constant cycle to the memory 3 and specifies a write address of code data. Then, the read address is supplied to the memory 3 in accordance with the transmission timing of the modem 5, and the read address of the code data is designated. As a result, the code data taken in at a constant speed is output at a speed corresponding to the communication speed of the modem 5. The modem 5 subjects the code data read from the memory 3 to the modulation processing defined by the standard, generates a transmission signal, and supplies the transmission signal to the transmission / reception circuit 6. In addition, for the transmission signal input from the transmission / reception circuit 6,
A demodulation process that is the reverse of the modulation process for code data is performed,
Reproduce the original code data. The transmission / reception circuit 6 is connected to the communication line, sends out the transmission signal output from the modem 5 to the communication line, takes in the transmission signal from the communication line, and supplies the transmission signal to the modem 5. The image processing circuit 1, the encoding / decoding circuit 2, the address generating circuit 4, and the modem 5 operate at timings according to a common reference clock, and their operation timings are synchronized with each other.

By the way, it has been considered that a facsimile having a memory transmission function as described above is provided with an answering machine function for storing a message from the transmitting side. In this case, if the memory 3 is used for recording a message,
It is possible to suppress an increase in circuit scale and reduce costs. Therefore, in order to store the voice data together with the coded data in the memory 3, as shown in FIG. 3, an answering machine control circuit 7, an A / D conversion circuit 8 and a digital signal processor (DSP) 9 are provided. Are connected. The message recording control circuit 7 extracts a voice signal representing a message that needs to be recorded from the transmission signal taken in by the transmission / reception circuit 6 and supplies it to the A / D conversion circuit 8. The A / D conversion circuit 8 performs analog / digital conversion on the audio signal input from the answering machine control circuit 7, and outputs the DSP 9 as audio data.
To supply. The DSP 9 compresses the audio data input from the A / D conversion circuit 8 to generate compressed audio data, and writes the compressed audio data in the memory 3. Also,
The original audio data is reproduced by performing decompression processing opposite to the compression processing on the compressed audio data read from the memory 3, and the audio data is supplied as reproduction data to a reproduction system such as an amplifier. Assuming that the compressed audio data has a data amount of 4.8 Kbps by the DSP 9, if a 4 Mbit DRAM is used as the memory 3, a message of up to about 15 minutes can be stored.

[0005]

When compressed audio data is stored in the memory 3 using a DRAM or the like, it is necessary to hold the data until the data is reproduced. Therefore, the backup of the memory 3 cannot be turned off while the voice mail function is operating. In order to solve such a problem, the memory 3 may be composed of a non-volatile memory such as an EEPROM. If the memory 3 is a non-volatile memory, the operation of holding the stored data is unnecessary, and the memory 3 does not need to be backed up even during the absence recording function, which is effective for power failure countermeasures.

However, when the memory 3 is constituted by a non-volatile memory and the image data is repeatedly stored and reproduced, the number of times of rewriting of the non-volatile memory becomes a problem. For example, in the case of a memory that can store code data for 20 pages at a time, if 200 pages are transmitted per day and a 10-year service life is to be guaranteed, it will be 37,000 times (200 pages / 20 (Page x 365 days x 10 years = 36500) needs to be rewritten, and more rewritings are required. Generally, a non-volatile memory, which can be rewritten many times, has strict manufacturing conditions and high manufacturing cost. In particular, as the storage capacity increases, the manufacturing yield decreases, and the manufacturing cost increases significantly.

Therefore, an object of the present invention is to extend the life of the memory and prevent an increase in cost while using a nonvolatile memory as a memory for storing voice data of a message.

[0008]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is characterized in that continuous image information is compressed line by line to code data. A first encoding circuit for converting, a code signal for modulating the code data according to a predetermined rule to form a transmission signal, a modem for transmitting to a communication line, and a voice signal taken out from the transmission signal taken from the communication line, and this voice signal And a memory for storing code data output from the first coding circuit and voice data output from the second coding circuit. An address designating circuit for designating a write address of the code data and the audio data to the memory, and the address designating circuit includes a basic address having a constant start address. It is to generate a real address by adding the rewritable offset address to scan.

[0009]

According to the present invention, since the start address of the memory for storing code data is shifted by the offset address, the address range in which the code data is written can be arbitrarily changed by periodically rewriting the offset address. This prevents only the memory cells located at a specific address from being rewritten with high frequency, and all the memory cells can be used almost equally. Therefore, the life of the entire memory cell can be improved without increasing the number of times that each memory cell can be rewritten.

[0010]

1 is a block diagram showing the configuration of a facsimile apparatus of the present invention. In this figure, an image processing circuit 1, an encoding / decoding circuit 2, a modem 5, a transmission / reception circuit 6, an answering machine control circuit 7, an A / D conversion circuit 8 and a DSP 9 are the same as those in FIG. The image data output from the image processing circuit 1 is converted into code data by the encoding / decoding circuit 2, the code data is converted into a transmission signal by the modem 5, and then transmitted to the communication line via the transmission / reception circuit 6. To be configured. Further, the voice signal received by the transmission / reception circuit 6 is taken out by the recorded message control circuit 7, and the A / D conversion circuit 8
After being converted into audio data by, it is compressed by the DSP 9 and converted into compressed audio data.

The memory 10 is composed of a DRAM (Dynamic Random Access Memory) 11 that requires a data holding operation and a flash-type PROM (Programmable Read Only Memory) 12 that is capable of batch erasing and rewriting data. It The first address generation circuit 13 is a DRA.
It is connected to M11 and generates a cyclic address whose head address is fixed. The second address generation circuit 14 is
It has the same configuration as the first address generating circuit 13, is connected to the offset circuit 15, and generates a cyclic address having a fixed start address. The offset circuit 15 is
It is connected to the PROM 12 and adds a constant offset address to the address generated by the address generation circuit 14.
In the offset circuit 15, when an overflow occurs due to addition, the overflow amount is ignored and the address is returned to the head address. That is, when the basic address changes from "0" to "n", the real address added with the offset address changes to "n" starting from the offset address, and returns to "0" after "n". Change to the address before the first address (offset address). For example, when adding an offset address of "n / 2" to a basic address that changes from "0" to "n", the real address is "n /" as shown in FIG.
It will change from "2" to "n" and then from "0" to "n / 2-1". The rewrite control circuit 16 stores some offset values and supplies one of the offset values to the offset circuit 15 in response to a rewrite instruction. For example, in the case shown in FIG. 2, “0” and “n / 2” are stored as the offset values, and one of them is supplied to the offset circuit 15. The rewriting instruction to the rewriting control circuit 16 is directly input by a person who operates the apparatus, or PR
The number of rewrites of the OM 12 may be counted and automatically given when the predetermined number of times is reached. However, if some data remains in the PROM 12 at the time of rewriting the offset address, the data cannot be read. Therefore, the timing of rewriting the offset address is immediately after reading the data of the PROM 12 or immediately after restarting. Must be set to. The memory control circuit 17 includes the DRAM 11 and the PROM.
Control writing of data to 12. For example, the code data supplied from the encoding / decoding circuit 2 is transferred to the DRAM 1
Write with priority to 1, and the overflow is PRO
Write to M12. Also, the compressed audio data written from the DSP 9 is written to a predetermined address of the PROM 12. Here, PROM12
Is separated into code data and compressed voice data, and a range from the start address of the address given from the offset circuit 15 to a fixed range is allocated to the storage of the compressed voice data, and immediately after the end of the range. Assigned to store coded data. If all the code data output from the encoding / decoding circuit 2 is written in the DRAM 11, the code data is not written in the PROM 12.

As described above, the PROM 12 which adds the offset address to the basic address to form the real address
In (1), the address of the memory cell can be shifted by changing the offset address. For example, FIG.
In the above, the hatched part is
When the offset address of "2" is added, the address shifts by that amount. Therefore, if the offset address is rewritten regularly, only the memory cells of a specific address will not be intensively used, and it is possible to prevent the memory cells from being unevenly deteriorated. Therefore, the life of the PROM 12 can be extended.

In the present embodiment, the case where the offset address is set as "0" and "1/2" is exemplified, but the setting of the offset address is performed in "1/4" unit or "1/8" unit. You may make it smaller. For setting the offset address, see PROM12.
It is most suitable if it is performed based on the storage capacity and the amount of compressed audio data.

[0014]

According to the present invention, the memory cells in the PROM portion can be prevented from partially deteriorating, so that the life of the entire memory can be lengthened, and as a result, the cost can be reduced. it can. Further, since the PROM portion can receive the overflow of the code data from the DRAM portion more times, it is possible to reduce the capacity of the DRAM portion and further reduce the cost.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a facsimile apparatus of the present invention.

FIG. 2 is a diagram illustrating a change in address for a PROM.

FIG. 3 is a block diagram showing a configuration of a conventional facsimile machine.

[Explanation of symbols]

 1 Image Processing Circuit 2 Encoding / Decoding Circuit 3, 10 Memory 4, 13, 14 Address Generation Circuit 5 Modem 6 Transmitter / Receiver Circuit 7 Answering Machine Control Circuit 8 A / D Converter Circuit 9 Digital Signal Processing Circuit (DSP) 11 DRAM 12 PROM 15 Offset circuit 16 Rewrite control circuit 17 Memory control circuit

Claims (3)

[Claims] 1. A first encoding circuit for compressing continuous image information row by row to convert it into code data, and modulating the code data according to a predetermined rule to form a transmission signal, which is then transmitted to a communication line. A modem for sending out, a voice signal from a transmission signal fetched from a communication line, a second coding circuit for digitally converting the voice signal to generate voice data, and the first coding circuit are outputted. A memory for storing code data and audio data output from the second encoding circuit, and an address specifying circuit for specifying a write address of the code data and the audio data to the memory are provided. The design circuit is characterized by adding a rewritable offset address to a basic address with a fixed start address to generate a real address. Fax machine. 2. The memory includes a RAM capable of repeating reading and writing and an electrically erasable and writable ROM, and the address generating circuit has a fixed start address with respect to the RAM. First done
Address generating section for giving the address of the above and the ROM
2. The facsimile apparatus according to claim 1, further comprising: a second address generator that gives a second address to which a changeable offset address is added. 3. The memory stores the code data in the R
3. The facsimile apparatus according to claim 2, wherein the AM portion is preferentially stored, and the overflow portion from the RAM portion is stored in the ROM portion.