JPH0918603A - Call signal detector - Google Patents

Abstract

PURPOSE: To relieve the processing load on a CPU in the case of detecting a call signal. CONSTITUTION: The detector is provided with a sampling circuit 33 that receives data resulting from theresholding an analog signal received via a telephone line 2 at a thresholding circuit 32 and stores the data in the order of reception and with a counter circuit 34 that counts the number of clock pulses and provides an output of an interrupt signal TNT when the count reaches a prescribed value. A CPU 11 reads data stored in the sampling circuit 33 in response to the input of an interrupt signal from the counter circuit 34 and discriminates whether or not a call signal with a prescribed frequency is received.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a call signal detecting device used for communication equipment such as a facsimile machine.

[0002]

2. Description of the Related Art FIG. 4 shows the configuration of a conventional call signal detecting device of this type. That is, this call signal detecting device takes in an analog signal received through the telephone line 1 via the photocoupler 2 and inputs it to the binarizing circuit 3 to binarize it at a preset reference level. Then, the binary data CS is processed by a CPU (Central Processing) as a processor.
Unit) 4 to the I / O port 5 connected to the bus. As shown in FIG. 5, the CPU 4 samples the binarized data CS input to the I / O port 5 based on a preset program at a sampling period of, for example, 1 ms, and at a predetermined frequency of 16 to 60 Hz, for example. When binary data that repeats on and off is detected, it is determined that a call signal has been received and the incoming call processing is performed.

Here, the CPU 4 generally constitutes a control unit main body of a communication device such as a facsimile machine. Therefore, the CPU 4 executes not only the normal program control of each unit constituting the communication device but also the program control for sampling the input data to the I / O port 5 to determine whether or not the call signal is received.

[0004]

As described above, in the conventional call signal detecting apparatus of this kind, the CPU 4 controls each unit constituting the communication terminal and the I / O port 5 has a very short cycle of about 1 ms. Since it was frequently sampled to determine whether or not the call signal was received, the processing load on the CPU 4 was heavy. On the other hand, in recent years, multifunctionalization of communication devices such as facsimile machines has been promoted, and the CPU 4
There is no choice but to increase the processing load. Therefore, if the processing load of the CPU 4 required for detecting the call signal can be reduced, it is possible to allow the increase of the processing load due to the multi-functionality to some extent, which is convenient.

Therefore, the present invention is intended to provide a call signal detecting apparatus capable of reducing the processing load of the processor required for detecting the call signal.

[0006]

A call signal detecting apparatus according to the present invention binarizes an analog signal received through a line.
A binarization circuit, a sampling circuit that captures binarized data by the binarization circuit each time a clock pulse is input, accumulates and stores the data in the sequence in which the clock pulse is captured, and counts the number of clock pulses to generate an interrupt signal And a processor that responds to the input of the interrupt signal, reads the data stored and stored in the sampling circuit, analyzes the read data, and determines whether or not a call signal of a predetermined frequency is received. It is equipped with.

[0007]

With the call signal detecting apparatus of the present invention configured as described above, the data obtained by binarizing the analog signal input through the line by the binarizing circuit is sampled in response to the clock pulse generation period. It is taken into the circuit, and is stored and stored in the order in which it is taken. The number of clock pulses is counted by the counter circuit, and when the counted value reaches a predetermined value, an interrupt signal is output to the processor. As a result, in the processor, program control is executed in response to the input of the interrupt signal, reading the data stored and stored in the sampling circuit, and determining whether or not a call signal of a predetermined frequency is received.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the call signal detecting apparatus of the present invention is applied to a facsimile machine will be described below with reference to FIGS. FIG. 1 is a block diagram showing the schematic arrangement of a facsimile apparatus according to this embodiment. That is, this facsimile apparatus includes a CPU 11 as a processor that constitutes the control unit main body of the facsimile apparatus and the CP
As a main memory unit controlled by U11, a ROM (Read
Only Memory) 12 and RAM (Random Access Memor)
y) 13 is installed. The ROM 12 has a CPU
Fixed data such as a program executed by 11 is stored in advance. Various memory areas for temporarily storing various data are formed in the RAM 13.

Further, this facsimile apparatus has a clock unit 14 for measuring the date and time, a data compression / expansion circuit 15 for compressing and expanding image data, a telephone circuit 17 to which a telephone 16 is connected, a modem 18 for modulating and demodulating, A reading control unit 20 that controls driving of a document reading unit 19 that optically reads a transmission document, a print control unit 22 that controls driving of a printing unit 21 that prints on recording paper, and a telephone number of a facsimile transmission destination are input. It is equipped with an operation panel 23 provided with keys and a display, an I / O port 24 for exchanging signals, and the like. Then, the CPU 11, the ROM 12, the RAM 13, the clock unit 14, the data compression / expansion circuit 15, the telephone circuit 17, the modem 18, the read control unit 20, the print control unit 22 and the I / O.
The port 24 is connected to a bus line 25 such as an address bus and a data bus.

In this facsimile apparatus, a telephone line 26 is connected to the telephone circuit 17 and the modem 18 via a line switching relay 27. The line switching relay 27 connects the telephone line 26 to the telephone circuit 17 side in normal times, and temporarily switches the telephone line 26 to the modem 18 side in response to a switching command signal from the CPU 11. is there.

Specifically, when the CPU 11 detects from the telephone circuit 17 that the line to the facsimile communication destination called by dial input from the telephone 16 or the operation panel 23 is connected, the line switching relay is detected. A switching command signal is transmitted to the telephone line 26 to the modem 1
Connect to side 8. Then, after the image data of the document read by the document reading unit 19 is compressed by the data compression / expansion circuit 15, the data is transmitted by facsimile to the facsimile communication destination via the modem 18 according to a predetermined facsimile communication procedure. Then, after transmitting the image data, if the line with the facsimile communication destination is disconnected, a return instruction signal is sent to the line switching relay 27 to return the telephone line 26 to the telephone circuit 17 side. . Incidentally, this process is called a calling process.

When the CPU 11 detects that the call signal from the facsimile communication destination is received by the data from the telephone circuit 17, it sends a switching command signal to the line switching relay 27 to send the telephone line 26 to the modem 18 side. Connecting.
Then, after the image data received by facsimile via the modem 18 is expanded by the data compression / expansion circuit 15, the print image is printed out by the printing unit 21. When the line with the facsimile communication destination is disconnected after receiving the image data, a program is configured to send a return command signal to the line switching relay 27 to return the telephone line 26 to the telephone circuit 17 side. There is. Incidentally, this process is called an incoming call process.

Here, a concrete configuration of the call signal detecting apparatus for detecting the call signal is shown in a block diagram of FIG.
The same parts as those in FIG. 1 are designated by the same reference numerals. That is, an analog signal received through the telephone line 26 is taken in through the photocoupler 31 and input to the binarization circuit 32 to be binarized at a preset reference level. Then, this binarized data is input to the IN terminal of the sampling circuit 33. The sampling circuit 33 receives a CK clock pulse of 100 KHz from a clock oscillator (not shown).
The binary data input to the IN terminal is fetched each time the data is input to the terminal, and the binary data D0 to D7 of 8 bits can be stored and stored. The stored and stored 8-bit binarized data D0 to D7 are read by the CPU 11 connected to the bus in response to the input of the read enable signal to the RE terminal.

The clock pulse is also input to the CK terminal of the counter circuit 34. The counter circuit 34 counts the clock pulses input to the CK terminal, resets the count value every time it counts a predetermined value (“8” in this embodiment), and outputs an interrupt signal INT to the CPU 11. Is configured. The photo coupler 31, the binarization circuit 32, the sampling circuit 33, and the counter circuit 34 are provided in the telephone circuit 17.

Thus, the CPU 11 is program-controlled so as to start the interrupt processing shown in the flowchart of FIG. 3 in response to the input of the interrupt signal INT. That is, first, a read enable signal is output to the sampling circuit 33, the 8-bit binarized data D0 to D8 accumulated and stored in the sampling circuit 33 is read, and stored in a built-in register or the like. Then, the binary data including the current binary data is analyzed, and the binary data read so far from the sampling circuit 33 is analyzed to repeat ON / OFF at a predetermined frequency set as a call signal in advance. It is determined whether or not is detected. Then, when it is confirmed that the corresponding binary data is detected, it is determined that the call signal is received, and the incoming call processing as described above is executed.

In the present embodiment having the above-mentioned structure, the analog signal input through the telephone line 26 is converted into two signals.
The binarized data in the binarization circuit 32 is taken into the sampling circuit 33 in response to the clock pulse generation period (100 KHz), and is stored and stored in the order in which it was taken.
In addition, the pulse number of the clock pulse is the counter circuit 3
The count value is 4, and when the count value becomes "8", the interrupt signal INT is output to the CPU 11. As a result, the CPU 11 sends a read enable signal to the sampling circuit 33 in response to the input of the interrupt signal to read the 8-bit binarized data D0 to D7 stored and stored in the sampling circuit 33. Program control for determining whether a call signal having a predetermined frequency is received is executed.

Therefore, as compared with the conventional call signal detecting apparatus in which the CPU 4 samples binary data input to the I / O port 5 at intervals of 1 ms to determine whether or not a call signal is received, the sampling of the CPU 11 is performed. Since the cycle is extended to 8 ms, the processing load on the CPU 11 required for detecting the call signal can be reduced. As a result, an increase in the processing load due to the multifunctionalization of the facsimile apparatus can be allowed to some extent, and the multifunctionalization can be achieved. Further, as compared with the conventional case, the sampling circuit 33 is hardware-wise.
Since only the counter circuit 34 is added, it can be realized at low cost.

In the above embodiment, a sampling circuit 33 for accumulating and storing 8-bit binary data is provided, and an interrupt signal INT is sent to the CPU 11 every time the counter circuit 34 counts "8" clock pulses. And then C
The case where the PU 11 samples is shown, but for example, 1
A sampling circuit for accumulating and storing 6-bit binary data is provided, and a clock pulse is set to "1" by the counter circuit 34.
Interrupt signal INT to CPU 11 every time 6 "pulses are counted
May be transmitted and the CPU 1 may perform sampling. By doing this, the CP required to detect the call signal
The processing load on U11 can be further reduced.

In the above embodiment, the case where the present invention is applied to the facsimile machine has been described, but the call signal detecting apparatus of the present invention can be applied to other communication terminals than the facsimile machine.

[0020]

As described above in detail, according to the present invention, it is possible to provide a call signal detecting device which can reduce the processing load of the processor in detecting the call signal at low cost.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a facsimile apparatus which is an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a call signal detection device in the embodiment.

FIG. 3 is a flowchart showing interrupt processing of the CPU in the embodiment.

FIG. 4 is a block diagram showing the configuration of a conventional call signal detection device.

FIG. 5 is a waveform diagram used to describe a conventional call signal detection operation.

[Explanation of symbols]

 11 ... CPU (processor) 17 ... Telephone circuit 18 ... Modem 26 ... Telephone line 27 ... Line switching relay 32 ... Binarization circuit 33 ... Sampling circuit 34 ... Counter circuit

Claims (1)

[Claims] 1. An analog signal received through a line is divided into two.
A binarizing circuit for binarizing, a sampling circuit for taking in binarized data by the binarizing circuit every time a clock pulse is input, accumulating and storing in the taking order, and counting the pulse number of the clock pulse. A counter circuit that outputs an interrupt signal when the value reaches a value, and whether or not the data stored and stored in the sampling circuit is read in response to the input of the interrupt signal and the read data is analyzed to receive a call signal of a predetermined frequency. A call signal detection device comprising: a processor for determining whether or not the call signal is detected.