JPH09185890A - Ferroelectric storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a sufficient signal voltage from a memory cell and to obtain the sufficient S/N by providing a charge transfer element to a signal line. SOLUTION: A memory cell MC is made up of a ferroelectric capacitor using a ferroelectric material for the insulator and an NMOSFET. Then a control signal FPC is used to turn off a precharge switch PC. Then a word line W is set to a word lien voltage VCH at selection to select a cell MC. The NMOSFET in the cell MC is conductive and a voltage being a difference between a voltage VDH of a data line D and a plate voltage VPL is fed to the ferroelectric capacitor and residual polarization is read by the data line as charges. In this case, the voltage of the line D changes tentatively but the voltage of the line D is restored to the voltage VDH at precharge again by the NMOSFET of the charge transfer element BBD. As a result the charges read from the ferroelectric capacitor to the line D are transferred to a node NSA.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory device.

[0002]

2. Description of the Related Art FIG. 4 shows a basic configuration example of a ferroelectric memory according to the prior art. In the figure, MC is a memory cell, and is composed of, for example, a ferroelectric capacitor having a ferroelectric such as PZT as an insulating film and an NMOS transistor.
Information is stored by the remanent polarization of this ferroelectric capacitor. One electrode of the ferroelectric capacitor is connected to the NMOS transistor, and the other electrode (plate electrode) is supplied with a voltage (VCC / 2) that is half the power supply voltage VCC. Although only one memory cell MC is shown here for simplicity, a plurality of memory cells MC are connected to the data line D.
It is selected by the word line W and exchanges a signal with the data line D. PC is a precharge switch and precharges the data line D to the ground voltage VSS.

The operation of this configuration will be described with reference to the timing waveforms shown in FIG. In the standby state, the control signal FPC
Accordingly, the precharge switch PC is turned on, and the data line D is precharged to the ground voltage VSS. During operation, the control signal FPC turns off the precharge switch PC. Therefore, the memory cell MC is selected by setting the word line W to the word line voltage VCH at the time of selection. The NMOS transistor in the memory cell MC is turned on, and the data line D is added to the ferroelectric capacitor.
And a voltage of VCC / 2, which is the voltage difference between the plate electrode and the plate electrode, is applied, and the residual polarization is read out to the data line D as an electric charge.
As a result, the voltage of the data line D changes and the control signal FS
The sense amplifier SA is activated by A, the voltage of the data line D is amplified, and information is discriminated. Lower the word line W,
Rewriting to the memory cell MC is performed by turning off the NMOS transistor in the memory cell MC. After that, the operation SA of the sense amplifier is stopped by the control signal FSA, and the precharge switch is turned on by the control signal FPC to return to the standby state.

The movement of the ferroelectric capacitor in this operation will be described with reference to the hysteresis characteristic shown in FIG. In the figure, the horizontal axis represents the voltage applied to the ferroelectric capacitor with the plate electrode as a reference, and the vertical axis represents the amount of charge held by the ferroelectric capacitor including polarization. In the state where no voltage is applied to the ferroelectric capacitor in the standby state, the ferroelectric capacitor holds the remanent polarization and takes one of the points PS0 and PS1 in FIG. 3 according to the stored information. . When the signal is read from the memory cell MC to the data line D, since the data line D is precharged to −VCC / 2 with reference to the plate electrode, the data line capacitance CD has a slope of −CD in FIG. It is represented by straight lines LL0 and LL1. The points of intersection PR0 and PR1 between this straight line and the hysteresis curve are points taken by the ferroelectric capacitor during reading. on the other hand,
Writing is performed by setting the data line D to either VSS or VCC to set points PW0 and PW1 in FIG.

[0005]

In this operation, "0" is set.
When reading out, the polarization is not inverted, whereas '1'
When reading out, the polarization is inverted to obtain the difference in signal voltage. However, when reading '1', a smaller voltage is applied to the ferroelectric capacitor than when writing, so
The polarization is not completely inverted, and only part of the remanent polarization can be read. The amount of charge obtained as this signal is affected by the hysteresis shape, but becomes smaller as the data line capacitance CD is smaller and the slope of the load line is smaller. Further, when the data line capacitance CD is increased to increase the signal charge amount, the signal charge is distributed to the data line capacitance and the signal voltage is determined, so that the signal voltage decreases. Therefore, there is a limit to the magnitude of the signal voltage that can be obtained even if the data line capacitance is changed.
About this property, 1995 IEE International Solid-State Circuits
Conference Digest of Technical Papers, p. 71 (1995 IEEE International Solid-Sta
te Circuits Conference Digest of Technical Pap
ers, p. 71,). Due to such characteristics, a sufficient signal voltage cannot be obtained and a sufficient S / N cannot be obtained depending on the hysteresis characteristic of the ferroelectric capacitor. This problem is more serious when operating in a region where the hysteresis characteristic is not saturated at a low voltage.

An object of the present invention is to obtain a sufficient signal voltage from a memory cell using a ferroelectric capacitor and to obtain a sufficient S /
To get N.

[0007]

A feature of the present invention for achieving the above object is to have a plurality of memory cells and a signal line for exchanging signals with the plurality of memory cells. Each of the cells is provided with a charge transfer element on the signal line in a ferroelectric memory device including a capacitor having a ferroelectric insulating film and a transistor.

By using the charge transfer element, a desired voltage can be applied to the ferroelectric capacitor at the time of reading regardless of the shape of the hysteresis characteristic of the ferroelectric capacitor and the size of the data line capacitance. The purpose of is achieved.

[0009]

1 shows an example of the basic configuration of the present invention. The feature is that the charge transfer element BBD is provided between the data line D and the sense amplifier SA. In the figure, the charge transfer device BBD is an NM operating in a source follower mode.
OS transistor. MC is a memory cell,
For example, it is composed of a ferroelectric capacitor having a ferroelectric material such as PZT as an insulating film and an NMOS transistor. Information is stored by the remanent polarization of this ferroelectric capacitor.
One electrode of the ferroelectric capacitor is connected to the NMOS transistor, and the other electrode (plate electrode) is supplied with the plate voltage VPL. Although only one memory cell MC is shown here for simplicity, the data line D
Are connected to the data line D and are selected by the word line W to exchange signals with the data line D. PC is a switch for precharge, which supplies the precharge voltage VPC to the node NSA.
To supply.

The operation of this configuration example will be described with reference to the timing waveforms shown in FIG. In the standby state, the control signal FP
The precharging switch PC is turned on by C,
The node NSA is precharged to the precharge voltage VPC. At the same time, the data line D is connected to the charge transfer device BBD.
The threshold voltage VT of the NMOS transistor
Only the control voltage VH and the lower voltage VDH (= VH-VT)
It has become.

During operation, the control signal FPC turns off the precharge switch PC. Therefore, by setting the word line W to the word line voltage VCH at the time of selection,
The memory cell MC is selected. NMO in memory cell MC
The S transistor is turned on, the voltage of the difference between the voltage VDH of the data line D and the plate voltage VPL is applied to the ferroelectric capacitor, and the residual polarization is read out to the data line D as electric charge.

As a result, the voltage of the data line D temporarily changes, but the NMOS transistor of the charge transfer element BBD causes the data line D to recharge the voltage VD at the time of precharging.
Return to H. As a result, the charges read from the ferroelectric capacitor to the data line D are transferred to the node NSA.
That is, according to the amount of charge transferred from the data line capacitance CDL to the memory cell MC, the parasitic capacitance CSA of the node NSA.
The charges move from the data line capacitance CDL to the data line capacitance CDL.

Then, the sense amplifier SA is activated by the control signal FSA, the voltage of the node NSA is amplified, and information is discriminated. When the read information is "1", the data line maintains VDH. In the case of "0", the node NSA and the data line D are pulled down to the write voltage VDL of "0". A read operation is performed by transferring this information to the outside.

Further, the write operation is performed by controlling the voltage of the data line D according to the information given from the outside. The word line W is lowered and the NM in the memory cell MC is
Rewriting to the memory cell MC is performed by turning off the OS transistor. After that, the control signal FS
The operation SA of the sense amplifier is stopped by A, and the control signal FP
The precharge switch is turned on by C to return to the standby state. The voltage applied to the ferroelectric capacitor is
It is attenuated by leakage current flowing through the ferroelectric substance.

The effect of this configuration example will be described using the hysteresis characteristic of the ferroelectric capacitor shown in FIG. In the figure, the horizontal axis represents the voltage applied to the ferroelectric capacitor with the plate electrode as a reference, and the vertical axis represents the amount of charge held by the ferroelectric capacitor including polarization.

When no voltage is applied to the ferroelectric capacitor in the standby state, the ferroelectric capacitor holds the remanent polarization, and the point PS on FIG. 3 is retained according to the stored information.
It takes either 0 or PS1 position. When a signal is read from the memory cell MC to the data line D, the data line D is VD
Since it is kept at H, it becomes the point PR on FIG.

On the other hand, for writing, the data line D is set to VDL, V
This is performed by setting the points PW0 and PW1 in FIG. At the time of reading, the same voltage as that at the time of writing "1" is applied, and since the point PR and the point PW1 coincide with each other, the remanent polarization can be completely read out, and the read out by "0" and "1". 2Q difference in the amount of charge
r. Therefore, a larger amount of signal can be obtained as compared with the conventional one.

Further, in this configuration, the signal voltage to be the input of the sense amplifier is determined by the remanent polarization Qr and the parasitic capacitance CSA of the sense amplifier section, and does not depend on the data line capacitance CDL. Since the parasitic capacitance CSA can have a smaller capacitance value than the data line capacitance CDL, a larger signal voltage can be obtained. Note that the charge amount of (Qs−Qr) is also read at the time of “1” reading without polarization inversion. This charge increases the voltage applied to the charge transfer element BBD, and the charge is transferred at high speed.

Next, FIG. 7 shows a concrete example of the configuration of the present invention. In the figure, MCAL and MCAR are memory cell arrays and share a sense amplifier section SAB arranged between MCAL and MCAR. Further, a column decoder YDEC is provided commonly to the plurality of memory cell arrays and the sense amplifier section, and the column selection line YS passes over the memory cell array.

The sense amplifier section SAB is specifically constructed as follows. Data line pairs D0bL and D0tL, D1bL and D1tL, ... In the memory cell array MCAL.
Are connected to the charge transfer gates SHLG0, SHLG1 ,. Further, charge transfer gates SHRG0, SHRG1, ... Are connected to the data line pairs D0bR and D0tR, D1bR and D1tR, ... In the memory cell array MCAR. The charge transfer gate has a role of transferring charges at the time of reading and a role of selecting the left and right data line pairs. Precharge circuits PC0, PC are provided between the charge transfer gates SHLG0, SHRG0, SHLG1, SHRG1 ,.
, Sense amplifiers SA0, SA1, ..., I / O gates IOG0, IOG1 ,. The precharge circuit is composed of PMOS transistors so that the high precharge voltage VPC can be easily supplied.

A configuration example of the memory cell arrays MCAL and MCAR is shown in FIG. At the intersections of the word lines W0, W1, ... And the data line pairs D0b and D0t, D1b and D1t ,.
The memory cell array MC is provided with the memory cell MC2.
A2 is configured. The memory cell MC2 is composed of two ferroelectric capacitors and two NMs each of which uses a ferroelectric as an insulating film.
It is composed of an OS transistor. Information is stored complementarily by the residual polarization of these two ferroelectric capacitors. One electrode of the ferroelectric capacitor is connected to the NMOS transistor, and the other electrode (plate electrode) is connected to the plate lines P0, P1 ,. It should be noted that this plate line may be a single electrode instead of being a divided wiring, which is easier in terms of process and suitable for high integration.

The operation of the configuration shown in FIG. 7 will be described using the timing waveform shown in FIG. The figure shows a case where the word line W0 is selected in the memory cell array MCAL and a signal is read to the data line pair D0bL, D0tL. The plate lines P0, P1, ...
Is kept at L. In the standby state, the PMOS transistor in the precharge circuit PC0 is turned on by the control signal FPCb, and the nodes NSAb and NSAt are precharged to the precharge voltage VPC. Further, both the control signals SHL and SHR are at the voltage VH, and the data line pairs D0bL and D0tL, D0bR and D0tR are changed from the control voltage VH by the threshold voltage VT of the NMOS transistor by the charge transfer gates SHLG0 and SHRG0. It is a low voltage VDH (= VH-VT). here,
The control signal SHR turns off the NMOS transistor in the charge transfer gate SHRG0, and the data line pair D0bR
And D0tR are separated from the nodes SAb and SAt.

Next, the precharge circuit PC0 is turned off by the control signal FPCb. Therefore, the memory cell MC2 is selected by setting the word line W0 to the word line voltage VCH at the time of selection. The NMOS transistor in the selected memory cell MC2 is turned on, one of the two ferroelectric capacitors undergoes polarization reversal, and the remanent polarization is read out as a charge to the data line pair D0bL, D0tL. here,
Even if the voltages of the data line pair D0bL and D0tL change temporarily, the data line D returns to the voltage VDH at the time of precharge again by the charge transfer gate SHLG0.

As a result, the charges read from the ferroelectric capacitor to the data line D are stored in the nodes NSAb and NSAt.
Is forwarded to Then, by lowering the control signal CSN to the low level voltage VDL, the NMOS transistor in the sense amplifier SA0 is turned on. At this time, the control signal CSP is maintained at the precharge voltage VPC, and when the voltage of the nodes NSAb and NSAt decreases due to the current of the NMOS transistor, the PMOS transistor in the sense amplifier SA0 also turns on. Therefore, the nodes NSAb and NSAt are positively feedback-amplified by the sense amplifier SA0, so that one becomes the voltage VPC and the other becomes the voltage VDL. At the same time, through the charge transfer gate SHRG0, the data line pair D0b
One of L and D0tL is the voltage VDH and the other is the voltage VDL.
Then, one of the two ferroelectric capacitors in the selected memory cell MC2 is polarization-inverted.

Although not shown in FIG. 9, the column decoder YDEC selects the column selection line YS0, the input / output gate IOG0 is turned on, and the nodes NSAb and NSAb are turned on.
A read / write operation is realized by exchanging signals between the SAt and the input / output line pair IOb, IOt. Then, the word line W0 is lowered and the memory cell MC2
Rewriting to the memory cell MC2 is performed by turning off the inside NMOS transistor. After that, the control signal CSN is returned to the precharge voltage VPC, the operation of the sense amplifier SA0 is stopped, and the precharge circuit PC0 is turned on by the control signal FPCb. Then, the control signal SH
The R turns on the NMOA transistor in the charge transfer gate SHRG0, couples the data line pair D0bR and D0tR to the nodes SAb and SAt, and returns to the standby state.

As in the present embodiment, the structure using the sense amplifier for differential amplification with the data line paired can be operated with less noise, and by using the charge transfer element there, a signal transfer can be performed. The voltage is increased and the S / N ratio can be increased. That is, stable high speed operation becomes possible.

By sharing the sense amplifier section SAB between the left and right memory cell arrays MCAL and MCAR, the area occupied by the sense amplifier section can be reduced, and the charge transfer gate can be used also for the role of selecting the left and right data line pairs. As a result, the area increase due to the charge transfer element can be eliminated. In addition, in this embodiment, the column decoder is shared by a plurality of sense amplifier sections to reduce the occupied area of the column decoder. At this time, it is not necessary to activate all of the plurality of sense amplifier sections at the same time, only the desired sense amplifier section is activated according to the address signal input from the outside, and the non-selected sense amplifier section remains in the standby state. Good as In that case, the input / output line pair IOb, IOt of the non-selected sense amplifier section SAB is connected to the nodes SAb, S.
By maintaining the same precharge voltage VPC as At,
It is possible to prevent unnecessary current from flowing to the input / output line pair.

The operation in the non-volatile mode in which one of the two ferroelectric capacitors in the memory cell MC2 shown in FIG. 8 has the configuration shown in FIG. did. It is possible to operate in the volatile mode used as a normal capacitor without polarization reversal of the ferroelectric capacitor with the same configuration.

The operation timing is shown in FIG. The plate lines P0, P1, ... Are set to the same voltage VDH as the data line pair at the time of precharging, except that the operation is performed by each control signal as in the nonvolatile mode operation shown in FIG. At this time, since the data line has an amplitude from the voltage VDH to VDL and is always lower than that of the plate line, the memory cell M
The two ferroelectric capacitors in C2 keep the same polarization orientation. Therefore, the memory cell MC2 is a dynamic random access memory (D
It operates similarly to a cell of RAM).

In FIG. 10, when the word line W0 is raised to VCH and the accumulated charge is read from the memory cell, the charge transfer gate SHLG0 transfers the charge to the nodes NSAb and NSAt. The accumulated charge is not distributed to the parasitic capacitance of the data line, the signal voltage is determined by the parasitic capacitance of the sense amplifier section, and a large signal voltage can be obtained by charge transfer as in the operation shown in FIG.

As described above, in the volatile mode operation in which the polarization reversal is not applied to the ferroelectric capacitor, the ferroelectric capacitor is not fatigued, so that the number of operations is not limited.
Normally, information is held by accumulated charge in the volatile mode operation shown in FIG. 10, saved in remnant polarization when the power is off, and the residual polarization is read out when the power is on and recalled to the accumulated charge, thereby limiting the number of operations. A non-volatile memory can be realized. This save operation is the same as the operation shown in FIG.
In the state where the data line pair D0bL, D0tL is amplified to VDL, VDH, the plate line P0 is set to the voltage VPL,
This can be achieved by lowering the word line to VSS. The recall operation can be realized by lowering the word line to VSS after setting the plate line P0 to the voltage VDH in the state shown in FIG. 9 in which the data line pair D0bL and D0tL is amplified to VDL and VDH. .

In FIG. 10, the operation in the non-volatile mode in which the polarization directions of both of the two ferroelectric capacitors in the memory cell MC2 shown in FIG. 8 are aligned in the configuration shown in FIG. 7 has been described. With the same configuration, it is possible to perform an operation in which the polarization of the two ferroelectric capacitors is reversed but the polarization is not inverted at the time of reading.

The operation timing is shown in FIG. The data line pair D0bL, D0tL is connected to the plate lines P0, P1,
Other than precharging to the same voltage VPL as that of ..., It operates by each control signal similarly to the operation in the volatile mode shown in FIG. That is, the signal line SPC that supplies the precharge voltage is set to the plate voltage VPL. As a result, the nodes NSAb and NSAt and the data line pair D0bL and D0.
All of tL, D0bR and D0tR are precharged to the voltage VPL. When the word line W0 is raised to VCH and the accumulated charge is read from the memory cell, the plate line and the data line have the same voltage. Therefore, the ferroelectric capacitor has only the voltage due to the redistribution of the accumulated charge originally stored. The remnant polarization is maintained without being added. At this time, the charge transfer gate SHLG0 does not perform charge transfer and serves only as a gate for selecting the left and right data line pairs. The signal voltage is positively feedback-amplified by the sense amplifier SA0 and the data line pair is opened to the voltages VDL and VDH, whereby the signal charge is rewritten in the memory cell. At this time, a voltage is applied to the ferroelectric capacitor, but the polarization direction is the same as that before reading. However, when the data line is reversed by the write operation, the polarization direction of the ferroelectric capacitor is reversed.

In this operation, the polarization of the ferroelectric capacitor is not inverted at the time of reading and fatigue is not caused, so that the number of operations can be extended. Normally, this operation reads the accumulated charge, and even when the power is turned on, the residual polarization is read by the operation in the non-volatile mode and recalled to the accumulated charge. It is possible to realize a non-volatile memory with a guaranteed number of operations.

Since charge transfer is not performed in this operation, the control signal SHL is set to a sufficiently high voltage VCH to speed up the driving of the data line pair by the sense amplifier and shorten the cycle time. . Further, since the precharge is performed by the plate voltage VPL, the control signal FPCb may be the voltage VDH when the precharge circuit PC0 is turned off.

In the above, as shown in FIG. 8, a memory cell array composed of a memory cell MC2 using two ferroelectric capacitors and two NMOS transistors.
The case of using MCA2 was explained, but 1 memory cell is used.
It is also possible to configure with one ferroelectric capacitor and one NMOS transistor.

An example of the memory cell array is shown in FIG. In the memory cell array MCA1 shown in the figure, the word line W1
0, W11, ..., Data line pair D10b and D10t, D
The memory cell MC1 is arranged at the intersection of either 11b or D11t, .... This is an arrangement similar to a two-intersection memory cell having a folded data line structure generally used in DRAM. The memory cell MC1 has a smaller number of elements than the memory cell MC2 of FIG. 8, and is suitable for high integration. However, since signals are exchanged with only one of the data line pairs, the reference voltage must be generated in the other of the data line pairs during reading in the operation in the non-volatile mode as shown in FIG. Therefore, the dummy word lines DW0 and DW1 and the data line pair D10b and D10 are used.
A dummy cell DC including two ferroelectric capacitors at the intersection of any one of t, D11b and D11t ,.
1 is provided. These two capacitors are
The capacitor area is half that of the ferroelectric capacitor of the memory cell MC1. One of the capacitors uses the plate electrode as VPL to perform polarization reversal at the time of reading. The other capacitor has the plate electrode as VDH and always maintains the same polarization direction and does not perform polarization reversal.

A dummy cell based on such a principle is disclosed in, for example, Japanese Patent Laid-Open No. 2-110893. The dummy cell of this method attempts to read out exactly half the amount of charge to the data line in the case where the ferroelectric capacitor of the memory cell does or does not undergo polarization inversion. The amount of remanent polarization read out depends on the shape of the hysteresis characteristic, and even a dummy cell having such a configuration cannot obtain an intermediate signal amount. However, in the present invention, since the remanent polarization can be completely read out from the ferroelectric capacitor by using the charge transfer, a desired charge amount can be obtained from the dummy cell and the intermediate value between “0” and “1” can be obtained. Can generate a reference voltage of.

In the configuration and operation described with reference to FIGS. 7 to 12, various voltages such as the precharge voltage VPC and the control voltage VH are used. Next, a method of generating these voltages will be described.

FIG. 13 shows a structural example of the power supply system of the ferroelectric memory device according to the present invention. Ferroelectric memory device chip CH
The feature is that the power supply voltage VCC from the outside of P is used as it is as the precharge voltage VPC. Further, the ground voltage VSS from the outside is used as it is as the low level voltage VDL of the data line.

In FIG. 13, PVSS is a power supply terminal to which the ground voltage VSS is supplied, and is a power supply terminal to which the PVCC power supply voltage VCC is supplied. GH is a step-down circuit that generates a control voltage VH used to control charge transfer.
The power supply voltage VC is configured in the same manner as a well-known voltage limiter circuit used in M or the like so that the NMOS transistor used in the charge transfer element during charge transfer operates in the saturation region.
C is stepped down and the control voltage VH is supplied. GDH is a step-down circuit that generates a high level data line voltage VDH,
It is composed of a reference NMOS transistor MDH, a bias current source CDH, and a buffer circuit BDH. The NMOS transistor MDH is an NMO used as a charge transfer element.
To have the same threshold voltage VT as the S transistor,
Make the channel length and substrate voltage the same.
The NMOS transistor MDH and the bias current source CDH form a source follower, and by sufficiently reducing the current of the bias current source CDH, a voltage lower than the control voltage VH by a threshold voltage VT is output. This voltage is supplied by the buffer circuit BDH.

By thus forming the step-down circuit VDH using the reference NMOS transistor MDH,
Even if the transistor characteristics vary, the voltage VDH lower than the control voltage VH by the threshold voltage VT can be supplied correspondingly.

GPL is a voltage dividing circuit for generating the plate voltage VPL and supplies an intermediate voltage between the high level voltage VDH and the low level voltage VDL of the data line. GCH is a booster circuit that generates the voltage VCH of the word line at the time of selection, and is composed of, for example, a well-known charge pump circuit and boosts the power supply voltage VCC so that the NMOS transistor of the memory cell can write the voltage VDH. Voltage VC
Supply H. The peripheral circuits such as the input / output buffer and the control circuit are operated with the power supply voltage VCC and the ground voltage VSS.

As in this configuration, the voltages VCC and VSS supplied from the outside are set as the voltages VPC and VDL used for charging / discharging the data lines as they are, even if the peak current due to charging / discharging the data lines is large. Stable operation is possible. Further, by generating another internal voltage such as VCH or VH in the chip, it is possible to operate with a single external power supply by VCC and VSS.

FIG. 14 shows another configuration example of the power supply system. The feature is that the power supply voltage VCC from the outside is used as it is as the high level voltage VDH of the data line. Also,
The ground voltage VSS from the outside is used as it is as the low level voltage VDL of the data line.

In FIG. 14, PVSS and PVCC are power supply terminals to which the ground voltage VSS and the power supply voltage VCC are supplied, respectively. GPC is a booster circuit that generates a precharge voltage VPC, and sufficiently boosts and supplies the power supply voltage VCC. This output voltage is also used as the word line voltage VCH. GHU is a control voltage V used for controlling charge transfer
This is a step-down circuit for generating H, which is composed of an NMOS transistor MH for reference, a bias current source CH, and a buffer circuit BH, and is a voltage VPC boosted by a step-up circuit GPC.
Step down. The NMOS transistor MH has the same channel length and the like so as to have the same threshold voltage VT as the NMOS transistor used as the charge transfer element. The current of the bias current source CH is made sufficiently small and the voltage VDH is
A voltage higher than the threshold voltage VT by a buffer circuit BH
Supplied by With this configuration, even if the transistor characteristics vary, the voltage VD
A voltage VH higher than H by a threshold voltage VT can be supplied. GPL is a voltage dividing circuit that generates the plate voltage VPL. The peripheral circuits such as the input / output buffer and the control circuit are operated with the power supply voltage VCC and the ground voltage VSS.

As in this configuration, the voltages VCC and VSS supplied from the outside are directly used as the high-level and low-level voltages VDH and VDL of the data line, so that the external power supply voltage and the data line amplitude become the same. It is possible to reduce the external power supply voltage. Further, when the operation shown in FIG. 11 is performed during the normal operation, the operation of the step-down circuit GH can be stopped because the control voltage VH is not used in such operation. Further, since the pre-charge voltage VPC is not used, the booster circuit GPC has only the ability to supply the word line voltage VCH statement, and the power consumption can be reduced by lowering the frequency of the charge pump.

In addition to the configuration described above, the present invention can be variously modified without departing from the spirit thereof.
For example, the precharge circuits PC0 and PC shown in FIG.
It is also possible to configure 1, ... With NMOS transistors instead of PMOS transistors. In this case, in order to perform the operation as shown in FIG. 9, the control signal F in FIG.
A signal having a phase opposite to that of PCb may be used as a signal having an amplitude capable of turning on / off the PMOS transistor with respect to the voltage from VDL to VPC. By using an NMOS transistor, it can be arranged close to the charge transfer gate, and in some cases the layout becomes easy. Further, the charge transfer gates SHRG0, SHRG1, ... And SHLG0, SHRG0, SHLG1 and SHRG1, in FIG.
It is also possible to configure ... With PMOS transistors instead of NMOS transistors. In that case, the relationship between the precharge voltage and the plate voltage of the sense amplifier and the voltage of the data line may be reversed. At that time, the plate voltage can be made equal to the ground voltage so that the plate voltage does not change when the power is turned off. By doing so, there is no risk of voltage being applied to the ferroelectric capacitor when the power is off, and stable operation is possible. Further, the memory cell can be composed of a ferroelectric capacitor and a PMOS transistor.

[0049]

According to the present invention, in a ferroelectric memory device in which a memory cell is composed of a ferroelectric capacitor having a ferroelectric material as an insulating film and a MOS transistor, it is sufficient for the ferroelectric capacitor at the time of reading. A high S / N can be obtained by applying a voltage to completely read out the remanent polarization.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a basic configuration example of the present invention.

FIG. 2 is an operation timing chart of the configuration example shown in FIG.

FIG. 3 is a hysteresis characteristic diagram of a ferroelectric capacitor for explaining the operation of the configuration example shown in FIG.

FIG. 4 is a circuit diagram showing a configuration example according to a conventional technique.

FIG. 5 is an operation timing chart of a configuration example according to the related art.

FIG. 6 is a hysteresis characteristic diagram of a ferroelectric capacitor for explaining an operation of a configuration example according to a conventional technique.

FIG. 7 is a circuit diagram showing a sense amplifier section of a specific configuration example of the present invention.

FIG. 8 is a circuit diagram showing a memory cell array in which a memory cell is composed of two ferroelectric capacitors and two MOS transistors.

9 is an operation timing chart of the configuration example shown in FIG.

10 is an operation timing chart of a volatile mode of the configuration example shown in FIG.

11 is an operation timing chart of another operation in the volatile mode of the configuration example shown in FIG.

FIG. 12 shows a ferroelectric capacitor having one memory cell and one memory cell.
FIG. 3 is a circuit diagram showing a memory cell array composed of individual MOS transistors.

FIG. 13 is a block diagram showing a configuration example of a power supply system.

FIG. 14 is a block diagram showing another configuration example of a power supply system.

[Explanation of symbols]

BBD ... Charge transfer element, D ... Data line, MC ... Memory cell, PC ... Precharge circuit, SA ... Sense amplifier, W
... word line.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroki Fujisawa 2326 Imai, Ome City, Tokyo, Hitachi, Ltd. Device Development Center (72) Inventor Kazuhiko Kajiya 2326 Imai, Ome City, Tokyo Hitachi, Ltd. Device Development Center Within

Claims (19)

[Claims] 1. A plurality of memory cells and a signal line for exchanging signals with the plurality of memory cells, wherein each of the plurality of memory cells includes a capacitor and a transistor using a ferroelectric material as an insulating film. A ferroelectric memory device including: a ferroelectric memory device, wherein a charge transfer element is provided on the signal line. 2. The transistor according to claim 1, wherein the transistor is M
An OS transistor, the gate electrode of the MOS transistor is connected to a select line for selecting the memory cell,
A ferroelectric memory device in which one of a drain electrode and a source electrode of the MOS transistor is connected to the signal line and the other is connected to an electrode of the capacitor. 3. The method according to claim 1, wherein when any one of the plurality of memory cells is selected and a signal is read from the memory cell to the signal line, the voltage of the signal line after being read is not yet read. A ferroelectric memory device that is substantially the same as the voltage of the. 4. The charge transfer device according to claim 3, wherein the charge transfer element is M.
A ferroelectric memory device which is an OS transistor and in which the voltage of the signal line is determined by the threshold voltage of the MOS transistor. 5. A ferroelectric memory device according to claim 1, comprising a precharge means for precharging an output terminal of the charge transfer element and a sense amplifier for discriminating an output of the charge transfer element. 6. The ferroelectric memory device according to claim 5, wherein the signal line is precharged via the precharge means and the charge transfer element. 7. The ferroelectric memory device according to claim 5, wherein the precharge means is supplied with a voltage which is not included in a voltage range of the signal line in a normal operation. 8. The ferroelectric memory device according to claim 1, wherein one electrode of the capacitor is supplied with a voltage in the middle of a voltage range of the signal line in a normal operation for at least a desired period. 9. A plurality of data lines, a plurality of word lines arranged to intersect the plurality of data lines, and a plurality of plurality of data lines arranged at desired intersections of the plurality of data lines and the plurality of word lines. A ferroelectric substance including a memory cell and a sense amplifier provided corresponding to the plurality of data lines for detecting a read signal, each of the plurality of memory cells including a capacitor having a ferroelectric substance as an insulating film. In the memory device, the plurality of data lines take a first voltage or a second voltage during a write operation of a memory cell, and a source electrode and a sense electrode corresponding to each of the plurality of data lines are provided. A MOS transistor connected to the drain electrode is provided, and the gate electrode of the MOS transistor is
A third voltage that is not included in the voltage range from the first voltage to the second voltage is supplied for at least a desired period, and the MOS transistor is supplied for at least the desired period.
Precharge means is provided at the node where the MOS transistor and the sense amplifier are connected, and the precharge means is supplied with a fourth voltage not included in the voltage range from the first voltage to the second voltage. Ferroelectric memory device. 10. The ferroelectric memory device according to claim 9, wherein the plurality of data lines are paired. 11. The difference between one of the first voltage and the second voltage and the third voltage is effectively the absolute value of the threshold voltage of the MOS transistor. The same ferroelectric memory device. 12. The memory device according to claim 9, wherein each of the plurality of memory cells has the capacitor having a first electrode and a second electrode, and the first electrode has the first voltage and the second electrode. A fifth voltage intermediate between the second voltage and the second voltage is supplied for at least a desired period, the gate electrode is connected to one of the plurality of word lines, and one of the drain electrode and the source electrode is connected to the plurality of the plurality of word lines. Of the data line, and a MOS transistor connected to the second electrode of the capacitor and the other of the data lines. 13. The ferroelectric memory device according to claim 12, wherein each of the plurality of memory cells includes two capacitors and two MOS transistors. 14. The ferroelectric memory device according to claim 12, wherein each of the plurality of memory cells includes one capacitor and one MOS transistor. 15. A ferroelectric memory device according to claim 9, further comprising means for generating the third voltage. 16. A ferroelectric memory device according to claim 15, further comprising means for supplying the first voltage and the fourth voltage from the outside. 17. A ferroelectric memory device according to claim 15, wherein each of the first voltage and the second voltage has a stage supplied from the outside. 18. A plurality of data lines, a plurality of word lines arranged so as to intersect with the plurality of data lines, and a plurality of word lines arranged at desired intersections of the plurality of data lines and the plurality of word lines. A ferroelectric substance including a memory cell and a sense amplifier provided corresponding to the plurality of data lines for detecting a read signal, each of the plurality of memory cells including a capacitor having a ferroelectric substance as an insulating film. In the memory device, when a memory cell is selected by the plurality of word lines, there is provided a mechanism for making the voltage of the data line effectively the same before and after driving the word line. Ferroelectric memory device. 19. The ferroelectric memory device according to claim 18, wherein the mechanism uses charge transfer.