JPH09180495A - Semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reduction in operating speed and to suppress the expansion of a semiconductor element region. SOLUTION: A semiconductor storage has a row/column separation circuit 1, a light amplifier 2, a read amplifier 3, a logic circuit 4, a row decoder 5, a column decoder 6, a read/write selection circuit 7, and a cell array part 8. Then, when a colunm address signal 103 corresponding to a faulty memory cell included in the cell array part 8 is inputted in the column decoder 6, the column address is judged to be a faulty address and a column address signal 108 corresponding to a redundancy switch corresponding to the substituted address is outputted and is inputted to the cell array part 8. Also, in the column decoder 6, no precharge signal input is required from the logic circuit 4 as different from before.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device.

[0002]

2. Description of the Related Art The structure of a typical conventional semiconductor memory device is shown in the block diagram of FIG. 4, and an example of partial structure of a memory cell portion inside the semiconductor memory device is shown in FIG. . As shown in FIG. 4, the semiconductor memory device includes a cell array section 8 and a row / column separation circuit that receives an address signal 101 input from the outside and outputs the row address signal 102 and a column address signal 103 separately. The column address signal 10 is input via the circuit 1, the row decoder 5 that inputs and decodes the row address signal 102, outputs the row address decode signal 107 and inputs the row address decode signal 107, and the precharge signal 117.
3 is input and decoded, the column address decode signal 108 to be replaced and the normal column address decode signal 109 are output, and is input to the cell array unit 8 and the column decoder 6 and writing / reading of data to / from the cell array unit 8 are performed. And a read / write selection circuit 7 for switching and selecting, and a data signal 110 for writing input from the outside
A write amplifier 2 which inputs, amplifies and outputs, a read amplifier 3 which amplifies read data output from the cell array section 8 via the read / write selection circuit 7 and outputs the data as a data signal 111 to the outside. Control signal 116
Input to the row / column separation circuit 1, the column decoder 6 and the read / write selection circuit 7, respectively.
17 and a logic circuit 4 which outputs a read / write selection signal 105.

Incidentally, in recent years, the number of memory cells has increased as the storage capacity of the cell array section 8 has increased,
Due to this, the probability of occurrence of defects in the memory cell tends to increase. As a method for complementing the defect of the memory cell and reducing the defect occurrence rate in the cell array section 8 as described above, at the time of writing / reading data, the address of the defective memory cell is not normally changed to another normal value. A method is adopted in which the yield of the cell array section 8 is improved by replacing the memory cells. The above-mentioned conventional example is an example in which only the function corresponding to the column address is added as the redundancy function to the cell array section 8, and the column address decoder signal 108 output from the column decoder 6 is the above-mentioned alternative memory cell. Is a signal input as a redundancy Y switch input to the redundancy dedicated digit line.

In FIG. 4, for address-related signal processing, first, an address signal 101 input from the outside
Is a logic circuit 4 in the row / column separation circuit 1.
It is controlled by the row / column separation signal 104 input by the input, separated into the row address signal 102 and the column address signal 103, output, and input to the corresponding row decoder 5 and column decoder 6, respectively. In the row decoder 5, the relevant row address signal 102
Are decoded, output as a row address decode signal 107, and input to the corresponding word line of the cell array section 8. Similarly, in the column decoder 6, the precharge signal 1 output from the logic circuit 4 is also output.
The column address signal 103 is decoded via 17 and, as described above, the address decode signal 108 is output as the redundancy Y switch input and is input to the corresponding redundancy-dedicated digit line of the cell array section 8 and the column address. Decode signal 109 is Y
It is output as a switch input, and the cell array unit 8 is also output.
Is input to the corresponding digit line of.

The operation of column address decode signals 108 and 109 will now be described with reference to the partial circuit diagram of cell array portion 6 of FIG. In FIG. 6, word lines 118 and 119, data bus 12
2, memory cells 27, sense amplifiers 28 and transfer gates 29 are arranged corresponding to the arrangement of digit lines 123, 124 and 125 and the input of sense amplifier activation signals 120 and 121. FIG.
For convenience of explanation, it is a diagram showing only one part of the cell array portion 8. In reality, a large number of memory cells, sense amplifiers, transfer gates, word lines, digit lines, etc. are provided corresponding to the storage capacity of the cell array portion 8. Are arranged. In FIG. 6, the redundancy Y switch input to the two transfer gates 29 for the memory cell 27 corresponding to the 2-bit column address, and the transfer of the redundancy memory cell 27 corresponding to the 1-bit column address. The state of the redundancy Y switch input to the gate 29 is shown. That is, the digit line 12 corresponding to the Y switch input
For 3 and 124, a digit line 125 corresponding to the redundancy Y switch input is provided. The digit line 125 is a redundancy-dedicated digit line which is utilized when a memory cell arranged on another digit line fails. Although two Y switch inputs corresponding to the digit lines 123 and 124 are shown as Y switch inputs in FIG. 6, one Y switch input of these Y switch inputs is shown in FIG. Only the column address decode signal 109 is shown and the other column address decode signals as Y switch inputs are omitted. The row address decode signal 107 described above is input to the word lines 118 and 119 and the like, and the sense amplifier activation signal 12 is input.
0 and 121 are signals input from the logic circuit 4, and the data bus 122 is used for inputting / outputting data signals.

In general, the column address decode signal 109 output from the column decoder 6 is as described above.
It is a signal of a plurality of bits corresponding to the number of arranged memory cells formed corresponding to the storage capacity of the cell array portion 8, and a plurality of Y switch inputs inputted to a plurality of transfer gates 29 arranged corresponding to respective columns. It is formed as a signal. In addition, the column address decode signal 10
Reference numeral 8 is formed as a redundancy Y switch input signal input to the transfer gate 29 arranged on the redundancy digit line 125 corresponding to the column address. In this Y switch input, and in FIG. 6, the redundancy Y switch input that is input to the transfer gate 29 of the redundancy memory cell 27 corresponding to the 1-bit column address, and 2 for the memory cell 27 that corresponds to the 2-bit column address. The state of the redundancy Y switch input to each transfer gate 29 is shown.

The above-mentioned column decoder 6 has a structure according to one embodiment of the column decoder 6 used in the present invention of FIG. 2, and the column redundancy circuit 9 is provided.
, A redundancy Y switch activation block 10, a column predecoder 11 and a column main decoder 12. However, in the column decoder 6 in the conventional example, as described in FIG. 4, the precharge signal 117 output from the logic circuit 4 is used.
Is input to the column decoder, and the precharge signal 117 is input to the column redundancy circuit 9 shown in FIG. 2. FIG. 2 is a diagram showing an embodiment of the present invention. Precharge signal 117
Is not listed. In addition, the column redundancy circuit 9
FIG. 5 shows an example of its detailed internal configuration.

In FIG. 5, the precharge signal 117 output from the logic circuit 4 is input to the inverting circuit formed by the PMOS transistor 20 and the NMOS transistor 21, and the level signal 118 is output on its output line.
Is output. Redundancy fuses 22-0, 22-1, 22-2, 22 are connected to the output lines of the inverting circuit, respectively.
-3, 22-4, 22-5, 22-6, 22-7, 22
-8 and 22-9, and NMOS transistors 23-0, 23-1, 23-2, 23-3, 2 connected in series to the respective redundancy fuses and having their drains grounded.
3-4, 23-5, 23-6, 23-7, 23-8 and 23-9 are provided, and on the other hand, 5 bit column addresses y ₀ , y ₁ , y ₂ , y ₃ and y
_The column address signal 103 including ₄ is input, and the column address y ₀ is inverted by the gate of the NMOS transistor 23-0 and the inverter 24-1 to obtain the NMO.
The column address y ₁ is input to the gate of the S transistor 23-0, inverted by the gate of the NMOS transistor 23-2 and the inverter 24-2 and input to the gate of the NMOS transistor 23-3, and the column address y ₂ is The column address y is inverted by the gate of the NMOS transistor 23-4 and the inverter 24-3 and input to the gate of the NMOS transistor 23-5.
₃ is inverted by the gate of the NMOS transistor 23-6 and the inverter 24-4 and input to the gate of the NMOS transistor 23-7.
₄ is inverted by the gate of the NMOS transistor 23-8 and the inverter 24-5 and input to the gate of the NMOS transistor 23-9. The level of the level signal 118 is set corresponding to the input of these column address signals, and is output as the redundancy determination signal 112 via the inverters 25 and 26. The redundancy determination signal 112 is input to the redundancy Y switch activation block 10 and the column predecoder 11, and the redundancy Y switch activation block 10 outputs the above-mentioned redundancy column address decode signal 108 and the column predecode signal. The column predecode signal 113 output from the decoder 11 is output as a column address decode signal 108 via the column main decoder 12 and input to the cell array unit 8. Note that FIG. 5 shows an example of the case where the column address signal 103 is a 5-bit signal, but in the operation description, generality is not lost even if such a limited example is used. .

Next, referring to FIG. 5, a column redundancy circuit 9 for identifying the input of a defective column address signal and outputting a predetermined redundancy judgment signal 112 will be described.
The defective address setting method and operation will be described. First, in the inverting circuit formed by the PMOS transistor 20 and the NMOS transistor 21, the "L" level precharge signal 1 corresponding to the normal operation mode is provided.
17 is input. Further, as the column address signal 103, the column address signals corresponding to the defective memory cells to be replaced when they are determined to be defective in the write / read operation test for the cell array unit 8 are y ₀ , y ₁ , y ₂ , If y ₃ and y ₄ , then
A column address signal 103 including the defective column addresses y ₀ , y ₁ , y ₂ , y ₃ and y ₄ is input. Then, in response to the input of such a defective column address, the redundancy judgment signal 112 output from the inverter 26 is output at the "H" level, and the redundancy fuses 22-0 to 22-9 are selected. One of the redundancy fuses is artificially blown. As an example thereof, the defective column address is y ₀ = “0”, y ₁ =
_{"1", y 2 = "} 1", y 3 = "0" and y ₄ =
In the case of "1", the redundancy fuses 22-1, 2
2-2, 22-4, 22-7 and 22-8 are pulled out, and the respective circuits are disconnected from the ground point. By doing so, for example, the column address signal 103 input from the row / column separation circuit 1 becomes y ₀ =
_{"0", y 1 = "} 1", y 2 = "1", when was the aforementioned defective address comprising y ₃ = "0" and y ₄ = "1", the redundancy fuse 22-0, 22-3, 2
The NMOS transistors 23-0, 23-3, 23-5, 23-6, and 23-9 corresponding to 2-5, 22-6, and 22-9 are all turned off, and other NMO
Although all the S transistors are in the conductive state, the level signal 118 is held at the “H” level because all the corresponding redundancy fuses are cut off. Therefore, the “H” level signal is output as the redundancy determination signal 112 via the inverters 25 and 26. When the column address signal 103 corresponding to a normal memory cell is input, at least the NMOS
Transistors 23-0, 23-3, 23-5, 23-6
One of the NMOS transistors 23 and 23-9 is turned on, the level signal 118 is transferred to the “L” level, and the redundancy determination signal 112 is output as the “L” level signal. That is, when the defective column address signal 103 to be replaced is input, the redundancy determination signal 112 is output as an "H" level signal.

The redundancy judgment signal 112 is output as a column address decode signal 108 acting as a redundancy Y switch input via the redundancy Y switch activation block 10 and is input to a corresponding digit line of the cell array section 8. Further, via the column predecoder 11 and the column main decoder 12,
It is output as a column address decode signal 109 which acts as a Y switch input corresponding to a column address signal from the outside, and is input to a corresponding digit line of the cell array section 8. The column predecoder 11 has a built-in logic function for preventing the digit line corresponding to the defective memory cell to be replaced from being activated.

In FIG. 4, at the time of writing (writing) data, a data input signal 110 input from the outside is amplified by the write amplifier 2 and read / write.
It is input to the write selection circuit 7. In the read / write selection circuit 7, the data input signal 110 is selected and input to the data bus of the cell array section 8 under the control of the read / write separation signal 105 input from the logic circuit 4, and the row decoder 5 and the column It is stored in the memory cell designated by the row address tecode signal 107 and the column address decode signal 109 respectively output from the decoder 6. Further, at the time of reading data, the data stored in the memory cell designated by the row address tecode signal 107 and the column address decode signal 109 is transferred to the data via the read / write selection circuit 7 and the read amplifier 3. The output signal 111 is output to the outside.

[0012]

In the conventional semiconductor memory device described above, in the column redundancy circuit, when the column address signal corresponding to the normal memory cell is input, the level signal on the output line of the inverting circuit in the column redundancy circuit is input. When the level of 118 is pulled to the “L” level through the redundancy fuse and the NMOS transistor, there is a drawback that the operation speed is reduced when the size of the NMOS transistor is small.
As a countermeasure, in order to increase the operation speed, the NMOS
When increasing the size of the transistor, the NM
There is a drawback that the semiconductor device area occupied by the OS transistor becomes excessively large.

[0013]

According to another aspect of the present invention, there is provided a semiconductor memory device including a memory cell array, which receives an address signal from the outside to write / read data to / from the memory cell array. As a means for discriminating an address signal corresponding to a defective memory cell in a cell array and generating and outputting a predetermined redundancy determination signal, on / off control is performed by a predetermined redundancy activation signal input to a gate, and externally input. N-bit address signal Ai
N first MOS transistors corresponding to respective inputs (i = 0, 1, 2, ..., N) and the n first MOS transistors are respectively connected in series. n first redundancy fuses and n for inverting and outputting the n-bit address signal Ai
N first inverters and ON / OFF control by the redundancy activation signal input to the gate,
N corresponding to each input of the n-bit address signal Ai which is inverted and output by the first inverters.
Second MOS transistors and the n second M transistors
The n first redundancy fuses and terminals adjacent to each other are connected in series to the OS transistor and are adjacent to each other at a specific node Ni corresponding to the output side with respect to the input of the n-bit address signal Ai. N second redundancy fuses connected, a second inverter that inverts and outputs the redundancy activation signal, and a redundancy activation signal that is inverted and output by the second inverter that is input to the gate Corresponding to n second MOS transistors which are on / off controlled and are inserted and connected between the wiring connected to the n node Ni and the ground point, and the input of the n-bit address signal Ai. And an AND circuit that outputs a logical product of the address signals output to the n nodes Ni. It is characterized by being configured with a constant circuit.

The address signal corresponding to the defective memory cell in the memory cell array is a column address signal. As a means for discriminating the column address signal and generating and outputting a predetermined redundancy determination signal,
The n-bit address signal Ai may be defined as an n-bit column address signal.

Alternatively, the address signal corresponding to the defective memory cell in the memory cell array is a row address signal, and the n bits are used as means for discriminating the row address signal and generating and outputting a predetermined redundancy determination signal. Address signal Ai may be defined as an n-bit row address signal.

[0016]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. As shown in FIG. 1, in this embodiment, a cell array unit 8 and an address signal 101 input from the outside are provided.
, And the row / column separation circuit 1 for separating and outputting the row address signal 102 and the column address signal 103, and the row address signal 102 for input and decoding,
A row decoder 5 that outputs a row address decode signal 107 and inputs it to the cell array unit 8 and a column address signal 103 that inputs and decodes it and outputs a column address decode signal 108 to be replaced and a normal column address decode signal 109. Then, the column decoder 6 input to the cell array unit 8, the read / write selection circuit 7 for switching and selecting the writing / reading of data to / from the cell array unit 8, and the data signal 1 for writing input from the outside.
A write amplifier 2 which inputs 10, amplifies and outputs, and a read amplifier 3 which amplifies read data output from the cell array unit 8 through the read / write selection circuit 7 and outputs the amplified data as a data signal 111 to the outside. Predetermined control signal 1
In response to 16 inputs, the row / column separation circuit 1, the read / write selection circuit 7 and the cell array section 8 are supplied with the row / column separation signal 104, the read / write selection signal 105 and the sense amplifier activation signal 106, respectively. And a logic circuit 4 for outputting. The main point of the present embodiment different from the conventional example is the difference in the internal configuration of the column decoder 6 and its operation function, and therefore, the precharge signal input from the logic circuit 4 is not required.

FIG. 2 is a block diagram showing the configuration of the column decoder 6, and FIG. 3 is a diagram showing the internal configuration of the column redundancy circuit 9 in FIG. In FIG. 2, the operations of the redundancy Y-stitch activation block 10, the column predecoder 11, the column main decoder 12, and the like are the same as those in the above-described conventional example, and therefore the description thereof will be omitted and refer to FIG. The operation of the column redundancy circuit 9 will be described.

In FIG. 3, the level of the redundancy activation signal 114 is set by the resistance and the divided voltage of the fuse 14, and the redundancy activation signal 11 is set.
The levels of 4 are NMOS transistors 16-0, 16-1, 16-2, 16-3, 16-4, 16-5, ...
It is supplied to the gates of 16-2n and 16- (2n + 1). The level of the redundancy activation signal 114 is inverted by the inverter 17- (n + 1) and supplied to the gates of the NMOS transistors 18-1, 18-2, 18-3, ..., 18-n. ing.
Column address signal 103 output from the row / column separation circuit 1, in the present embodiment, the column address of n bits A _0, A _1, A _2, is formed by .................. A _n, The column address A ₀ corresponds to the NMOS transistor 16-0 and the redundancy fuse 15-0.
Inverter 17-1, NMOS transistor 16-
AND through 1 and redundancy fuse 15-1
The column address A ₁ input to the circuit 19 is the NMOS
Transistor 16-2 and redundancy fuse 15
-2, inverter 17-2, NMOS transistor 1
6-3 and the redundancy fuse 15-3
The column address A ₂ input to the ND circuit 19 is NM
It is input to the AND circuit 19 through the OS transistor 16-4 and the redundancy fuse 15-4, the inverter 17-3, the NMOS transistor 16-5 and the redundancy fuse 15-5, and the column address A _n.
Is an NMOS transistor 16-2n, a redundancy fuse 15-2n, an inverter 17-n, and an NMO.
It is input to the AND circuit 19 via the S transistor 16- (2n + 1) and the redundancy fuse 15- (2n + 1). Further, the NMOS transistors 18-1, 18-2, 18-3, ..., 18 acting to pull the levels of the level signals 115-0 to 115-n input to the AND circuit 19 to the ground level. -N is the redundancy activation signal 11 supplied to each gate
On / off control is performed by the inversion level of 4.

Next, referring to FIG. 3, the redundancy fuses 15-0, 1 correspond to the input of the defective column address.
5-1, 15-2, 15-3, 15-4, ……………,
In the case of pulling out 15-2n and 15- (2n + 1), the fuse 14 is pulled out and the redundancy activation signal 114 is set to the "H" level. This gives N
All the MOS transistors 18-1 to 18-n are turned off. Then, as in the case of the conventional example, the n-bit column addresses A ₀ , A ₁ , A ₂ , ... ...... A _n forming the defective column address signal to be replaced are input and the AND circuit is input. In order that the redundancy judgment signal 112 output from 19 is output at "H" level, one of the redundancy fuses 15-0 to 15- (2n + 1) is artificially pulled out to disconnect the circuit. To do. For example, the defective column address is A ₀ =
“0”, A ₁ = “1”, A ₂ = “1”, ……………… A
_{When n} = "0", the redundancy fuse 15-
0, 15-3, 15-5, ..., 15-2n are pulled out, and the respective circuits are disconnected and excluded as input circuits to the AND circuit 19. By doing this,
For example, if the column address signal 103 input from the row / column separation circuit 1 is A ₀ = “0”, A ₁ = “1”,
In the case of the above defective column address including A ₂ = “1”, ..., And A _n = “0”, the address A ₀
= “0” is inverted by the inverter 17-1, and N
The level signal 115 of “1” level is passed through the MOS transistor 16-0 and the redundancy fuse 15-0.
-0 is input to the AND circuit 19 and the address A ₁ =
“1” is input to the AND circuit 19 as the level signal 115-1 of “1” level via the NMOS transistor 16-2 and the redundancy fuse 15-2, and the address A ₂ = “1” is set to the NMOS transistor 16-2. -4
And “1” via the redundancy fuse 15-4.
The level signal 115-2 of the level is input to the AND circuit 19, and the address A _n = "0" is inverted by the inverter 17-n to generate the NMOS transistor 16
-(2n + 1) through the level signal 1 of "1" level
15-n is input to the AND circuit 19. Therefore,
Redundancy judgment signal 1 output from the AND circuit 19
As "12", an "H" level signal is output. When the column address signal 103 corresponding to a normal memory cell is input, at least one of the level signals 115-0 to 115-n is in the state of being output at "L" level. , The redundancy judgment signal 112 output from the AND circuit 19 is always "L".
It is output as a level signal. That is, when the defective column address signal 103 to be replaced is input,
The redundancy determination signal 112 is output as an "H" level signal. When there is no defective column address, the redundancy activation signal 114 is set to the “L” level without pulling out the fuse 14 to turn on all the NMOS transistors 18-0 to 18-n. It is also possible to always set the redundancy judgment signal 112 output from the AND circuit 19 to the “L” level.

In FIG. 2, the redundancy judgment signal 112 is the redundancy Y switch activation block 10.
Is output as a column address decode signal 108 which acts as a redundancy Y switch input, and is input to the corresponding digit line of the cell array section 8. Further, the column address decode signal 109 that receives the column address signal 103 and the redundancy judgment signal 112 and acts as a Y switch input corresponding to the column address signal from the outside via the column predecoder 11 and the column main decoder 12. And is input to the corresponding digit line of the cell array section 8. The column predecoder 11 has a built-in logic function for preventing the digit line corresponding to the defective memory cell to be replaced from being activated.

As is apparent from FIG. 3, in the present embodiment, it becomes unnecessary for the column decoder 6 to receive the supply of the precharge signal from the logic circuit for determining the defective column address, and the internal structure of the column decoder 6 is reduced. In the column redundancy circuit 9, when the column address signal corresponding to the normal memory cell is input, there is a problem caused by the size of the NMOS transistor when the inversion signal level of the precharge signal is set to the ground level via the redundancy fuse. As a result, it is possible to prevent a decrease in the operating speed, and it is possible to avoid an increase in the semiconductor element region accompanying the increase in the size of the NMOS transistor.

In the above embodiment, the operation has been described by taking as an example the case where a defective memory cell corresponding to a column address is interposed as the object of redundancy, but the present invention is not limited to this. However, it goes without saying that the present invention is effectively applied to the case where the redundancy target is a row address and the case where both the column address and the row address are targets.

[0024]

As described above, according to the present invention, an address signal corresponding to a redundancy memory cell to be converted is discriminated from an address signal input corresponding to a defective memory cell, and a redundancy discrimination signal is output. The means includes a MOS transistor that is connected in series to a predetermined redundancy fuse, is controlled by a redundancy activation signal, and functions as a transfer gate for the address signal of a plurality of bits, via the MOS transistor and the corresponding conductive redundancy fuse. By providing a means for outputting the redundancy judgment signal by the logical product of the level signals output by
It is possible to prevent a decrease in operating speed without being affected by the size of the transistor, and it is possible to suppress the expansion of the semiconductor element region due to the increase in size of the MOS transistor.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a column decoder in the first embodiment.

FIG. 3 is a circuit diagram showing an embodiment of a column redundancy circuit according to the present embodiment.

FIG. 4 is a block diagram showing a conventional example.

FIG. 5 is a circuit diagram showing an example of a column redundancy circuit in a conventional example.

FIG. 6 is a circuit diagram showing a portion of a cell array section.

[Explanation of symbols]

1 Row / Column Separation Circuit 2 Write Amplifier 3 Read Amplifier 4 Logic Circuit 5 Row Decoder 6 Column Decoder 7 Write / Write Select Circuit 8 Cell Array Section 9 Column Redundancy Circuit 10 Redundancy Y Switch Activation Block 11 Column Predecoder 12 Column Main Decoder 13 Resistance 14 Fuse 15-0 to 15- (2n + 1), 22-0 to 22-9
Redundancy fuses 16-0 to 16- (2n + 1), 18-1 to 18-n,
21, 23-0 to 23-9 NMOS transistors 17-1 to 17- (2n + 1), 24-1 to 24-5,
25, 26 Inverter 19 AND circuit 20 PMOS transistor 27 Memory cell 28 Sense amplifier 29 Transfer gate 101 Address signal 102 Row address signal 103 Column address signal 104 Row / column separation signal 105 Read / write separation signal 106 Sense amplifier activation signal 107 Row Address decode signal 108, 109 Column address decode signal 110 Data input signal 111 Data output signal 112 Redundancy determination signal 113 Column predecode signal 114 Redundancy activation signal 115-0 to 115-n, 118 Level signal 116 Control signal 117 Precharge signal 118, 119 Word lines 120, 121 Sense up activation signal 122 Data bus 123 to 125 bit lines

Claims (3)

[Claims] 1. A semiconductor memory device including a memory cell array, which receives an address signal from the outside and writes / reads data to / from the memory cell array, and determines an address signal corresponding to a defective memory cell in the memory cell array. As a means for generating and outputting a predetermined redundancy judgment signal, on / off control is performed by a predetermined redundancy activation signal input to the gate, and an n-bit address signal Ai (i = 0) input from the outside is controlled. , 1, 2, ..., N) corresponding to respective inputs of n first MOS transistors, and n first MOS transistors connected in series to the n first MOS transistors, respectively. 1 redundancy fuse, and n first n-bit address signals Ai for inverting and outputting the n-bit address signal Ai. Inverters and n number of n-bit address signals Ai which are on / off controlled by the redundancy activation signal input to the gate and are inverted and output by the n number of first inverters. Second n-type MOS transistor and the n-th second n-type MOS transistor are respectively connected in series and correspond to the output side for the input of the n-bit address signal Ai.
In, the n second redundancy fuses to which terminals are connected to the adjacent n first redundancy fuses, the second inverter that inverts and outputs the redundancy activation signal, and the second inverter On / off control is performed by the redundancy activation signal inverted and output by the second inverter, and n second n-channels are inserted and connected between the wiring connected to the n node Ni and the ground point. A redundancy determination circuit configured to include at least a MOS transistor and an AND circuit that outputs a logical product of the address signals output to the n nodes Ni in response to the input of the n-bit address signal Ai. A semiconductor memory device comprising: 2. An address signal corresponding to a defective memory cell in the memory cell array is a column address signal, and the n bits are used as means for determining the column address signal and generating and outputting a predetermined redundancy determination signal. 2. The semiconductor memory device according to claim 1, wherein the address signal Ai is defined as an n-bit column address signal. 3. An address signal corresponding to a defective memory cell in the memory cell array is a row address signal, and the n bits are used as means for determining the row address signal and generating and outputting a predetermined redundancy determination signal. 2. The semiconductor memory device according to claim 1, wherein said address signal Ai is defined as an n-bit row address signal.