JPH0917961A - Electrostatic protector of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To improve the protection ability to high frequency of surge voltage by inserting a C-B junction diode and a B-E junction diode in parallel between a signal terminal and a first power terminal. CONSTITUTION: A junction diode 3a between a collector and a base slow in response and a junction diode 10 between an emitter and a base quick in response are connected in parallel between a signal terminal and a positive power source. When positive surge voltage is applied, low-frequency components large in power leave off to high potential power wiring 8, with forward currents flowing to both of the protective diodes 3a and 10, and high-frequency components small in power leave off to the high-potential power wiring 8, with forward currents flowing to the protective diode 10. Therefore, the transistor of the inner circuit gets to hard to be broken by high-frequency to low-frequency surge voltage, and the electrostatic breakdown strength of a semiconductor integrated circuit can be raised, without using special manufacture process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for protecting a semiconductor integrated circuit from damage caused by static electricity or surge, that is, an electrostatic protection apparatus for a semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIGS. 3 and 4 are a circuit diagram and a sectional view, respectively, for explaining an example of a conventional electrostatic protection device for a semiconductor integrated circuit.

The electrostatic protection device 100 includes an output signal line 9a connected to an output signal terminal 1a and a low potential power supply wiring 7
(Connected to the _VEE power supply terminal) and low-potential power supply wiring 8 (connected to the _Vcc power supply terminal) have protection diodes 2a and 3a, respectively.

The protection diode 2a has an n ⁺ -type lead region 1
7a and n ⁻ -type semiconductor layer 15c provided with 7a
(Epitaxial layer) and an anode composed of ap ⁺ -type diffusion layer 16b formed in the n ^-- type semiconductor layer 15c. The protection diode 3a includes an n ⁺ -type lead region 17b and an n ⁻ -type semiconductor layer 15 provided with the same.
e and a cathode formed of ap ⁺ -type diffusion layer 16d formed in the n ⁻ -type semiconductor layer 15e.

The signal output terminal 1a is connected to a peak rectifier circuit 201
A terminal for receiving an output signal of a differential transistor pair of Q2 and Q3, a constant current source I1, a load transistor Q4, and a load resistor R1, and a peak rectifier circuit 201 are connected to a differential amplifier circuit 202 (Q6, Q7). , And a constant current source I2, load resistors R3 and R4. Vref is a reference voltage. The time constant for charging the capacitor C1 by the emitter follower Q1 is smaller than the time constant for discharging from C1 via Q2.

The emitter follower Q1 is an n ⁻ type semiconductor layer 1
5f (connected to the n ⁺ type buried layer 12c and the n ⁺ type extraction region 17c) is a collector region, the p ⁺ type diffusion layer 16e formed in the n ⁻ type semiconductor layer 15f is a base region, and the p ⁺ type diffusion layer 1
6e has an n ⁺ -type diffusion layer 18b formed as an emitter region.

When a positive surge voltage is applied to the output signal terminal 1a, a forward current flows through the protection diode 3a, and when a negative surge voltage is applied, a forward current flows through the protection diode 2a to protect the peak rectifier circuit. Is done.

In the electrostatic protection device 100, the internal circuit is not limited to a peak rectifier circuit, but is generally provided between an input signal terminal or an output signal terminal (generally referred to as a signal terminal) of the semiconductor integrated circuit and the internal circuit. Is provided.

FIGS. 5 and 6 are a circuit diagram and a sectional view showing another conventional example.

Between the input signal terminal 1 and the low-potential power supply wiring 7, a protective diode 2 having an n ⁺ -type lead region 17d and an n ⁺ -type buried layer 12d as a cathode and the p ^- type semiconductor substrate 11 as an anode; The p ⁺ type diffusion layer 16f is used as a collector region, and n
^- type semiconductor layer 15h of the base region, p ^- -type semiconductor substrate 1
A PNP transistor 4 having 1 as an emitter is inserted. Further, between the high potential power supply wiring 8 and the protection diode 3 having the p ⁺ type diffusion layer 16d as an anode, the n ⁻ type diffusion layer 15e, and the n ⁺ type extraction region as a cathode, are inserted. Note that the p ⁺ type diffusion layer 16 f also serves as the protection resistor 5. The PNP transistor 4 compensates for the lack of protection capability of the protection diode 2 against a negative surge voltage, and the protection resistor 5 alleviates a sharp voltage applied to the input PNP transistor 6.

[0011]

The conventional electrostatic protection device described above has a collector-base junction diode (C-C).
B diode). The CB diode can have a considerable discharge capacity by occupying a large area. However, the CB diode has an n ⁻ -type diffusion layer having a low impurity concentration (formed simultaneously with the collector region of the vertical NPN transistor constituting the internal circuit). ), The response is slow due to the parasitic resistance, and the protection ability of the internal circuit against high-frequency surge voltage is poor. The same applies to the conventional example described with reference to FIGS.

The problem that the protection ability against the high-frequency surge voltage is poor is more serious as the capacitance as viewed from the signal terminal is larger as in the conventional example described with reference to FIGS. In FIG. 3, the output signal terminal 1a
When a positive overvoltage is applied to the capacitor C1 to accumulate charge in the capacitor C1, as described above, the transistor Q1 is discharged because of the large time constant discharged through the transistor Q2 and the slow response of the protection diode 3a. The breakdown occurs first, and the peak rectifier circuit 201 is destroyed.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an electrostatic protection device for a semiconductor integrated circuit having an improved protection capability against a high-frequency surge voltage.

[0014]

According to the present invention, there is provided an electrostatic protection device for a semiconductor integrated circuit, wherein a first first conductivity type semiconductor layer on a surface portion of a semiconductor substrate is a collector region, and a first semiconductor layer formed in the collector region is provided. Including a bipolar transistor having a second conductivity type diffusion layer as a base region, a first first conductivity type diffusion layer formed in the base region as an emitter region, a first power supply line and a second power supply line In a static electricity protection device for a semiconductor integrated circuit provided with a circuit, a second first conductivity type semiconductor layer on a surface portion of the semiconductor substrate is connected to the first power supply wiring, and the second first conductivity type semiconductor is provided. The second formed in the layer
A first protection diode formed by connecting the second conductivity type diffusion layer to a signal terminal, and a third first protection diode on a surface portion of the semiconductor substrate.
A third second conductivity type diffusion layer formed in the conductivity type semiconductor layer is connected to the signal terminal, and a second first conductivity type diffusion layer formed in the third second conductivity type diffusion layer is connected to the signal terminal. A second protection diode connected to the first power supply wiring.

Here, the parasitic capacitance of the second protection diode is preferably smaller than that of the first protection diode.

Further, the signal terminal may be an output signal terminal connected to an emitter follower that extracts the output of the peak rectifier circuit.

[0017]

Function: CB junction diode (first protection diode) and BE junction diode (second protection diode)
Are inserted in parallel between the signal terminal and the first power supply terminal. For a surge voltage of a polarity having a low frequency, a forward current flows through both of them at a low frequency, and a response at a high frequency. Forward current flows through the second protection diode, which is fast. The response speed can be further increased by reducing the parasitic capacitance of the second protection diode.

[0018]

1 and 2 are a circuit diagram and a sectional view of a semiconductor chip, respectively, showing an embodiment of the present invention.

In this embodiment, a semiconductor substrate (element isolation oxide film 13 and isolation p ^{+) is formed} by epitaxially growing an n ⁻ type semiconductor layer 15 on a p ⁻ type semiconductor substrate 11 made of silicon.
In the element forming region partitioned by the mold embedded region 14, n is formed near the interface between the p ⁻ type semiconductor base 11 and the n ⁻ type semiconductor layer 15.
^{A +} type buried layer 12 is provided. The first n ⁻ -type semiconductor layer 15f on the surface portion of FIG.
A bipolar transistor (Q1) having a first p ⁺ -type diffusion layer 16e formed in 5f as a base region and a first n ⁺ -type diffusion layer 18b formed in the base region 16e as an emitter region, a first power supply In an electrostatic protection device for an analog semiconductor integrated circuit including an internal circuit including a wiring (high-potential power supply wiring 8) and a second power supply wiring (low-potential power supply wiring 7),
The second n ⁻ -type semiconductor layer 15 on the surface of the above-mentioned semiconductor substrate
e (connected to the n ⁺ type buried layer 12b and the n ⁺ type extraction region 17b) is connected to the first power supply wiring (8), and the second p ⁺ formed in the second n ⁻ type semiconductor layer 15e is connected. Protection diode 3a formed by connecting type diffusion layer 16d to output signal terminal 1a, and a third p ⁺ type diffusion formed in third n ⁻ type semiconductor layer 15d on the surface of the semiconductor substrate. The layer 16c is connected to the output signal terminal 1a by the signal wiring 9a, and the third p
Second n ⁺ type diffusion layer 18 formed in ⁺ type diffusion layer 16 c
a connected to the first power supply wiring (8).

The n ^- type semiconductor layers 15a to 15g are all formed by the same epitaxial process, and the subscripts of a to g are given for convenience of explanation. Symbol 12, 1
The same applies to subscripts attached to 3,14,16,17,18. The p ⁺ -type diffusion layers 16b to 16e are simultaneously formed in the n ⁻ -type semiconductor layers in each element formation region by a so-called base diffusion step. Similarly, the n ⁺ -type diffusion layers 18a and 18b are simultaneously formed in the emitter diffusion step. Bipolar transistors Q2 to Q7 constituting the internal circuit have the same structure as Q1 except for the occupied area. The low-potential power supply wiring 7, the high-potential power supply wiring 8, and the output signal wiring 9a are aluminum alloy films that selectively cover a silicon oxide film (not shown) that covers the surface of the semiconductor substrate.

Further, it has the same protection diode 2a as the conventional example described with reference to FIGS.

When a negative surge voltage is applied to the output signal terminal 1a, a forward current flows through the protection diode 2a. When a positive surge voltage is applied, a relatively low-frequency component with a large power flows through both the protection diodes 3a and 10 in a forward direction to pass through the high-potential power supply wiring 8, and a relatively high-frequency component with a small power is protected. A forward current flows through the diode 10 and escapes to the high potential power supply wiring 8. The cathode of the protection diode 10 is an n ⁺ -type diffusion layer 18a.
The response speed is high because the parasitic resistance is smaller than that of the cathode a containing the n ⁻ type semiconductor layer 15e. It is more preferable that the parasitic capacitance of the protection diode 10 be smaller than that of the protection diode because the response speed can be further increased. For this purpose, the PN junction area of the protection diode 10 may be made smaller than that of the protection diode.

Although the breakdown voltage of the protection diode 10 is lower than that of the protection diode 3a, the large parasitic capacitance of the high-potential power supply wiring (the n ⁺ type buried layer and the p ^+
( There is a PN junction capacitance of the mold substrate), the static electricity is also accumulated, so that the breakdown due to the excessive breakdown current hardly occurs.

As described above, the peak rectifier circuit has been described as an example in which the internal circuit is easily broken by the high frequency surge voltage. However, regardless of the type of the internal circuit and the signal terminal, a BE junction diode having a high response speed is used. It is clear that this can improve the immunity to high frequency surge voltages. Further, the present invention can be applied not only to analog integrated circuits but also to digital integrated circuits such as ECL gate arrays.

[0025]

As described above, according to the present invention,
A protection diode using a CB junction of a transistor as a protection element against a positive surge voltage to a signal terminal and a protection diode using an EB junction of a transistor are arranged in parallel on a semiconductor substrate on which a semiconductor integrated circuit is formed. Therefore, there is an effect that the transistor of the internal circuit is not easily destroyed by the high frequency or low frequency surge voltage, and the resistance to electrostatic breakdown of the semiconductor integrated circuit can be increased without using a special manufacturing process.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a sectional view showing one embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional example.

FIG. 4 is a sectional view showing a conventional example.

FIG. 5 is a circuit diagram showing another conventional example.

FIG. 6 is a sectional view showing another conventional example.

[Description of Signs] 1 Input signal terminal 1a Output signal terminal 2, 2a Protection diode 3, 3a Protection diode (CB diode) 4 PNP transistor 5 Protection resistor 6 NPN transistor 7 Low potential power supply wiring 8 High potential power supply wiring 9 Input Signal wiring 9a Output signal wiring 10 Protection diode (E-B diode) 11 p-type silicon substrate 12a to 12dn ⁺ buried layer 13a to 13e Isolation oxide film 14a to 14e P ⁺ buried layer for separation 15a to 15g n ⁻ type semiconductor layers 16 a to 16 ep ⁺ type diffusion layers 17 a to 17 c n ⁺ type extraction regions 18 a, 18 b n ⁺ type diffusion layers 100, 100 a Static protection device 201 Peter rectifier circuit 202 Differential amplifier C1, C2 Capacitor I1, I2 Constant current source R1 to R4 Resistance Q1 to Q7 NPN transistor V _CC High potential power supply terminal V _EE low potential power supply terminal

Claims (3)

[Claims] 1. A semiconductor device comprising: a first first conductivity type semiconductor layer on a surface portion of a semiconductor substrate; a collector region; a first second conductivity type diffusion layer formed in the collector region; a base region; and a base region. An electrostatic protection device for a semiconductor integrated circuit, comprising: a bipolar transistor having a first first conductivity type diffusion layer as an emitter region; and an internal circuit including a first power supply line and a second power supply line. A second first conductivity type semiconductor layer on the surface of the semiconductor device is connected to the first power supply wiring, and a second second conductivity type diffusion layer formed on the second first conductivity type semiconductor layer is connected to a signal terminal. A first protection diode connected to the semiconductor substrate, and a third second conductivity type diffusion layer formed on a third first conductivity type semiconductor layer on the surface of the semiconductor substrate, connected to the signal terminal; The second first conductive layer formed in the third second conductive type diffusion layer An electrostatic protection device for a semiconductor integrated circuit, comprising: a second protection diode formed by connecting an electric diffusion layer to the first power supply wiring. 2. The method according to claim 1, wherein the parasitic capacitance of the second protection diode is the first.
2. The electrostatic protection device for a semiconductor integrated circuit according to claim 1, wherein the parasitic capacitance is smaller than the parasitic capacitance of the protection diode. 3. The electrostatic protection device for a semiconductor integrated circuit according to claim 1, wherein the signal terminal is an output signal terminal connected to an emitter follower that extracts an output of the peak rectifier circuit.