JPH09179095A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To dispense with external circuitry and also to reduce a power consumption by treating as a reference potential a different potential from a substrate potential of a semiconductor integrated circuit comprising a scanning line driving circuit for an input signal inputted to the scanning driving circuit. SOLUTION: An intermediate voltage input circuit of a scanning line driving circuit (common driver) references a potential GND (or a potential Vcc) which is an intermediate voltage of a liquid crystal driving voltage between a potential V×H and a potential V×L, and converts an input signal of the voltage level between a potential Vcc and potential GND, into an internal logic signal of the voltage level between a potential V×C (for example, -15V) and a potential V×L, referred to a substrate potential (for example, -20V) of a semiconductor integrated circuit as the reference potential. Thus, since the internal logic circuit references the substrate potential V×L can operates with the internal logic signal of the voltage level between the potential V×C and the potential V×L, the circuit can be comprised of standard CMOS circuits and can reduce the power consumption.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a technique effective when applied to a scanning line driving circuit in a simple matrix type liquid crystal display device.

[0002]

2. Description of the Related Art STN (Super Twisted)
Nematic) simple matrix type liquid crystal display devices are widely used as display devices such as notebook personal computers.

FIG. 14 is a block diagram showing a schematic structure of a conventional STN type simple matrix type liquid crystal display device, 101 is a display control device, 102 is a power supply circuit, and 103.
Is a conversion circuit, LCD is a liquid crystal display panel, IC-U1, I
C-U2, IC-U3, IC-Un are upper drain drivers (data line drive circuits), IC-L1, IC-L
2, IC-L3, IC-Ln are lower drain drivers (data line drive circuits), IC-C1, IC-C2, IC
-C3, IC-C4, IC-C5 are common drivers (scan line driving circuits).

In FIG. 14, a liquid crystal panel control device 10 is shown.
1 is each segment driver (IC-U1 to IC-Un, IC-L1 to IC-Ln) based on a display control signal and display data transferred from the host computer side or the like.
And controls each common driver (IC-C1 to IC-C5).

The power supply circuits 102 have different Vx.
H, V2, V3, V4, VxL, VxC, Vcc, GN
The voltage of D is generated, and the voltage of V2, the voltage of V4, the voltage of Vcc, and the voltage of GND are generated in each segment driver (IC
-U1 to IC-Ln), and supplies the voltage of VxH, the voltage of V3, the voltage of VxL, and the voltage of VxC to each common driver (IC-C1 to IC-C5).

A liquid crystal display panel (LCD) includes a pair of glass substrates arranged to face each other with a liquid crystal in between, and a liquid crystal side surface of one glass substrate extends in the X direction and in the Y direction. M common electrodes (scanning lines) arranged in parallel are formed, and each of the m common electrodes is connected to the corresponding common driver (IC-C1 to IC-C5).

Further, n segment electrodes (data lines) extending in the Y direction and arranged in parallel in the X direction are formed on the liquid crystal side surface of the other glass substrate. The two segment electrodes are divided into upper and lower parts, and each of the n divided segment electrodes is divided into two corresponding upper segment drivers (IC-U1 to IC-U).
n) or each of the corresponding lower segment drivers (IC-L1 to IC-Ln).

The intersection of the plurality of segment electrodes and the plurality of common electrodes constitutes a pixel region, and each upper segment driver (IC-U1 to IC-Un) and each lower segment driver (IC-L1 to Driving voltages are applied to the plurality of segment electrodes and the plurality of common electrodes from the IC-Ln) and the common drivers (IC-C1 to IC-C5) to drive the pixels.

In the simple matrix type liquid crystal display device, the driving voltages applied to the plurality of segment electrodes and the plurality of common electrodes are inverted at a predetermined cycle so that no DC voltage is applied to the liquid crystal. A so-called AC drive method is employed.

FIG. 15 is a view for explaining the data line drive voltage applied to the segment electrodes and the scan line drive voltage applied to the common electrode of the conventional STN type simple matrix type liquid crystal display device shown in FIG. FIG.

As shown in FIG. 15, for example, when the alternating signal (M) is at a high level, V4 supplied from the power supply circuit 102 is supplied to each segment electrode of data "1".
The drive voltage of is “0” for each segment electrode,
When the drive voltage of V2 supplied from the power supply circuit 102 is applied and the alternating signal (M) is at Low level,
The power supply circuit 102 is connected to each segment electrode of data “1”.
The drive voltage of V2 supplied from the power supply circuit 102 supplies V4 to the segment electrodes of the data “0”.
Drive voltage is applied.

Similarly, when the alternating signal (M) is at the high level, the power supply circuit 10 is connected to the selected common electrode.
When the alternating voltage signal (M) is at the low level, the VxH drive voltage supplied from 2 is applied with the VxL drive voltage supplied from the power supply circuit 102 to the selected common electrode, and is not selected. The drive voltage of V3 supplied from the power supply circuit 102 is applied to the common electrode regardless of whether the alternating signal (M) is at the high level or the low level.

FIG. 16 shows the segment drivers (IC-U1 to IC-Un, IC-L1 to IC-L) shown in FIG.
n) and each common driver (IC-C1 to IC-
It is a block diagram showing a schematic structure of C5).

As shown in FIG. 16, each segment driver (IC-U1 to IC-Un, IC-L1 to IC-L).
n) is a segment input buffer 111, a segment internal logic circuit 112, a segment output buffer 11
3, a segment liquid crystal drive voltage output circuit 114.

Each segment driver (IC-U1 to IC
-Un, IC-L1 to IC-Ln) includes display data (Din) from the display control device 101, and a display control signal (clock (CL1, CL) of logic signal voltage level).
2), the alternating signal (M)) is input, and the display data (Din) and the display control signal correspond to the input signal shown in FIG.

Each segment driver (IC-U1
To IC-Un, IC-L1 to IC-Ln), display control signals other than the clocks (CL1, CL2) and the alternating signal (M) described above are also input as display control signals from the display control device 101. Although input, it is omitted in FIG.

Each segment driver (IC-U1 to IC
-Un, IC-L1 to IC-Ln) are the display control device 1
01 for display data latch clock (CL
2) The display data (Din) is taken into the internal logic circuit 112 via the input buffer 111 according to 2), and one horizontal display data (Din) for each segment electrode is supplied to the liquid crystal drive voltage by the output timing control clock (CL1). The display data (Di) is output to the output circuit 114.
n) and the alternating signal (M), the power supply circuit 102
The V2 or V4 voltage supplied from the liquid crystal drive voltage output circuit 114 is output to the segment electrodes.

In this case, each segment driver (IC
-U1 to IC-Un, IC-L1 to IC-Ln) output a carry signal as an output signal via the output buffer 113, and the carry signal of the previous stage is directly input to the carry input of the drain driver of the next stage. The carry signal controls the display data fetching operation of each segment driver to prevent the wrong display data from being fetched by the segment driver.

Further, each common driver (IC-C1 to I
C-C5) includes a common input buffer 220, a common internal logic circuit 230, an output buffer (1) 240, and a common liquid crystal drive voltage output circuit 250. The liquid crystal drive voltage output circuit 250 outputs the level shifter (4) 251. And a buffer (2) 252.

Each common driver (IC-C1 to IC-C
5), a display control signal (clock (CL1), alternating signal (M) and frame signal (FLM)) of logic signal voltage level is input from the display control device 101, and this display control signal is shown in FIG. It corresponds to the input signal.

Each common driver (IC-C1 to I-I
In C-C5), as the display control signals input from the display control device 101, display control signals other than the clock (CL1), the alternating signal (M) and the frame signal (FLM) are also input. It is omitted in FIG.

Each common driver (IC-C1 to IC-C
5) is 1 by the frame signal (FLM) input from the display control device 101 and the clock (CL1).
A common electrode driven every horizontal scanning time is selected by the internal logic circuit 230, and the voltage of VxH supplied from the power supply circuit 102 based on the alternating signal (M) to the selected common electrode, or The liquid crystal drive voltage output circuit 250 outputs the voltage of VxL to the common electrode, and the common electrodes other than the selected common electrode are supplied with the voltage of V3 from the power supply circuit 102. Output from the output circuit 250 to the common electrode.

In this case, each common driver (IC-C
1 to IC-C5) output a carry signal as an output signal via the output buffer (1) 240, and the carry signal of the previous stage is directly input to the carry input of the common driver of the next stage. The common electrodes driven every horizontal scanning time are sequentially selected.

The conversion circuit 103 includes a common driver (IC
-C1 to IC-C5) input signals (frame signal (FLM), clock (CL1), alternating signal (M)) of logic signal voltage levels to the common drivers (IC-C1 to IC-C5). ) Is an input voltage range in which VxL + Vcc to VxL (for example, −15 V to −2).
0V) potential.

[0025]

FIG. 17 shows the segment drivers (IC-U1 to IC-Un, I) shown in FIG.
It is a figure which shows the voltage level of the input signal of C-L1-IC-Ln) and each common driver (IC-C1-IC-C5), an internal logic signal, and an output signal.

Generally, a logic signal is a signal having a high level of a potential Vcc (for example, 5 V) and a low level of a potential GND (for example, 0 V), that is, a potential GND.
(Or potential Vcc) is a signal having a reference potential and a voltage level of potential Vcc to potential GND, and this logic signal voltage level corresponds to an intermediate potential of the liquid crystal drive voltage of potential VxH to potential VxL.

Then, each segment driver (IC-U
1 to IC-Un, IC-L1 to IC-Ln), the voltage level of the drive voltage (V2, V4) output to each segment electrode is equal to or lower than the logic signal voltage level. Each segment driver (IC-U1 to IC-U1
It is possible to control IC-Ln).

Therefore, each segment driver (IC
-U1 to IC-Un, IC-L1 to IC-Ln), the input buffer 111, the internal logic circuit 112, the output buffer 113, and the liquid crystal drive voltage output circuit 114 have the potential V.
Standard CMOS (Complement) having cc (for example, 5 V) and potential GND (for example, 0 V) as power supply potentials.
ary Metal-Oxide-Semicondu
Ctor) circuit.

However, each common driver (IC-
C1 to IC-C5) need to apply the liquid crystal drive voltage of VxH or VxL from the liquid crystal drive voltage drive circuit 250 to each common electrode.
Is a well-known high breakdown voltage CMO in which the potential VxH (for example, 20V) and the potential VxL (for example, -20V) are power source potentials.
It must be composed of S circuits.

Therefore, as shown in FIG. 17, the logic signal voltage level (potential Vcc to potential GND) becomes the intermediate potential of each common driver (IC-C1 to IC-C5), that is, the undefined region of the CMOS circuit. The input signal could not be recognized as a control signal.

Further, each common driver (IC-C1 to I
C-C5) input buffer 220, internal logic circuit 2
30 and output buffer (1) 240 in standard CMOS
If it is configured by a circuit, it is possible to reduce power consumption and increase speed.

However, as shown in FIG. 18, when the standard CMOS circuit and the high withstand voltage CMOS circuit are formed on the same semiconductor substrate, it is necessary to pair with the substrate potential reference MOS.

FIG. 18 shows a standard CMOS circuit and a high withstand voltage CM.
It is sectional drawing which shows an example which comprised the OS circuit and the same P-type semiconductor substrate.

As shown in FIG. 18, when the standard CMOS circuit and the high breakdown voltage CMOS circuit are formed on the same P-type semiconductor substrate, the substrate potential is one of the power supply potentials of the high breakdown voltage CMOS circuit. It is necessary to set the potential to VxL.

Therefore, each common driver (IC-C
1 to IC-C5), the input buffer 220, the internal logic circuit 230, and the output buffer (1) 240 are the same P
In the case of a standard semiconductor circuit and a standard CMOS circuit, as shown in FIG.
0, internal logic circuit 230 and output buffer (1)
240 indicates a potential VxC (for example, -15V) and a potential Vx.
It was necessary to set L and the power supply potential.

Therefore, each common driver (IC-C1
-IC-C5), the input signal of the logic signal voltage level, that is, the potential GND (or the potential Vcc) is used as a reference potential, and the input signal whose voltage level is the potential Vcc to the potential GND is input to each common driver (IC). -C1-IC
-C5) is an input voltage range in which the substrate potential VxL of the semiconductor integrated circuit is a reference potential, and the voltage level is the potential Vx.
The conversion circuit 1 converts the internal logic signal of C to the potential VxL into
I had to shift by 03.

As described above, in the conventional simple matrix type liquid crystal display device, each common driver (IC-C1 to IC-
The voltage level of the input signal input to C5) is converted by an external conversion circuit into each common driver (IC-C1 to IC-C).
5) needs to shift to the input voltage range where it operates,
There was a problem that the number of parts increased.

As can be understood from FIG. 17, the output signal (carry signal) output from the output buffer (1) 240 of each common driver (IC-C1 to IC-C5) is also the substrate potential of the semiconductor integrated circuit. A signal whose voltage level is VxC to VxL with VxL as a reference potential, and an external conversion circuit is required to convert this output signal into a logic signal voltage level, resulting in an increase in the number of parts. There was a problem.

In order to solve the above problems, as shown in FIG. 19, a double well structure is adopted so that the standard CMOS circuit is independent of the semiconductor substrate on which the high breakdown voltage CMOS circuit is formed. Good.

FIG. 19 shows a standard CMOS circuit and a high withstand voltage CM.
It is sectional drawing which shows one example which comprised the OS circuit and the P-type semiconductor substrate independently.

However, in the CMOS circuit shown in FIG. 19, since it is necessary to form a double well, a dedicated manufacturing apparatus or a dedicated manufacturing process is required, and the CMOS shown in FIG. There is a problem that the circuit cannot be manufactured, and there is a problem that the cost increases.

Further, in order to solve the above problems,
When each of the common drivers (IC-C1 to IC-C5) is composed of a P-type semiconductor substrate, the input buffer 220, the internal logic circuit 230 and the output buffer (1) 240 may have a circuit structure of only PMOS transistors. ,
In that case, there are problems that power consumption increases and high-speed operation cannot be performed.

The present invention has been made to solve the above-mentioned problems of the prior art. An object of the present invention is to eliminate the need for an external conversion circuit in a liquid crystal display device and to increase power consumption. To provide a technique capable of operating a scanning line driving circuit by an input signal of a voltage level with a potential different from a substrate potential of a semiconductor integrated circuit forming the scanning line driving circuit as a reference potential without causing the above. is there.

Another object of the present invention is to eliminate the need for an external conversion circuit in a liquid crystal display device and increase the substrate potential of a semiconductor integrated circuit forming a scanning line drive circuit without increasing power consumption. It is an object of the present invention to provide a technique capable of outputting an output signal having a voltage level having different potentials as reference potentials from a scanning line driving circuit.

Another object of the present invention is to provide a technique capable of applying a high voltage to a gate of a liquid crystal display device without reducing the mutual conductance (gm) of a MOS transistor used in a scanning line driving circuit. That is.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0047]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A first electrode substrate having a plurality of data lines, a second electrode substrate having a plurality of scanning lines orthogonal to the data lines, the first electrode substrate and the second electrode substrate A liquid crystal panel sandwiched between a liquid crystal panel and a liquid crystal panel, a data line drive circuit for applying a data line drive voltage to the plurality of data lines, and a scan line drive for applying a scan line drive voltage to the plurality of scan lines. In a liquid crystal display device including a circuit and a display control device that controls the data line driving circuit and the scanning line driving circuit, the scanning line driving circuit is configured by a semiconductor integrated circuit, and is input to the scanning line driving circuit. The input signal is an input signal whose reference potential is a potential different from the substrate potential of the semiconductor integrated circuit forming the scanning line driving circuit.

(2) In the above-mentioned means (1), the scanning line driving circuit inputs an input signal whose reference potential is a potential different from the substrate potential of the semiconductor integrated circuit to the substrate potential of the semiconductor integrated circuit. First to convert to an internal signal
It is characterized by including the level shift means of.

(3) In the above-mentioned means (2), the first level shift means comprises an input buffer composed of a MOS transistor of a conductivity type different from that of the semiconductor substrate of the semiconductor integrated circuit, and a CMOS circuit structure. 1 level shifter and a second level shifter having a CMOS circuit configuration, the input buffer determines the High level and the Low level of the input signal, and based on the determination result in the input buffer, the first level shifter The level shifter converts the input signal into a first internal signal whose amplitude is larger than the amplitude of the input signal, using the substrate potential of the semiconductor integrated circuit as a reference potential, and the second level shifter converts the first internal signal to The substrate potential of the semiconductor integrated circuit is used as a reference potential and converted into an internal signal having the same (or equivalent) amplitude as the amplitude of the input signal. To.

(4) A first electrode substrate having a plurality of data lines, a second electrode substrate having a plurality of scanning lines orthogonal to the data lines, the first electrode substrate and the second electrode substrate A liquid crystal panel sandwiched between a liquid crystal panel and a liquid crystal panel, a data line drive circuit for applying a data line drive voltage to the plurality of data lines, and a scan line drive for applying a scan line drive voltage to the plurality of scan lines. In a liquid crystal display device including a circuit and a display control device that controls the data line driving circuit and the scanning line driving circuit, the scanning line driving circuit is configured by a semiconductor integrated circuit, and is output from the scanning line driving circuit. The output signal is an output signal whose reference potential is a potential different from the substrate potential of the semiconductor integrated circuit forming the scanning line driving circuit.

(5) In the means of (4) above, the scanning line driving circuit uses an internal signal having a substrate potential of the semiconductor integrated circuit as a reference potential and a potential different from the substrate potential of the semiconductor integrated circuit as a reference potential. Second to convert to output signal
It is characterized by comprising the level shift means of.

(6) In the means of (5), the second level shift means is composed of a third level shifter having a CMOS circuit structure and a MOS transistor of a conductivity type different from that of the semiconductor substrate of the semiconductor integrated circuit. An output buffer according to the present invention, the third level shifter uses the substrate potential of the semiconductor integrated circuit as a reference potential for the internal signal,
Converting the second internal signal whose amplitude is larger than the amplitude of the internal signal to the output buffer, and using the potential of the second internal signal different from the substrate potential of the semiconductor integrated circuit as a reference potential;
It is characterized in that an output signal whose amplitude is the same as (or equivalent to) the amplitude of the internal signal is converted.

(7) In the means (6), one of the voltages applied to the gate of the MOS transistor forming the output buffer is the substrate potential of the semiconductor integrated circuit, and one of the voltages forming the output buffer. The voltage applied to the source of the MOS transistor is a reference potential different from the substrate potential of the semiconductor integrated circuit.

(8) In the means of (7) above, the MOS transistor constituting the output buffer is a MOS transistor having a low breakdown voltage MOS structure between the drain and source and a gate having a high breakdown voltage MOS structure. Is characterized by.

According to the means (1) to (3),
In a liquid crystal display device, without using an external circuit,
Since an input signal having a reference potential different from the substrate potential of the semiconductor integrated circuit can be input to the scan line driver circuit, the number of components can be reduced, and the internal circuit of the scan line driver circuit can be replaced by the semiconductor integrated circuit. Since it can be operated by an internal signal whose substrate potential is the reference potential, the internal circuit can have a COMS circuit configuration, the power consumption can be reduced, and the operation speed can be improved.

According to the above means (4) or (5),
In a liquid crystal display device, without using an external circuit,
Since the output signal of the reference potential different from the substrate potential of the semiconductor integrated circuit forming the scanning line driving circuit can be output from the scanning line driving circuit, the number of parts can be reduced.

According to the above means (6) to (8),
In the liquid crystal display device, since the low breakdown voltage MOS structure can be provided between the drain and the source of the MOS transistor that constitutes the output buffer of the scanning line driving circuit, and the high breakdown voltage MOS structure only at the gate, the MO transistor that constitutes the output buffer
The mutual inductance (gm) can be increased as compared with the case where all of the S transistors have a high withstand voltage MOS structure, which makes it possible to improve the driving capability of the output buffer of the scanning line driving circuit as compared with the conventional case. Become.

[0059]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention applied to a simple matrix type liquid crystal display device of the STN mode will be described below in detail with reference to the drawings.

In all the drawings for describing the embodiments of the present invention, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.

FIG. 1 is a block diagram showing a schematic structure of a STN type simple matrix type liquid crystal display device according to an embodiment of the present invention, and 101 is a display control device.
102 is a power supply circuit, LCD is a liquid crystal display panel, IC-U
1, IC-U2, IC-U3, IC-Un are upper drain drivers (data line drive circuits), IC-L1, IC
-L2, IC-L3, IC-Ln are lower drain drivers (data line drive circuits), IC-C1, IC-C2
IC-C3, IC-C4, and IC-C5 are common drivers (scan line driving circuits).

In the embodiment of the present invention, a display control signal of a logic signal voltage level (frame signal (FL) is used as an input signal of each common driver (IC-C1 to IC-C5).
M), the clock (CL1) and the alternating signal (M) are input, and the common drivers (IC-C1 to IC)
The difference from the conventional STN type simple matrix type liquid crystal display device shown in FIG. 14 is that a carry signal of a logic signal voltage level is output as an output signal from -C5).

Each segment driver (IC-U1
To IC-Un, IC-L1 to IC-Ln), display control signals other than the clocks (CL1, CL2) and the alternating signal (M) are also input as display control signals input from the display control device 101. However, it is omitted in FIG.

Similarly, each common driver (IC-C1 to
As display control signals input from the display control device 101 to the IC-C5), display control signals other than the clock (CL1), the alternating signal (M) and the frame signal (FLM) are also input, but FIG. Are omitted in.

FIG. 2 shows each segment driver (IC-U1 to IC- in the liquid crystal display device according to the embodiment of the present invention.
Un, IC-L1 to IC-Ln), and a block diagram showing a schematic configuration of each common driver (IC-C1 to IC-C5).

In the embodiment of the present invention, each segment driver (IC-U1 to IC-Un, IC-L1 to I).
C-Ln) is the segment input buffer 111, the segment internal logic circuit 112, and the segment output buffer 11 as in the conventional segment driver shown in FIG.
3, the segment liquid crystal drive voltage output circuit 114, and its operation is the same as that of the conventional segment driver shown in FIG.

Each common driver (IC-C1 to IC-C
5) is composed of an intermediate voltage input circuit 120, a common internal logic circuit 130, an intermediate voltage output circuit 140, and a common liquid crystal drive voltage output circuit 150.

Here, the intermediate voltage input circuit 120 comprises a common input buffer 121, a level shifter (1) 122 and a level shifter (2) 123, and an intermediate voltage output circuit 140 includes a level shifter (3) 141 and an output buffer. (1) 142, and the liquid crystal drive voltage output circuit 150 further includes a level shifter (4) 151 and an output buffer (2) 152.

FIG. 3 shows the segment drivers (IC-U1 to IC-Un, IC-L1 to IC-L) shown in FIG.
n) and each common driver (IC-C1 to IC-
It is a figure which shows the voltage level of the input signal of C5), an internal logic signal, and an output signal.

Each common driver (IC-C1 to IC-C
The intermediate voltage input circuit 120 of 5) has a potential VxH to a potential V.
The potential GND (or the potential Vcc), which is the intermediate voltage of the liquid crystal drive voltage of xL, is used as the reference potential, and the input signal whose voltage level is the potential Vcc to the potential GND is the substrate potential VxL of the semiconductor integrated circuit (for example, -20V). Is used as a reference potential and the voltage level is converted to an internal logic signal having a potential of VxC (for example, −15V) to VxL.

That is, the intermediate voltage input circuit 120 uses the potential GND (or the potential Vcc) different from the substrate potential VxL of the semiconductor integrated circuit forming the common driver as a reference potential, and the input signal whose voltage level is from the potential Vcc to the potential GND. Is converted into an internal logic signal having a voltage level of the potential VxC to the potential VxL with the substrate potential VxL of the semiconductor integrated circuit as a reference potential.

Further, each common driver (IC-C1 to I
The intermediate voltage output circuit 140 of C-C5) outputs the carry output (output signal) to the common driver in the next stage.
An output in which an internal logic signal having a substrate potential VxL of the semiconductor integrated circuit as a reference potential and a voltage level of potential VxC to potential VxL is potential GND (or potential Vcc) as a reference potential and a voltage level of potential Vcc to potential GND. Convert to signal.

Hereinafter, the intermediate voltage input circuit 12 shown in FIG.
A specific circuit configuration of 0 and the intermediate voltage output circuit 140 will be described when the semiconductor integrated circuit forming the common driver is configured by a P-type semiconductor substrate.

FIG. 4 shows the intermediate voltage input circuit 12 shown in FIG.
5 is a circuit diagram showing an example of a specific circuit configuration of 0, and FIG.
FIG. 5 is a diagram showing a timing chart of the circuit shown in FIG. 4.

As shown in FIG. 4, the intermediate voltage input circuit 12
The 0 input buffer 121 is the E / D input buffer 121.
a and an E / D input buffer 121b, each E / D
The D input buffers (121a, 121b) are E / D type inverters having a PMOS circuit configuration including PMOS transistors (Qp1, Qp2 ', Qp3, Qp4).

Each E / D input buffer (121a, 121a
b) is a first series circuit including an enhancement type PMOS transistor (Qp1) and a depletion type PMOS transistor (Qp2 ') between the potential Vcc and the potential GND, an enhancement type PMOS transistor (Qp3) and an enhancement type PMOS transistor (Qp3). And a second series circuit including a PMOS transistor (Qp4).

The source and gate of the PMOS transistor (Qp2 ') of the first series circuit are connected to each other, and
The source of the transistor (Qp2 ′) is connected to the gate of the PMOS transistor (Qp4) of the second series circuit,
Output signals (a signal and b signal) are output from the source of the PMOS transistor (Qp4).

An input signal is applied to the gates of the PMOS transistor (Qp1) and the PMOS transistor (Qp3) of the E / D input buffer (121a), and E
The output signal (a signal) of the E / D input buffer (121a) is applied to the gates of the PMOS transistor (Qp1) and the PMOS transistor (Qp3) of the / D input buffer (121b).

The level shifter (1) 122 of the intermediate voltage input circuit 120 includes enhancement type PMOS transistors (Qp5, Qp6) and enhancement type NMOS.
The level shifter (2) 123 is a CMOS circuit structure inverter composed of transistors (Qn5, Qn6). Similarly, the level shifter (2) 123 is a CMOS circuit structure inverter composed of an enhancement type PMOS transistor (Qp7) and an enhancement type NMOS transistor (Qn7). .

The level shifter (1) 122 has a potential Vcc.
And the substrate potential VxL of the semiconductor integrated circuit, the PMOS
Transistor (Qp5) and NMOS transistor (Qn
5) and a fourth series circuit including a PMOS transistor (Qp6) and an NMOS transistor (Qn6).

The drain of the NMOS transistor (Qn5) of the third series circuit is connected to the gate of the NMOS transistor (Qn6) of the fourth series circuit, and the drain of the NMOS transistor (Qn6) of the fourth series circuit is
It is connected to the gate of the NMOS transistor (Qn5) of the third series circuit.

Further, the a signal output from the E / D input buffer 121a is applied to the gate of the PMOS transistor (Qp5), and the b signal output from the E / D input buffer 121b is applied to the gate of the PMOS transistor (Qp6). An output signal (c signal) is output from the drain of the NMOS transistor (Qn6).

The level shifter (2) 123 has the potential VxC.
And a substrate potential VxL of the semiconductor integrated circuit, a PMOS transistor (Qp7) and an NMOS transistor (Qn7) connected in series are provided.

The output signal of the level shifter (1) 122 is applied to the gate of the PMOS transistor (Qn7) and the gate of the NMOS transistor (Qn7).
An internal logic signal is output from the connection point between the PMOS transistor (Qn7) and the NMOS transistor (Qn7).

In the circuit configuration shown in FIG. 4, the PMOS
Transistor (Qn7) and NMOS transistor (Qn7)
7) The signal output from the connection point with
And the output signal from the inverter 124 is used as an internal logic signal.

As shown in FIG. 5, the input buffer 121
Uses the potential GND (or the potential Vcc) as a reference potential and determines the "High level" and "Low level" of the input signal whose voltage level is from the potential Vcc to the potential GND, and determines the E / D input buffer 121a and the E / D. The input buffer 121b outputs complementary signals a and b.

The a signal and the b signal are input to the level shifter (1) 122, and the level shifter (1) 122
Is an input signal having a potential GND (or a potential Vcc) as a reference potential and a voltage level of potential Vcc to potential GND, a substrate potential VxL of the semiconductor integrated circuit as a reference potential, and a voltage level of potential Vcc to potential VxL. It is converted into a c signal and output.

This c signal is input to the level shifter (2) 123, and the level shifter (3) 123 uses the substrate potential VxL of the semiconductor integrated circuit as a reference potential, and outputs the c signal whose voltage level is from Vcc to VxL. With the substrate potential VxL of the integrated circuit as a reference potential, the voltage level is the potential Vx.
It is converted to an internal logic signal of C to potential VxL and output.

Therefore, the internal logic circuit 130 is
Since the substrate potential VxL of the semiconductor integrated circuit is used as a reference potential and the semiconductor integrated circuit can be operated by an internal logic signal whose voltage level is the potential VxC to the potential VxL, the internal logic circuit 130 can be configured by a standard CMOS circuit, It becomes possible to reduce the power.

Since the level shifter (1) 122 is connected between the potential Vcc and the substrate potential VxL of the semiconductor integrated circuit, the MOS transistor forming the level shifter (1) 122 has a high breakdown voltage MOS structure. Has become.

Further, since the level shifter (2) 123 receives the c signal having the voltage level of the potential Vcc to the potential VxL, it is a MOS which constitutes the level shifter (2) 123.
Only the gate of the transistor has a high withstand voltage MOS structure, for example,
The gate oxide film is thickened.

It is possible to use the input buffer shown in FIG. 6 instead of the E / D input buffers (121a, 121b) shown in FIG.

The input buffer shown in FIG. 6A is an enhancement type PMOS transistor (Qp1) and an enhancement type PMO in which the gate and drain are connected.
The S transistor (Qp2) is connected to the potential Vcc and the potential GN.
It is connected in series with D, and an output signal is output from the connection point.

Further, the input buffer shown in FIG.
Enhancement type PMOS transistor (Qp1)
And a depletion type P in which the gate and source are connected
A MOS transistor (Qp2 ') is connected in series between the potential Vcc and the potential GND, and an output signal is output from the connection point.

The input buffer shown in FIG. 6C is
A first series circuit including an enhancement type PMOS transistor (Qp1) and an enhancement PMOS transistor (Qp2) having a gate and a drain connected between the potential Vcc and the potential GND, and an enhancement type PMOS transistor (Qp3). And an enhancement type PMOS transistor (Qp4)
Of the first series circuit, and the source of the PMOS transistor (Qp2) of the first series circuit is
The input signal is connected to the gate of the transistor (Qp4), the input signal is applied to the gates of the PMOS transistor (Qp1) and the PMOS transistor (Qp3), and the output signal is output from the source of the PMOS transistor (Qp4).

The level shifter (2) 12 shown in FIG.
Instead of 3, the level shifter shown in FIG. 7 can be used.

The level shifter shown in FIG. 7A operates by a complementary input signal (c signal and its inverted signal).
This is a level shifter having a circuit configuration similar to that of the level shifter (1) 122.

Further, the level shifter shown in FIG.
In the level shifter shown in FIG. 7A, the complementary input signal (c signal and its inverted signal) is enhanced by the enhancement type N.
The input is made to a MOS transistor.

FIG. 8 shows the intermediate voltage output circuit 14 shown in FIG.
9 is a circuit diagram showing an example of a specific circuit configuration of 0.
FIG. 9 is a diagram showing a timing chart of the circuit shown in FIG. 8.

As shown in FIG. 8, the level shifter (3) 1
41 is the potential Vcc and the substrate potential VxL of the semiconductor integrated circuit
Between the PMOS transistor (Qp8) and the NMOS
A fifth series circuit including a transistor (Qn8),
It has a sixth series circuit including a PMOS transistor (Qp9) and an NMOS transistor (Qn9).

The drain of the PMOS transistor (Qp8) of the fifth series circuit is connected to the gate of the PMOS transistor (Qp9) of the sixth series circuit, and the drain of the PMOS transistor (Qp9) of the sixth series circuit is 5 is connected to the gate of the PMOS transistor (Qp8) in the series circuit.

The internal logic signal is applied to the gate of the NMOS transistor (Qn8), and the inverted signal of the internal logic signal is applied to the gate of the NMOS transistor (Qn9).
A complementary output signal (d signal and its inverted signal) is output from the connection point with the transistor (Qn8) and the connection point with the PMOS transistor (Qp9) and the NMOS transistor (Qn9).

Since the output signal output from the output buffer 142 has the potential GND (or the potential Vcc) as the reference potential and the voltage level is from the potential Vcc to the potential GND, the output buffer 142 should be formed of a CMOS circuit. I can't.

Therefore, the output buffer 142 includes the enhanced PMOS transistors (Qp10, Qp11).
Comprised of a PMOS transistor (Qp10) and PM
The OS transistor (Qp11) is connected in series between the potential Vcc and the potential GND, and an output signal is output from the connection point between the PMOS transistor (Qp10) and the PMOS transistor (Qp11).

Further, the PMOS transistor (Qp10)
The gate of the level shifter (3) 141 has a PMOS transistor (Qp8) and an NMOS transistor (Qn).
8) The d signal output from the connection point with
The inverted signal of the d signal output from the connection point between the PMOS transistor (Qp9) and the NMOS transistor (Qn9) of the level shifter (1) 122 is applied to the gate of the OS transistor (Qp11).

As shown in FIG. 9, the level shifter (3) 1
Reference numeral 41 designates a substrate potential VxL of the semiconductor integrated circuit as a reference potential, an internal logic signal having a voltage level of the potential VxC to potential VxL, and a substrate potential VxL of the semiconductor integrated circuit as a reference potential, and a voltage level of potential Vcc to potential VxL. The d signal and its inverted signal are output.

The d signal and its inverted signal are applied to the gate of the PMOS transistor (Qp10) and the gate of the PMOS transistor (Qp11) of the output buffer 142, and the PMOS transistor (Qp10) and the PMOS transistor of the output buffer 142 are applied. (Qp11)
Means that only one of them is turned on by the d signal and its inverted signal.

Therefore, the level shifter (3) 141 and the output buffer 142 make the substrate potential V of the semiconductor integrated circuit V.
xL is a reference potential, and the voltage level is from potential VxC to potential V
The internal logic signal of xL is the potential GND (or the potential Vcc) as a reference potential, and the voltage level has an amplitude of Vc.
c to GND output signal.

Here, since the level shifter (3) 141 is connected between the potential Vcc and the substrate potential VxL of the semiconductor integrated circuit, M which constitutes the level shifter (3) 141.
The OS transistor has a high breakdown voltage MOS structure.

The PMOS transistor (Q11) of the output buffer 142 has a threshold (Vt
Since h) becomes high, the potential GND (or the potential Vc
c) is a reference potential, and the voltage level is from potential Vcc to potential G.
Even if a signal of ND is applied to the gate, an output signal having a voltage level of potential Vcc to potential GND cannot be obtained.

Therefore, the substrate potential VxL of the semiconductor integrated circuit output from the level shifter (3) 141 is used as a reference potential, and a signal (d signal and its inverted signal) whose voltage level is Vcc to VxL is output from the output buffer 142. Gate of the PMOS transistor (Qp10) and PM
Input to the gate of the OS transistor (Qp11).

As a result, the potential GND (or the potential V
cc) as a reference potential and the voltage level has an amplitude of Vcc to G
An output signal that is ND can be output.

Further, the PMOS transistor (Qp10) and the PMOS transistor (Q
p11) has a potential Vcc to a potential G between the drain and the source.
ND low voltage, but PMOS transistor (Qp1
0) gate and PMOS transistor (Qp11)
A signal having a voltage level of the potential Vcc to the potential VxL (d signal and its inverted signal) with the substrate potential VxL of the semiconductor integrated circuit as a reference potential is input to the gate of the.

Therefore, the PMOS transistor (Qp1
0) and the PMOS transistor (Qp11) have a high breakdown voltage MOS structure only in the gate, for example, a gate oxide film is thickened.

As a result, the PMO of the output buffer 142 is
A low breakdown voltage MOS structure can be provided between the drain and source of the S transistor (Qp10) and the PMOS transistor (Qp11), and the mutual inductance (gm) can be increased as compared with the case where all of them have a high breakdown voltage MOS structure. it can.

FIG. 10 shows the intermediate voltage output circuit 1 shown in FIG.
It is a circuit diagram which shows the other example of the concrete circuit structure of 40.

In the circuit shown in FIG. 10, an enhancement type PMOS transistor and an enhancement type NMOS transistor are connected between the level shifter (3) 141 and the output buffer 142 shown in FIG. An inverter circuit 143 for waveform shaping including a CMOS inverter connected in series between Vcc and the substrate potential VxL of the semiconductor integrated circuit is added.

In the circuit shown in FIG. 8, the level shifter (3)
Since the operation speed of 141 is slow, the output buffer 14
2 has a drawback that a through-current flows, but the circuit shown in FIG. 10 can suppress the through-current flowing through the output buffer 142.

In the embodiment of the present invention, the semiconductor integrated circuit forming the common driver may be formed of an N type semiconductor substrate.

FIG. 11 shows a standard CMOS circuit and a high withstand voltage CM.
FIG. 12 is a cross-sectional view showing an example in which an OS circuit and an N-type semiconductor substrate are simultaneously configured. As can be understood from FIG. 11, when a semiconductor integrated circuit that constitutes a common driver is configured by an N-type semiconductor substrate, The substrate voltage of the integrated circuit becomes the potential VxH.

FIG. 12 shows the intermediate voltage input circuit 1 shown in FIG.
FIG. 20 is a circuit diagram showing a circuit configuration when 20 is configured by an N-type semiconductor substrate.

When the intermediate voltage input circuit 120 shown in FIG. 4 is composed of an N-type semiconductor substrate, as shown in FIG.
Each of the E / D input buffers (121a, 121b) has an enhancement type NM between the potential Vcc and the potential GND.
OS transistor (Qn1) and depletion type NMO
A first series circuit including an S transistor (Qn2 ') and an enhancement type NMOS transistor (Qn2').
3) and enhancement type NMOS transistor (Qn
4) and the 2nd series circuit which consists of.

The source and gate of the NMOS transistor (Qn2 ') of the first series circuit are connected to each other, and
The source of the transistor (Qn2 ′) is connected to the gate of the NMOS transistor (Qn4) of the second series circuit,
Output signals (a signal and b signal shown in FIG. 4) are output from the source of the NMOS transistor (Qn4).

An input signal is applied to the gates of the NMOS transistor (Qn1) and the NMOS transistor (Qn3) of the E / D input buffer (121a), and E
The output signal (a signal shown in FIG. 4) of the E / D input buffer (121a) is applied to the gates of the NMOS transistor (Qn1) and the NMOS transistor (Qn3) of the / D input buffer (121b).

The level shifter (1) 122 of the intermediate voltage input circuit 120 is a third series circuit including a PMOS transistor (Qp5) and an NMOS transistor (Qn5) between the substrate potential VxH and the potential GND of the semiconductor integrated circuit. And a fourth series circuit including a PMOS transistor (Qp6) and an NMOS transistor (Qn6).

The drain of the PMOS transistor (Qp5) of the third series circuit is connected to the gate of the PMOS transistor (Qp6) of the fourth series circuit, and the drain of the PMOS transistor (Qp6) of the fourth series circuit is
It is connected to the gate of the PMOS transistor (Qp5) of the third series circuit.

Furthermore, the output signal (signal a shown in FIG. 4) output from the E / D input buffer 121a is output to the gate of the NMOS transistor (Qn5) from the E / D input buffer 121b (see FIG. 4). Signal b)
Is applied to the gate of the NMOS transistor (Qn6), and an output signal (c signal shown in FIG. 4) is output from the drain of the NMOS transistor (Qn6).

The level shifter (2) 123 has a PMOS transistor (Qp7) and an NMOS transistor (Qn7) connected in series between the substrate potential VxH and the potential GND of the semiconductor integrated circuit.

The output signal of the level shifter (1) 122 is applied to the gate of the PMOS transistor (Qn7) and the gate of the NMOS transistor (Qn7).
An internal logic signal is output from the connection point between the PMOS transistor (Qn7) and the NMOS transistor (Qn7).

In the intermediate voltage input circuit 120 shown in FIG. 12, the input buffer 121 has the potential GND (or Vc).
c) is a reference potential, and the voltage level is from potential Vcc to potential G.
“High level” and “Lo” of the input signal which is ND
w level ", and the level shifter (1) 122 outputs the input signal whose voltage level is from the potential Vcc to the potential GND,
Input signal "High level" and "Low level"
In response to the substrate potential VxH of the semiconductor integrated circuit as a reference, the level shifter (3) 123 converts the substrate potential VxH into a signal having a voltage level of potential VxH to potential GND and outputs the signal. Then, the voltage level is converted into the internal logic signal having the potential VxH to the potential VxC and output.

Here, since the level shifter (1) 122 is connected between the substrate potential VxH and the potential GND of the semiconductor integrated circuit, M which constitutes the level shifter (1) 122.
The OS transistor has a high breakdown voltage MOS structure.

Further, since the level shifter (2) 123 receives a signal whose voltage level is from the potential VxH to the potential GND with the substrate potential VxH of the semiconductor integrated circuit as a reference, the MOS constituting the level shifter (2) 123 is input. Only the gate of the transistor has a high breakdown voltage MOS structure.

FIG. 13 shows an intermediate voltage output circuit 1 shown in FIG.
FIG. 10 is a circuit diagram showing a circuit configuration when 40 is configured by an N-type semiconductor substrate.

As shown in FIG. 13, the level shifter (3)
141 is the potential GND and the substrate potential Vx of the semiconductor integrated circuit.
Between H and H, PMOS transistor (Qp8) and NMO
It has a fifth series circuit including an S transistor (Qn8) and a sixth series circuit including a PMOS transistor (Qp9) and an NMOS transistor (Qn9).

The drain of the NMOS transistor (Qn8) of the fifth series circuit is connected to the gate of the NMOS transistor (Qn9) of the sixth series circuit, and the drain of the NMOS transistor (Qn9) of the sixth series circuit is the first. 5 is connected to the gate of the NMOS transistor (Qn8) in the series circuit.

The internal logic signal is applied to the gate of the PMOS transistor (Qp8), and the inverted signal of the internal logic signal is applied to the gate of the PMOS transistor (Qp9).
A complementary output signal (d signal shown in FIG. 8 and its inverted signal) is output from the connection point with the transistor (Qn8) and the connection point with the PMOS transistor (Qp9) and the NMOS transistor (Qn9).

In the intermediate voltage output circuit 140 shown in FIG. 13, the substrate potential VxH of the semiconductor integrated circuit is used as the reference potential, the internal logic signal having the voltage level of the potential VxH to the potential VxC is used as the reference potential of the substrate potential VxH of the semiconductor integrated circuit. Then, the voltage level is converted from the potential VxH to the potential GND (and its inverted signal) and output, and the potential GND (or the potential Vcc) is used as the reference potential from the output buffer 142, and the voltage level is from the potential Vcc to the potential. The output signal which is GND is output.

Since the level shifter (3) 141 is connected between the substrate potential VxH and the potential GND of the semiconductor integrated circuit, M which constitutes the level shifter (3) 141 is connected.
The OS transistor has a high breakdown voltage MOS structure.

Further, since the output buffer 142 receives a signal having a substrate potential VxH of the semiconductor integrated circuit as a reference potential and a voltage level of the potential VxH to the potential GND,
Only the gate of the MOS transistor forming the output buffer 142 has a high breakdown voltage MOS structure.

As a result, the low withstand voltage MOS structure can be provided between the drain and source of the NMOS transistor forming the output buffer 142, and the mutual inductance (gm) can be increased as compared with the case where all of them have the high withstand voltage MOS structure. can do.

It should be noted that the voltage values shown in each figure are examples only, and it goes without saying that the present invention can be applied to voltage values other than this voltage value.

Further, in the embodiments of the present invention, the case where the present invention is applied to the STN type simple matrix type liquid crystal display device has been described, but the present invention is not limited to this, and the present invention is of a TFT (Thin Film Transistor) type. It goes without saying that it can be applied to an active matrix type liquid crystal display device.

As described above, the invention made by the present inventor is
Although specifically described based on the embodiments of the present invention, the present invention is not limited to the embodiments of the present invention, and it is needless to say that various modifications can be made without departing from the gist of the present invention. .

[0144]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

(1) According to the present invention, in the liquid crystal display device, a reference potential different from the substrate potential of the semiconductor integrated circuit forming the scanning line driving circuit is input to the scanning line driving circuit without using an external circuit. Since a signal can be input and an output signal having a reference potential different from the substrate potential of the semiconductor integrated circuit included in the scan line driver circuit can be output from the scan line driver circuit, the number of parts can be reduced. Become.

(2) According to the present invention, in the liquid crystal display device, since the internal logic circuit of the scanning line driving circuit can have a CMOS circuit configuration, power consumption can be reduced,
In addition, it becomes possible to improve the operation speed.

(3) According to the present invention, in the liquid crystal display device, the MOS constituting the output buffer of the scanning line drive circuit.
Since it is possible to have a low breakdown voltage MOS structure between the drain and source of the transistor and a high breakdown voltage MOS structure only for its gate, compared to the case where all the MOS transistors forming the output buffer have a high breakdown voltage MOS structure, The inductance (gm) can be increased, which makes it possible to improve the driving capability of the output buffer of the scanning line driving circuit as compared with the conventional one.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of an STN type simple matrix liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of each segment driver and each common driver in the liquid crystal display device according to the embodiment of the present invention.

FIG. 3 is a diagram showing voltage levels of an input signal, an internal logic signal, and an output signal of each segment driver and each common driver shown in FIG.

4 is a circuit diagram showing an example of a specific circuit configuration of the intermediate voltage input circuit 120 shown in FIG. 2 when the semiconductor integrated circuit is configured by a P-type semiconductor substrate.

5 is a diagram showing a timing chart of the circuit shown in FIG.

FIG. 6 is a circuit diagram showing another circuit configuration of the E / D input buffer shown in FIG.

FIG. 7 is a circuit diagram showing another circuit configuration of the level shifter (2) shown in FIG.

8 is a circuit diagram showing an example of a specific circuit configuration of the intermediate voltage output circuit 140 shown in FIG.

9 is a diagram showing a timing chart of the circuit shown in FIG.

10 is a circuit diagram showing another example of a specific circuit configuration of the intermediate voltage output circuit 140 shown in FIG.

FIG. 11 is a cross-sectional view showing an example in which a standard CMOS circuit and a high breakdown voltage CMOS circuit are simultaneously formed on an N-type semiconductor substrate.

12 is a circuit diagram showing a circuit configuration when the intermediate voltage input circuit 120 shown in FIG. 4 is configured by an N-type semiconductor substrate.

13 is a circuit diagram showing a circuit configuration when the intermediate voltage output circuit 140 shown in FIG. 8 is configured by an N-type semiconductor substrate.

FIG. 14 is a block diagram showing a schematic configuration of a conventional STN type simple matrix liquid crystal display device.

15 is a diagram for explaining a data line driving voltage applied to a segment electrode and a scanning line driving voltage applied to a common electrode of the conventional STN type simple matrix liquid crystal display device shown in FIG. is there.

16 is a block diagram showing a schematic configuration of each segment driver shown in FIG. 14 and each common driver.

17 is a diagram showing voltage levels of an input signal, an internal logic signal, and an output signal of each segment driver shown in FIG. 14 and each common driver.

FIG. 18 is a cross-sectional view showing an example in which a standard CMOS circuit and a high breakdown voltage CMOS circuit are configured on the same P-type semiconductor substrate.

FIG. 19 is a cross-sectional view showing an example in which a standard CMOS circuit and a high breakdown voltage CMOS circuit are independently configured on the same P-type semiconductor substrate.

[Explanation of symbols]

101 ... Display control device, 102 ... Power supply circuit, 103 ... Conversion circuit, 111, 121, 121a, 121b, 220
... input buffer, 112, 130, 230 ... internal logic circuit, 113, 142, 152, 240, 252 ... output buffer, 114, 150, 250 ... liquid crystal drive voltage output circuit, 120 ... intermediate voltage input circuit, 122, 123,
141, 151, 251 ... Level shifter, 140 ... Intermediate voltage output circuit, 124, 143 ... Inverter, LCD ...
Liquid crystal display panel, IC-U1 to IC-Un, IC-L1
~ IC-Ln ... Drain driver, IC-C1 ~ IC-
C5 ... Common driver, Qp1 to Qp11 ... PMOS transistor, Qn1 to Qn11 ... NMOS transistor.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Kenichi Akiyama 3300 Hayano, Mobara-shi, Chiba Electronic device division, Hitachi, Ltd. (72) Shinji Yasukawa 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd. ( 72) Inventor Akira Ogura 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd. (72) Inventor Naomi Matsumoto 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd.

Claims (8)

[Claims] 1. A first electrode substrate having a plurality of data lines, and a second electrode substrate having a plurality of scanning lines orthogonal to the data lines.
A liquid crystal panel including an electrode substrate, a liquid crystal sandwiched between the first electrode substrate and the second electrode substrate, and a data line driving circuit that applies a data line driving voltage to the plurality of data lines. A liquid crystal display device comprising: a scanning line driving circuit for applying a scanning line driving voltage to the plurality of scanning lines; and a display control device for controlling the data line driving circuit and the scanning line driving circuit. The circuit is composed of a semiconductor integrated circuit, and the input signal input to the scanning line driving circuit is an input signal whose reference potential is a potential different from the substrate potential of the semiconductor integrated circuit forming the scanning line driving circuit. Characteristic liquid crystal display device. 2. The first scanning circuit driving circuit converts an input signal whose reference potential is different from a substrate potential of the semiconductor integrated circuit into an internal signal whose reference potential is the substrate potential of the semiconductor integrated circuit. The liquid crystal display device according to claim 1, further comprising: 3. The input buffer, wherein the first level shift means is composed of a MOS transistor of a conductivity type different from that of the semiconductor substrate of the semiconductor integrated circuit, a first level shifter having a CMOS circuit configuration, and a CMOS circuit configuration. Second
And a level shifter for determining the High level and the Low level of the input signal by the input buffer,
Based on the determination result of the input buffer, the first level shifter converts the input signal into a first internal signal whose amplitude is larger than that of the input signal, with the substrate potential of the semiconductor integrated circuit being a reference potential. The second level shifter converts the first internal signal into an internal signal having an amplitude the same as (or equivalent to) the amplitude of the input signal, using the substrate potential of the semiconductor integrated circuit as a reference potential. Item 2. The liquid crystal display device according to item 2. 4. A first electrode substrate having a plurality of data lines, and a second electrode substrate having a plurality of scanning lines orthogonal to the data lines.
A liquid crystal panel including an electrode substrate, a liquid crystal sandwiched between the first electrode substrate and the second electrode substrate, and a data line driving circuit that applies a data line driving voltage to the plurality of data lines. A liquid crystal display device comprising: a scanning line driving circuit for applying a scanning line driving voltage to the plurality of scanning lines; and a display control device for controlling the data line driving circuit and the scanning line driving circuit. The circuit is composed of a semiconductor integrated circuit, and the output signal output from the scanning line driving circuit is an output signal whose reference potential is different from the substrate potential of the semiconductor integrated circuit forming the scanning line driving circuit. Characteristic liquid crystal display device. 5. The second scanning circuit driving circuit converts an internal signal having a substrate potential of the semiconductor integrated circuit as a reference potential into an output signal having a potential different from the substrate potential of the semiconductor integrated circuit as a reference potential. The liquid crystal display device according to claim 4, further comprising: 6. The second level shift means is a CMO.
The semiconductor integrated circuit includes a third level shifter having an S circuit configuration, and an output buffer including a MOS transistor of a conductivity type different from that of the semiconductor substrate of the semiconductor integrated circuit. The third level shifter allows the internal signal to be transferred to the semiconductor integrated circuit. The substrate potential of the circuit is used as a reference potential, and the second buffer is converted into a second internal signal whose amplitude is larger than that of the internal signal.
6. The internal signal is converted into an output signal whose amplitude is the same as (or equivalent to) the amplitude of the internal signal, using a potential different from the substrate potential of the semiconductor integrated circuit as a reference potential. Liquid crystal display device. 7. One of the voltages applied to the gate of the MOS transistor forming the output buffer is the substrate potential of the semiconductor integrated circuit, and the voltage applied to the source of the one MOS transistor forming the output buffer. 7. The liquid crystal display device according to claim 6, wherein is a reference potential different from the substrate potential of the semiconductor integrated circuit. 8. The MOS transistor constituting the output buffer is a MOS transistor having a low breakdown voltage MOS structure between a drain and a source and a gate having a high breakdown voltage MOS structure. Liquid crystal display device.