JPH09172576A - Solid-state image pickup element and image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correct a random defect in the solid-state image pickup element. SOLUTION: First to fourth frames are used for a period for correcting a random defect, a picture element output for the 1st frame period is stored in a capacitor 22r of a sample-and-hold circuit 21r, a random defect discrimination selection circuit provides an output of a current value when a difference between the picture element output current value sampled in the capacitor 22 and the picture element output storage value corresponding to the current value is within a prescribed range and the random defect discrimination selection circuit provides an output of a stored value when the difference is at the outside of the prescribed range. A control circuit invalidates the discrimination by the random defect discrimination selection circuit and allows the random defect discrimination selection circuit to provide an output of the stored value in the capacitor 22r and the discrimination by the random defect discrimination selection circuit is validated for the 2nd to the fourth period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device in which random defects in an image are corrected and an image pickup apparatus using the same.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram of a main part of a conventional image pickup apparatus. The subject is imaged on the light-receiving surface of the solid-state image sensor 11 by the taking lens 10, the video signal outputs are sequentially taken out from the solid-state image sensor 11, amplified by the amplifier 12, and then A /
It is digitized by the D converter 13 and stored in the frame memory 14. Addresses on the frame memory 14 corresponding to the defective pixels of the solid-state image sensor 11 are registered in the defective pixel registration ROM 15. The correction circuit 16 outputs the value of the adjacent pixel for the pixel value of this address, and outputs the pixel value stored in the frame memory 14 for the other addresses.

According to this image pickup device, a fixed pixel defect can be corrected by software.

[0004]

However, the above-mentioned image pickup device cannot correct defects that occur randomly. Random defects are caused by, for example, crystal defects in the photodiode portion. This problem becomes significant due to the reduction in pixel size as the number of pixels of the solid-state image sensor increases.

It is possible to detect and correct random defects by providing a plurality of frame memories 14 and comparing the values of corresponding pixels in each frame, but the configuration becomes complicated. In view of such problems, an object of the present invention is to provide a solid-state image sensor in which random defects are corrected and an image pickup apparatus using the same.

[0006]

According to the present invention, a plurality of pixels are arranged and a solid-state image pickup in which the first to nth frame or the first to nth field (n ≧ 3) is set as a cycle of random defect correction. If the difference between the analog storage unit that stores the pixel output in the first frame period or the first field period and the current pixel output value and the corresponding pixel output storage value is within a predetermined range, the element is an element. A random defect determination / selection circuit that outputs a current value and outputs the stored value if the difference is outside a predetermined range, and a storage value of the analog storage means in the first frame period or the first field period. And a control circuit for outputting the output of the random defect determination / selection circuit as a pixel value in the second to nth frame periods or the second to nth field periods.

According to the present invention, in the second to nth frame periods or the second to nth field periods, if the difference between the current pixel output value and the corresponding pixel output memory value is within a predetermined range, the memory value is stored. Since it is output, there is an effect that a random defect is corrected. Further, since the random defect is corrected by the solid-state image sensor itself, it is not necessary to provide a plurality of frame memories outside the solid-state image sensor, or to determine whether or not the random defect is based on the contents,
The use of this solid-state image pickup element has the effect of simplifying the configuration of the image pickup apparatus.

Assuming that there is no random defect in the first frame or the first field, the second to nth frames or the second to nth frames are assumed.
Since random defects of n fields are determined, the first
If there is a random defect in the frame or the first field, it will be erroneously determined.
The probability that there is a random defect in the field is 1 / (n-1) of the probability that there is a random defect in the second to nth frames,
Moreover, since n ≧ 3, according to the present invention, a sufficient effect can be obtained in terms of image quality improvement.

In the first aspect of the present invention, in the pixel, a reverse voltage is applied, a photodiode for accumulating the photo-excited signal charge, and the signal charge is sampled and held in the first capacitor. A first sample-hold circuit that outputs a corresponding signal to the first signal line, and a second sample that samples the signal charge and holds it in a second capacitor and outputs a signal that corresponds to the held charge to the second signal line. A hold circuit, and the analog storage means includes
The first capacitor.

According to the first aspect, since the first sample-hold circuit and the second sample-hold circuit have a symmetrical structure with respect to the photodiode, the random defect can be accurately determined. According to a second aspect of the present invention, the random defect determination / selection circuit, in a valid state, outputs a second signal if the difference between the signal on the first signal line and the signal on the second signal line is within a predetermined range. The signal on the line is selected and output, and if it is outside the predetermined range, the signal on the first signal line is selected and output, and in the invalid state, the signal on the first signal line is selected and output regardless of the difference. In the first frame period or the first field period, the control circuit causes the first sample and hold circuit to sample and hold the signal charge, and disables the random defect determination / selection circuit. In the ~ n frame period or the second to nth field period, the second sample and hold circuit is made to sample and hold the signal charge, and the random defect judgment / selection circuit is made effective.

According to the second aspect, in any of the 1st to nth frame periods or the 1st to nth field periods,
Since the pixel value is output from the random defect determination / selection circuit, the pixel value output characteristics are the same in each period, and the image quality is improved. According to a third aspect of the present invention, there is provided a transistor switch connected between an output terminal of the random defect judgment / selection circuit and a video output line, and a horizontal shift register for selecting the transistor switch in a dot-sequential manner.

According to a fourth aspect of the present invention, the pixels are arranged two-dimensionally, the first signal line and the second signal line are common to the same pixel column, and the first sample and hold circuit is used. A first transistor switch connected between the output end of the second signal line and the first signal line, and a second transistor switch connected between the output end of the second sample and hold circuit and the second signal line, A vertical shift register that selects the first transistor switches line-sequentially in the first slam period and selects the second transistor switches line-sequentially in each period of the second to nth frames.

In a fifth aspect of the present invention, each of the first sample-hold circuit and the second sample-hold circuit includes a capacitor, and a sampling transistor switch for discharging the electric charge of the capacitor to the photodiode when turned on. A reset transistor switch that charges the capacitor when turned on, and a source follower circuit that outputs a voltage according to the voltage of the capacitor,
And the capacitor is the gate capacitance of the source follower circuit.

According to the fifth aspect, the pixel configuration is relatively simple, and the pixel density can be improved. In a sixth aspect of the present invention, the random defect judgment / selection circuit judges whether or not the difference between the signal on the first signal line and the signal on the second signal line is within a predetermined range, and is a binary signal. And a gate circuit for invalidating the output of the random defect determination circuit when the enable signal is active and validating the output of the random defect determination circuit when the enable signal is inactive. And a selector switch that selects and outputs one of the signal on the first signal line and the signal on the second signal line in accordance with the output of the gate circuit.

In a seventh aspect of the present invention, any one of the solid-state image pickup devices described above, a photographing lens for forming an image of a subject on a light-receiving surface of the solid-state image pickup device, and an output signal of the solid-state image pickup device are processed and displayed. A signal processing circuit for generating a device video signal.

According to the seventh aspect, since the solid-state image pickup device is used, the structure of the image pickup device can be simplified.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a solid-state image sensor. For simplification of description, the pixel array is 2 rows and 2 columns in FIG. Pixel Pij (i = 1, 2, j
= 1, 2) is shown in FIG.

In the pixel Pij, the left and right of the photodiode 20 have a symmetrical structure, and the constituent elements on the left side of the photodiode 20 are denoted by r in the reference numerals of the corresponding constituent elements on the right side of the photodiode 20. The photodiode 20 is
The anode is connected to the ground line, and the cathode is connected to the input terminals of the sample hold circuit 21 and the sample hold circuit 21r.

The sample-hold circuit 21 is connected between one end of the hold capacitor 22, the input end and the output end of the sample-hold circuit 21, and the power supply potential Vdd, respectively.
The S transistor switch 23, the buffer amplifier 24, and the MOS transistor switch 25 are connected. A MOS transistor switch 26 is connected between the output end of the sample hold circuit 21 and the vertical signal line Bj, and the output end of the sample hold circuit 21r and the vertical signal line Brj are connected.
26r is connected between and.

A sampling signal S, a reset signal RS, and a row selection signal Vi are supplied to the gates of the MOS transistor switches 23, 25, and 26, respectively.
The gates of the transistor switches 23r, 25r and 26r have sampling signals Sr and reset signals R respectively.
Sr and the row selection signal Vri are supplied. Turn on the MOS transistor switch 25 and hold capacitor 2
By charging 2 with a power supply potential Vdd, for example, 5V,
The hold capacitor 22 is reset. When the MOS transistor switch 23 is turned on, the signal charge (electrons) accumulated in the cathode of the photodiode 20 by photoexcitation moves to the hold capacitor 22 through this and discharges the hold capacitor 22. As a result, the photodiode 20 is reset. The voltage corresponding to the amount of charge held by the hold capacitor 22 is the buffer amplifier 2
It is output from 4. When the MOS transistor switch 26 is turned on, the output of the buffer amplifier 24 is taken out onto the vertical signal line Bj, and the vertical signal line Bj has a potential (pixel value).
It becomes Vij.

To increase the pixel density, the pixel Pij
It is necessary to simplify the configuration of. FIG. 3A shows a configuration example of the hold capacitor 22, the buffer amplifier 24, and the MOS transistor switch 26 for this purpose. This circuit is a source follower circuit with a switch in which MOS transistors 241, 26, and 242 are connected in series. The MOS transistor 241 and the MOS transistor 2 are connected to each other.
The buffer amplifier 24 shown in FIG.
The hold capacitor 22 in FIG. 2 is the gate capacitance of the MOS transistor 241. The MOS transistor 242 functions as a current source, and its gate has a constant potential V
bb is applied. When the MOS transistor switch 26 is on, the potential Vij corresponding to the input potential vij is taken out.

With such a structure, the pixel Pi shown in FIG.
The configuration of j becomes relatively simple. FIG.
This is a modified example corresponding to (A), and the MOS transistor 2
The gate capacitance of 41 and the capacitor 22a connected to the gate of the MOS transistor 241 constitute the hold capacitor 22 of FIG. In FIG. 1, reset signals RS and RSr and sampling signals S and Sr are commonly supplied from the control circuit 30 to all the pixels P11 to P22.

Row selection lines Vr1 and Vr2 are connected to the parallel output terminals of the vertical shift register 31, and column selection lines H1 and H2 are connected to the parallel output terminals of the horizontal shift register 32. The row selection lines Vr1 and Vr2 are also connected to one input ends of the AND gates 331 and 332, respectively, and the enable signal EN is supplied from the control circuit 30 to the other input ends of the AND gates 331 and 332. Row select lines V1 and V2 are connected to the output terminals of the AND gates 331 and 332. The control circuit 30
A vertical start pulse and a horizontal start pulse are supplied to the serial data input terminals of the vertical shift register 31 and the horizontal shift register 32, respectively, and a vertical shift pulse and a horizontal shift pulse are supplied to the clock input terminals of the vertical shift register 31 and the horizontal shift register 32, respectively. Supply.

As a result, the row selection line Vr1 is selected,
When the enable signal EN is at high level, the row selection line V1
The column select lines H1 and H2 are sequentially selected in this state, the row select line Vr2 is then selected, and the row select line V2 is also selected when the enable signal EN is at a high level.
In this state, the column selection lines H1 and H2 are sequentially selected. The vertical signal lines Br1 and B1 are connected to the input terminals of the random defect determination / selection circuit 341, and the vertical signal lines Br2 and B2 are connected.
Is connected to the input terminal of the random defect judgment / selection circuit 342.

Random defect judgment / selection circuit 34j (j =
An example of the configuration of (1) and (2) is shown in FIG. The random defect determination / selection circuit 34j includes a random defect determination circuit 40,
A switching circuit 41 and an AND gate 42 are provided. The random defect determination circuit 40 determines that the defect is not a random defect if | Vij-Vrij | <ΔV (1), and outputs a high level, and otherwise outputs a low level. ΔV here
Is a criterion value. The output of the random defect determination circuit 40 and the enable signal EN are supplied to the AND gate 42, and the output of the AND gate 42 selectively controls the switching circuit 41. The switching circuit 41 selects and outputs the potential Vrij on the vertical signal line Bri when the output of the AND gate 42 is at a low level, and selects and outputs the potential Vij on the vertical signal line Bij otherwise.

In FIG. 1, the outputs of the random defect judgment / selection circuits 341 and 342 are connected to the video output line B0 via MOS transistor switches 351 and 352, respectively. Column select lines H1 and H2 are connected to the gates of the MOS transistor switches 351 and 352, respectively. Next, the operation of the present embodiment configured as described above will be described based on the timing chart of FIG.

In the present embodiment, the first to fourth frames are one cycle of the random defect correction, and this one cycle is, for example, the first cycle for improving the SN ratio in the portion which processes the output of the solid-state image sensor. It is also a frame addition cycle for adding corresponding pixel values of 4 frames. First, all pixels P11
The hold capacitors 22 and 22r of P22 are set to the voltage V
It is reset by dd, and the MOS transistor switches 23, 25, 26, 23r, 25r and 26 are turned off.

(1) First frame All the pixels P11 to P11 by the pulse of the sampling signal Sr.
The signal charge (electrons) accumulated in the photodiode 20 is transferred to the MOS transistor switch 23 r
And is supplied to the hold capacitor 22r to discharge the hold capacitor 22r, whereby the photodiode 20 is reset.

Next, the row selection line Vr1 goes high and the pixels P11 and P12 of the first row 26r are turned on.
The vertical signal line Brj (j = 1, 2) becomes the potential Vr1j corresponding to the potential vr1j of the hold capacitor 22r. Since the enable signal EN is at a low level, the random defect determination / selection circuits 341 and 342 are in an invalid state, and the potential Vr1 on the vertical signal lines Br1 and Br2 is in the state.
1 and Vr12 are selected by the random defect determination / selection circuits 341 and 342, respectively.

Next, MO is applied by a pulse on the column selection line H1.
The S transistor switch 351 is turned on and the potential Vr
11 is taken out as a video signal Vout on the video output line B0, then the MOS transistor switch 352 is turned on by a pulse on the column selection line H2, and the potential Vr12 is taken out as a video signal Vout on the video output line B0.

Next, the row selection line Vr2 becomes high level, the MOS transistor switch 26r of the pixels P21 and P22 of the second row is turned on, and the vertical signal line Brj (j =
1, 2) becomes the potential Vr2j corresponding to the potential vr2j of the hold capacitor 22r. Since the enable signal EN is at the low level, the random defect determination / selection circuit 341
And 342 are in an invalid state, and the vertical signal line Br1
And potentials Vr21 and Vr22 on Br2 are selected by random defect determination / selection circuits 341 and 342, respectively.

Next, MO is applied by a pulse on the column selection line H1.
The S transistor switch 351 is turned on and the potential Vr
21 is taken out as a video signal Vout on the video output line B0, then the MOS transistor switch 352 is turned on by a pulse on the column selection line H2 and the potential Vr22 is taken out as a video signal Vout on the video output line B0.

The pulse of the reset signal RS turns on the MOS transistor switches 25 of all the pixels P11 to P22 to reset the hold capacitors 22. (2) Second frame All pixels P11 to P2 by the pulse of the sampling signal S
For each of the two, the signal charge (electrons) accumulated in the photodiode 20 is supplied to the hold capacitor 22 through the MOS transistor switch 23, and the hold capacitor 22 is discharged, whereby the photodiode 20 is reset.

The enable signal EN goes high. Next, the row selection lines Vr1 and V1 become high level, the MOS transistor switches 26r and 26 of the pixels P11 and P12 in the first row are turned on, and the vertical signal line Brj (j =
1, 2) becomes the potential Vr1j corresponding to the potential vr1j of the hold capacitor 22r, and the vertical signal line Bj (j =
1, 2) becomes the potential V1j corresponding to the potential v1j of the hold capacitor 22. Since the enable signal EN is at a high level, the random defect determination / selection circuits 341 and 3 are
42 is in the valid state, the potential V1j on the vertical signal line Bj is selected if the random defect determination / selection circuit 34j determines that there is no random defect, and the vertical signal line if it is determined that there is a random defect. Potential Vr1 on Brj
j is selected.

Next, the pulse on the column select line H1 causes the MO.
The S transistor switch 351 is turned on and the potential V1
1 or Vr11 is taken out as a video signal Vout on the video output line B0, and then M is generated by a pulse on the column selection line H2.
When the OS transistor switch 352 is turned on, the potential V
12 or Vr12 is a video signal Vout on the video output line B0.
Is taken out as

Next, the row selection lines Vr2 and V2 are set to the high level, the MOS transistor switches 26r and 26 of the pixels P21 and P22 of the second row are turned on, and the vertical signal line Brj (j = 1, 2) is turned on. The potential Vr2j corresponds to the potential vr2j of the hold capacitor 22r, and the vertical signal line Bj (j = 1, 2) becomes the potential V2j corresponding to the potential v2j of the hold capacitor 22. Enable signal E
Since N is at a high level, the random defect determination / selection circuits 341 and 342 are in an effective state, and if the random defect determination / selection circuit 34j determines that there is no random defect, the potential V2j on the vertical signal line Bj. Is selected,
If it is determined that there is a random defect, the potential Vr1j on the vertical signal line Brj is selected.

Next, the pulse on the column selection line H1 causes the MO.
The S transistor switch 351 is turned on and the potential Vr
21 or Vr21 is a video signal Vout on the video output line B0.
Then, the MOS transistor switch 352 is turned on by the pulse on the column selection line H2 and the potential Vr22 or V22 is output to the video signal Vou on the video output line B0.
taken out as t.

The pulse of the reset signal RS turns on the MOS transistor switches 25 of all the pixels P11 to P22 to reset the hold capacitor 22 to the voltage Vdd. (3) Third and Fourth Frames In both the third and fourth frames, the same processing as the above processing in the second frame is performed.

In the conventional solid-state image pickup device, when the pixel value V12 of the third frame is a random defect like the video signal Vout of FIG. 4 (M), the pixel value V12 is output as it is. On the other hand, according to the present embodiment, since the pixel value V12 of the third frame does not satisfy the above expression (1), the random defect determination / selection circuit 342 determines that it is a random defect, and the pixel value Vr12 is selected. In this way, the video signal Vout in which the random defect as shown in FIG. 4L is corrected is taken out from the solid-state image sensor.

Further, since the random defect is corrected by the solid-state image pickup device itself, it is not necessary to provide four frame memories outside the solid-state image pickup device or to judge whether the random defect is based on the contents. By using this solid-state image pickup device, the structure of the image pickup apparatus becomes simple. Since the random defects of the 2nd to 4th frames are determined on the assumption that the first frame has no random defect, an erroneous determination is made when the first frame has a random defect. The probability of random defects in the frame is 2-4
Since the probability that a frame has a random defect is 1/3, the random defect in the conventional solid-state imaging device can be reduced to 1/3. Since the number of pixels is large and all random defects are not recognized by the human eye, according to this embodiment, a sufficient effect can be obtained in terms of image quality improvement.

The present invention also includes various modifications. For example, although the case where the solid-state image sensor is a two-dimensional image sensor has been described in the above embodiment, the present invention is
It is also applicable to a three-dimensional image sensor. In this case, the MOS transistor switches 26 and 26r of FIG. 2 are unnecessary. The pixel value transfer may be transfer by another method such as CCD.

The present invention is not limited to the processing for the output of the solid-state image sensor such as the frame addition processing. For example, the present invention may be applied to an image pickup apparatus that does not perform frame addition for picking up an image of a fast-moving subject, and whether or not to correct a random defect may be selected as a mode.
In the non-correction mode, the value of ΔV in the above equation (1) may simply be increased. The value of ΔV may be arbitrarily set from the outside.

Of course, the frame may be a field.

[Brief description of the drawings]

FIG. 1 is a block diagram of a solid-state image sensor according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a pixel in FIG.

3 is a diagram showing a configuration example of a main part of the circuit of FIG. 2 and a random defect determination / selection circuit of FIG.

FIG. 4 is a timing chart showing the operation of the solid-state image sensor of FIG.

FIG. 5 is a block diagram of a main part of a conventional imaging device.

[Explanation of symbols]

P11 to P22, Pij Pixel 20 Photodiode 21, 21r Sample and hold circuit 22, 22r Hold capacitor 23, 25, 26, 351, 352 MOS transistor switch 24 Buffer amplifier 30 Control circuit 31 Vertical shift register 32 Horizontal shift register 341, 342 Random defect Judgment / selection circuit 40 Random defect judgment circuit 41 Switching circuit

Claims (8)

[Claims] 1. A solid-state image sensor having a plurality of pixels arrayed therein, the first to nth frames or the first to nth fields (n ≧ 3) being a cycle of random defect correction, the first frame period or the first frame period. If the difference between the analog storage means that stores the pixel output in the field period and the current pixel output value and the corresponding pixel output storage value is within a predetermined range, the current value is output, and the difference is outside the predetermined range. If so, the random defect determination that outputs the stored value
In the selection circuit and in the first frame period or the first field period, the storage value of the analog storage means is output as a pixel value,
A control circuit that outputs the output of the random defect determination / selection circuit as a pixel value in the n-frame period or the second to n-th field periods. 2. The pixel includes a photodiode to which a reverse voltage is applied and accumulates photo-excited signal charge, and the signal charge is sampled and held in a first capacitor, and a signal corresponding to the held charge is first A first sample-and-hold circuit for outputting on the signal line; and a second sample-and-hold circuit for sampling the signal charge and holding it in the second capacitor and outputting a signal according to the held charge on the second signal line. The solid-state imaging device according to claim 1, wherein the analog storage means is the first capacitor. 3. The random defect determination / selection circuit, when in a valid state, has a signal on the second signal line if the difference between the signal on the first signal line and the signal on the second signal line is within a predetermined range. And outputs the signal on the first signal line if it is outside the predetermined range, and in the invalid state, selects and outputs the signal on the first signal line regardless of the difference. In the first frame period or the first field period, the control circuit causes the first sample and hold circuit to sample and hold the signal charge, disable the random defect determination / selection circuit, and set the second to nth frames. In the period or the second to n-th field periods, the second sample-and-hold circuit is made to sample and hold the signal charge, and the random defect judgment / selection circuit is made effective. The solid-state imaging device. 4. A transistor switch connected between an output end of the random defect judgment / selection circuit and a video output line, and a horizontal shift register for selecting the transistor switch in a dot-sequential manner. The solid-state image sensor according to claim 3. 5. The pixels are arranged two-dimensionally, and the first signal line and the second signal line are common to the same pixel column, and the output end of the first sample hold circuit and the A first transistor switch connected to the first signal line, a second transistor switch connected to the output terminal of the second sample-hold circuit and the second signal line, and in the first slam period. 5. A vertical shift register that selects the first transistor switch line-sequentially and selects the second transistor switch line-sequentially in each period of the second to n-th frames. Solid-state image sensor. 6. The first sample-hold circuit and the second sample-hold circuit each include a capacitor, a sampling transistor switch for discharging the electric charge of the capacitor to the photodiode when the capacitor is on, and a sampling transistor switch when the capacitor is on. 6. A reset transistor switch for charging a capacitor, and a source follower circuit for outputting a voltage according to the voltage of the capacitor, the capacitor being a gate capacitance of the source follower circuit. One of
The solid-state image sensor according to item 1. 7. The random defect judging / selecting circuit judges whether a difference between a signal on the first signal line and a signal on the second signal line is within a predetermined range and outputs a binary signal. A random defect judgment circuit; a gate circuit that invalidates the output of the random defect judgment circuit when the enable signal is active; and a gate circuit that enables the output of the random defect judgment circuit when the enable signal is inactive. 7. A changeover switch for selecting and outputting one of a signal on the first signal line and a signal on the second signal line in accordance with an output of the gate circuit, and a selector switch according to any one of claims 3 to 6. Or 1
The solid-state image sensor according to item 1. 8. The solid-state image sensor according to claim 1, a photographing lens for forming an image of a subject on a light-receiving surface of the solid-state image sensor, and an output signal of the solid-state image sensor. And a signal processing circuit for generating a video signal for a display device.