JPH09172099A - Single-layer poly-crystalline silicon split gate eeprom cellwith embedded control gate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electrically erasable/writable read-only memory (EEPROM) cell. SOLUTION: An electrically erasable/writable read-only memory cell has a split gate transistor 34 for read use and an N-type buried plate control gate 32. The split gate transistor 34 has drain and source regions 42 and 40 and a channel region 44 between both regions 42 and 40. A silicon dioxide layer covers the drain, channel and source regions 42, 44 and 40. The silicon dioxide layer, which is formed on one part of the channel region 44 and the drain region 42, is formed thicker than that of a silicon dioxide layer 62, which lies on the remaining channel region and the source region. A polycrystalline silicon single layer 36 is provided on the channel region 44. N-type buried plates are provided at intervals from the source, drain and channel regions to the lateral direction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit memory device (memory element), and more particularly to an electrically erasable and writable read-only device having a single-layer polycrystalline silicon split gate having a buried plate type control gate. It relates to a memory (EEPROM) cell.

[0002]

BACKGROUND OF THE INVENTION Very Large Scale Integrated Circuit (VLSI) structures, especially non-volatile memory devices (ie, memory devices of the type that retain stored data even after power to the device is turned off). In, device installation area (area) and memory / search (read)
It is the greatest goal and a challenge to make the operation speed more efficient and to further improve the efficiency and simplification of the device configuration and manufacturing (which is directly related to the cost).

In particular, a conventional EEPROM device has a plurality of memory cells, and each of these memory cells has a storage transistor with a so-called floating gate. One of the characteristics of such a memory transistor is that the information written therein can be maintained even when the power to the EEPROM device is cut off, and moreover, it can be stored in the memory transistor. You can also erase the data. More specifically, regarding the basic operation (operation) of a conventional so-called flash EEPROM memory cell, channel hot electron injection is performed for programming, and Fowler-Nordhiem tunneling (tunnel phenomenon) is performed for erasing data. Is known to be used. Flash EEPROM having an array of cells
In a semiconductor device, each cell is independently programmable and independently readable. However,
As a result of trying to reduce the size of each cell (which can increase the storage capacity per device), the select transistor (which each cell could be independently erased) is often omitted. Was done. Therefore, all cells were erased simultaneously as one block.

The problem resulting from the above arrangement is known to those skilled in the art as "over-erasure". Specifically, during erase, some of the cells in the block being erased are overerased before other cells are fully erased. The floating gate of an "over-erased" cell is therefore deprived of electrons (depleted) and the net charge is positive. Due to this positive net charge, the "over-erased" cell functions as a depletion type transistor, that is, a transistor that cannot be turned off even when a normal operating voltage (operating voltage) is applied. Under this condition, a leakage current is generated in the next read operation, and this leakage current may adversely affect the performance and integrity of the memory device.

As a means for solving the above-mentioned "over-erase" problem of the conventional EEPROM device, a split gate structure is provided. A conventional split gate structure is formed using at least two layers of polycrystalline silicon and has one floating gate transistor. The first layer of polycrystalline silicon forms the floating gate. However, this floating gate covers only a portion of the channel area between the source and drain. The rest of the channel area is directly controlled by the second layer of polycrystalline silicon (control gate). This control gate is also provided on the floating gate. Therefore, the conventional split gate memory cell has the same structure as the insulating transistor and the floating gate transistor connected in series. The isolation transistor is not affected by the state of the floating gate, and when its control gate (of the isolation transistor) is not activated (that is, when the memory cell is not selected), the floating gate transistor is "excessive". Erased,
Therefore, it remains off even when in the conducting state.
Therefore, despite the "over-erase" problem described above, memory device consistency is maintained. But “over-erasure”
This solution to the above problem requires two layers of polycrystalline silicon, thus complicating the construction and increasing manufacturing costs.

Another solution attempted by other persons skilled in the art is to use one isolation or access transistor in the read path in isolation to generate leakage current during a read operation for an unselected cell. Is to prevent. This approach is shown in FIG. 1, where reference numeral 10 is a conventional EEPROM memory cell. The memory cell 10 includes a high voltage calling transistor 12, a tunnel (silicon) oxide layer 14, a floating gate 16, and a buried control gate 18.
And a low voltage calling transistor 20 and a floating gate transistor 22 sharing the floating gate 16. Those skilled in the art will understand the operation of cell 10 by referring to the table below.

[0007]

[Table 1]

It should be noted that the technique represented by cell 10 has a single layer polycrystalline silicon construction, with only floating gate 16 made of polycrystalline silicon material. In this memory cell, one isolation transistor (isolation transistor) 20 is separately provided in the read passage. Further, the cell 10 is provided with a transistor 12 to isolate the tunnel oxide layer 14 / floating gate 16 from the high voltage of the high voltage bit line (HV BL) when the cell 10 is not selected. Transistor 12 has HV
In order to withstand the conventional high voltage of BL (for example, 15 V), the source and drain are connected and joined (junction) in a special configuration (for example, the diffusion pitch width is much larger). As a result, valuable (if not otherwise) space within the cell is occupied by the special configuration described above. In summary, the 4.5 transistor configuration shown in FIG. 1 is rather complex, thus resulting in lower memory cell density and increased cost, resulting in a less competitive product.

Accordingly, at least one of the above problems can be mitigated or eliminated, and therefore flash EEPROMs.
There is a need to provide improved memory configurations suitable for use in memory devices such as devices.

[0010]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an EEPROM device which addresses the above-mentioned "overerase" problem, while avoiding the high cost and complex construction associated with conventional approaches to this problem. That is.

The memory cell according to the present invention not only achieves the above objects, but also provides a smaller cell than the conventional cell configuration. These improvements are achieved by a single layer polycrystalline silicon floating gate structure with a buried plate control gate. The embedded control gate is responsive to an externally applied potential to control the programming and reading operations of the cell. The split gate transistor has a floating gate portion that is operable to connect to a buried control gate. Combining and joining the split-gate transistor and the buried control gate overcomes the complex structure of the prior art and provides functionality that meets the standards required in the general market.

In a preferred embodiment, the device according to the invention comprises a semiconductor substrate of the first conductivity type, preferably P-type silicon. Source and drain regions of a second conductivity type (preferably n-type silicon) opposite the first conductivity type are formed in the substrate. The source and drain regions are spaced apart from each other so that a channel region is formed therebetween. The channel area includes a first sub-area, the first sub-area extending from the drain area to the source area and for selection (or isolation)
Form part of the gate. The channel further includes a second sub-region extending between the first sub-region and the source, the second sub-region forming part of the read transistor. A buried control gate region (preferably n-type silicon) is formed in the substrate, the buried control gate region being spaced from the source region, the drain region and the channel. A single layer of dielectric material (preferably silicon oxide) is formed over the substrate. This layer has a dielectric tunnel area, which extends over the second partial area of the channel (described above) and at least a portion of the source. The silicon oxide layer in the dielectric tunnel area portion is thinner than the silicon oxide layer overlying the rest of the channel and drain area.

A floating gate (preferably polycrystalline silicon) is located over the layer of silicon oxide described above. The floating gate includes a first portion extending above the channel and a second portion extending above the buried control gate. A select transistor is formed in the first subregion of the channel to prevent the "over-erase" of the floating gate that has already occurred, causing an undesired turn-on condition when the memory cell is not selected. (That is, the insulating function is exerted when the memory cell is not selected). A read transistor is formed in the second subregion of the channel, the read transistor determining the state of the memory when the memory cell is selected. The select transistor has a threshold voltage (Vt), which is higher than the voltage of the read transistor, because the silicon oxide layer at the gate of the select transistor is the same as that of the read transistor. This is because it is thicker than that. this,
Selection (or isolation) due to higher threshold voltage (Vt)
Function is brought. Programming occurs in the drain region by channel hot electron injection, while erasing (ie, removing electrons from the floating gate) occurs near the source region of the split-gate transistor due to the well-known Fowler-Nordhiem tunneling phenomenon. Generated through (a layer of) thin silicon oxide.

Other objects, features and advantages of the present invention include:
The following detailed description and accompanying drawings (features of the present invention are shown by way of specific examples and do not pose any limitation)
Will be apparent to those skilled in the art.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the accompanying drawings. In the accompanying drawings, the same (similar) reference numerals are given to the same parts / elements in different drawings. I am doing it. FIG. 2 illustrates a preferred memory cell 30 embodiment according to the present invention. The memory cell 30 is composed of a buried control gate 32 and a split gate transistor 34 having a floating gate portion 36. The control gate 32 controls the reading (reading operation) and programming of the memory cell 30 according to the voltage (potential) supplied from the outside. The floating gate 36 can be connected / connected to the control gate 32 and constitutes a part of the split gate transistor 34. The floating gate 36 has a first portion 36a and a second portion 36b (FIG. 3).

The following abbreviations are used in FIG.

HV BL is a high voltage
Abbreviation for Bit Line (high voltage bit line).

CG is an abbreviation for control gate.

Vsource is a symbol indicating the voltage of the power supply terminal (source side terminal) of the split gate transistor 34.

The memory cell 30, as in many other cases, is suitable for storing and storing binary data, which can take two states, and EEPRO.
It is suitable for use in an M cell structure. Therefore, in the structure shown in FIG. 2, it can be considered that the memory cell 30 constitutes a part of a large memory cell array (an array formed by a matrix of a plurality of memory cells 30). Each cell has a control gate connected to one common word line WL, and the memory cells 3 in the same column (each column) are connected to one row bit line (column bit line). Each has a connected high voltage bit line (HV BL). The usage of such a memory cell 30 is merely an example. That is, the memory cell 30 can be used in other methods, methods, and cases (for example, it can also be used in a programmable logic device (PLD)).

The invention will be better understood by reference to the detailed construction of the apparatus according to the preferred embodiment. Therefore, next, reference will be made to FIGS. 3 to 6.

FIG. 3 is a plan layout view of a memory cell according to the preferred embodiment (the outline of which is shown in FIG. 2). FIG. 3 is a diagram attached to enable those skilled in the art to manufacture and use the device according to the present invention. Also,
FIG. 3 is a diagram attached as a guide diagram (explanatory diagram) for clarifying the relationship between FIGS. 4 and 5 described later. For reasons that will become apparent below, the area of the memory cell 30 is considerably smaller than that of the conventional one. The area occupied by the memory cell 30 shown in FIG. 3 is 5.25 × 5.6 μm, or about 29 square microns (using the 0.65 μm design ruler). If the memory cell 30 is made with a smaller design ruler, the area can be even smaller (eg, using a 0.5 μm ruler to be 18 square microns). A conventional design / structure to be compared with this (equivalent in function / function) (for example,
In the design / structure of the memory cell 10 shown in FIG. 1, the area is 110 square microns to 220 square microns or more. Such a significant reduction in area is very important for a variety of reasons that will be appreciated by those skilled in the art (eg, higher density per unit price, better performance, etc.). Reason).

The memory cell 30 includes a semiconductor substrate 38 of a first conductivity type, a source region 40 having a second conductivity type opposite to the first conductivity type and formed in the substrate 38, and a second conductivity type. And a drain region 42 formed on the substrate 38 having a proper shape. Here, the source region 40 and the drain region 42 are separated from each other, and a channel region 44 is formed therebetween.

FIG. 4 is a cross-sectional view taken along a plane perpendicular to the floating gate portion 36, and also shown in FIG.
4 is a cross-sectional view taken along line 4 and FIG.
It is the figure seen from the direction of arrow 4. FIG. 4 shows a general and schematic structure of the split gate transistor portion 34 of the memory cell 30. Substrate 38 is preferably P-type silicon. A conventional field oxide region (not shown) is provided to separate the split gate transistor (34) from another split gate transistor (34) of another memory cell (30) on the same substrate (38). Separated. Further, the oxide region (oxide region) is made of, for example, a silicon dioxide (silicon dioxide) material having a thickness of about 5000 angstroms.

As best shown in FIG. 4, the source region 40 comprises a heavily and heavily doped N + ohmic contact region 46 and a slightly lower, slightly lightly doped N region. And a mold area 48. N
The mold area 48 is generally the contact area 46 to the drain area 4
It extends toward 2. Similarly, the drain area 42
It has a heavily doped N + ohmic contact region 50 and a slightly lower, lightly doped N-type region 52. The N-type region 52 generally extends from the contact region 50 toward the power source region 40. Area 46/48 above
And 50/52 are provided for improving / improving the punch-through characteristics and punch-through characteristics of the apparatus. That is, when the drain / source has a sufficiently high voltage with respect to the source / drain, the depletion region extends beyond (crosses) the channel, resulting in current flow regardless of gate voltage. (That is, even if the gate voltage is zero). This state is known as a punch through state (a punch through phenomenon). The N + / N structure is provided to reduce the electric field / electric field in the drain and source depletion regions. The ohmic N + contact areas 46 and 50 consist of the doping areas in the substrate 38, with an average concentration of 10 ¹⁵ -10 ¹⁶ atoms of arsenic per square centimeter (preferably 10 per square centimeter).
Arsenic with an average concentration of ¹⁶ atoms). Similarly, N type region 48
And 52 are doped with an average concentration of 10 ¹⁴ -10 ¹⁵ atoms per square centimeter (preferably an average concentration of about 10 ¹⁵ atoms per square centimeter). still,
Those of ordinary skill in the art will appreciate other N-specie impurities.
It will be appreciated that a) may be used to form both the source area 40 and the drain area 42. Also, the doping may likewise be somewhat different and variations to that extent are within the scope of the invention.

The channel 44 is basically divided into two areas. The first area 54 is select
The second area 56 is for forming a floating gate or a read (read) transistor.

A layer 58 of dielectric material (eg, oxide of silicon) is formed on the substrate 38. This layer 58 comprises a thick oxide area 60 formed on the first area 54 of the channel 44, a second area 56 and at least the source area 4.
Thin tunnel oxide (dielectric) areas 62 extending over a portion of the zeros. Preferably, the thick oxide region 60 is a silicon dioxide material having a thickness of about 145-300 angstroms (particularly preferably the thickness is 190 angstroms). Also, the thin oxide area 62 is preferably a silicon dioxide material having a thickness of about 70-100 angstroms (particularly preferably the thickness is 80 angstroms).

Floating gate 36 preferably comprises a polycrystalline silicon material (poly). Floating gate 36 has a thickness of 1.0-2.0 kiloangstroms (2 kiloangstroms in the preferred embodiment). The floating gate 36 is preferably N +
To have a sheet resistance of about 80-150 ohms per square (Ω / □). Selection of an appropriate dopant and determination of its amount and magnitude to obtain the above resistance value does not require more than the thought and effort normally performed by those skilled in the field of semiconductor manufacturing. The first portion 36a is
Extends substantially over the channel 44, while the second portion 36
b extends substantially over the buried control gate 32 (FIG. 5).

Referring now to FIG. 5, the well area (we
ll region) (for example, P well) 63 is formed on the substrate 38. The buried control gate area 32 is
It has conductivity and conductivity opposite to that of the substrate 38, and is preferably N-type silicon. Techniques for forming and making such N (type) plates (including selecting appropriate impurities and determining their concentrations) are well known in the art. The embedded control gate 32 is connected to the control gate signal by a contact portion / contact 66. This contact point 6
6 is, for example, a metal contact (metal contact).

Referring now to FIGS. 4 and 5, for convenience of explanation, the control gate 32 is a conventional double poly-silicon material split gate structure (double poly) described in the "Prior Art" section of this specification. split gate structure)
It functions and plays the role of the second layer of the polycrystalline silicon material described above (that is, the control gate). That is, when a voltage is supplied to the contact portion 66 (as a result, a voltage is supplied to the control gate 32) by electrostatic coupling / capacitive coupling, a potential is induced in the floating gate 36. Therefore, applying a positive voltage to the control gate 32 will capacitively and capacitively couple the positive voltage to the floating gate 36. The degree and degree of static coupling have already been studied in this technical field, and for example, US Pat.
No. 4,649,520 (Patent holder Eitan. Patent issued date March 1987
10 days). The contents of this U.S. patent are hereby incorporated by reference.

With particular reference to FIG. 4, the split gate structure shown forms two series connected transistors. The first transistor is the select or access transistor 68, which is composed of the first area 54, the thick oxide area 60, and the floating gate 36. The second transistor is a read or floating gate transistor 70,
Area 56, thin tunnel oxide area 62, and floating gate 36. Drain area 42 is connected to the drain of transistor 68, source area 40 is connected to the source of transistor 70, while transistors 68 and 70 are connected by channel 44.

The basic principle is that the threshold voltage of field effect transistors, such as transistors 68 and 70, varies as a function of gate oxide thickness. According to this, since the oxide 60 is thicker than the oxide 62, the threshold voltage of the transistor 68 is higher than that of the transistor 70. Since the threshold voltage of transistor 68 is higher,
It is possible to effectively and efficiently deal with the problem of "over-erase" described in the "prior art" of the present specification (the above problems can be solved). . In particular, if the floating gate 36 of the memory cell 30 is overerased, there will be sufficient net positive charge to keep the transistor 70 conductive. (That is, a depletion type device.) This is
This is true even if no positive potential is supplied to the control gate through the control gate 32. However, since the thick oxide 60 raises the threshold voltage of the transistor 68, the overerasure caused by manufacturing tolerances will cause the well-known inverted / inverted channel in the first area 54.
It is not enough to induce a sion channel). Therefore, transistor 68 is maintained in a non-conducting state (a true enhancement mode device) (truly enhancement-mode).
device). FIG. 6 shows a split gate transistor 3
4 shows an electrical equivalent circuit of No. 4.

Split gate structure 34 is preferably designed and constructed to have the following gate lengths: L1
The gate length shown in FIG. 4 (ie, transistor 68
Gate length) is equal to 0.9 microns plus LV, and gate length L2 (ie, the gate length of read transistor 70) is equal to 0.3 microns plus LV. Where LV
Is a Lynch Value of 0.25 micron. The gate length is the split gate transistor 3
4 applies when programming, erasing and reading.

The operation and operation of the preferred memory cell 30 embodiment shown schematically in FIG. 2 will now be described in detail with reference to FIGS. The bias conditions shown in Table 2 are applied to the program mode, erase mode, and read mode, which are the operation modes of the memory cell 30.

[0035]

[Table 2]

To program the memory cell 30,
The bias conditions shown in Table 2 are applied to the memory cell 30. In particular, Vpp is 11.5V, Vcc is 5.0V, and Vt is 1.3V. As shown most clearly in FIG. 4, the floating gate 36 has a channel hot electron prolongation.
ctron Programming). Especially,
When the source 40 is grounded and the programming voltage Vpp is applied to the high voltage bit line HV BL, a relatively large programming current flows from the drain to the source. In other words, the electrons are accelerated to flow from the source to the drain. A programming (high) voltage provided via control gate 32 is coupled to floating gate 36. Thus, the electrons gain enough energy to jump (jump) the silicon-silicon dioxide energy barrier, and thus
The oxide 60 penetrates (penetrates) and flows to the floating gate 36. The floating gate 36 itself is completely surrounded by oxide. The injected electrons raise the threshold voltage of the transistors 68 and 70 by a predetermined value.

During the erase mode, application of the bias conditions shown in Table 2 results in erase (ie, removal of charge from floating gate 36) through tunnel oxide 62. As best shown in FIG. 4, this erase is a phenomenon caused by electrons tunneling from floating gate 36 to source 40 through thin tunnel oxide 62. This tunnel phenomenon is due to Fowler-Nordhei
This is a tunnel phenomenon of n.

During the read mode, when the bias conditions of Table 2 are applied, the memory cell 30 takes one of two predetermined responses depending on the pre-existing charge on the floating gate 36. Floating gate 36
Is programmed (ie charged)
If so, neither of the transistors 68 and 70 will be turned on in response to the Vcc supplied to the control gate 32. Therefore, no current flows in the split gate transistor 34 from the source to the drain.
Conversely, if floating gate 36 is not programmed (ie, not charged),
Both the transistors 68 and 70 are turned on, and the read current (read current) Idsr is supplied from the source terminal of the split gate transistor 34 to the high voltage bit line HV.
It flows to BL. For example, the high voltage bit line HVBL is connected to a current sense amplifier (not shown). The current detection amplifier is an amplifier that continuously monitors the current of the bit line. The current detection amplifier is configured to have a predetermined threshold value, and is triggered when the read current Idsr exceeds the predetermined threshold level. When the current sense amplifier is triggered, its output changes state (the state of the output changes). The output state of the current detection amplifier indicates the state of the selected memory cell. If the memory cell 30 is not selected, the memory cell cannot supply the current to the bit line by the select transistor 68. Therefore, it does not prevent reading the state of the selected memory cell. As noted above, if floating gate 36 is overerased, transistor 70 will take the form of a depletion type device (ie, a device that will be held ON under the normal operating voltage applied to the control gate). Become). However, since the transistor 68 has a high threshold voltage, it is not affected by floating gate overerase. In particular, when memory cell 30 is not selected, control gate 32 is grounded (ie, Vss), and therefore transistor 68
Does not turn on (though transistor 70 would have conducted current without select transistor 68).

In summary, the transistor 34 performs programming, erase, reading and isolation functions (if not selected). By highly integrating and integrating the functions in this manner, the area can be greatly reduced or reduced.
In particular, a large area reduction can be achieved as compared with the conventional technique and method described based on the memory cell 10 (FIG. 1).

The memory cell 30 (particularly the structure related to the split gate transistor 34) is formed by a conventional method known to those skilled in the art (there may be a plurality of known methods, but any of them may be used). However, the memory cell 3 is preferably formed by a method including the following steps.
Make 0. First, the active areas 54 and 56 of the split gate transistor 34 are formed. Next, a layer of dielectric silicon dioxide of about 145 Å (ie,
Area 60) is created on the substrate 38. Then, a peripheral / peripheral gate mask is used to define, expose, and prepare the active area outside the memory core. After the oxide dip step known in the art, a thin gate oxide (70-150 Å) is formed around the perimeter. This step results in a total oxide thickness of about 20 in area 60, as shown in FIG.
0-325 Angstroms. Next, a standard cell threshold voltage Vt adjust implant and a surrounding threshold voltage Vt adjustment implant are performed. Thereafter, a tunnel mask is used to shape the thin tunnel oxide 62 (FIGS. 3 and 4). Then, using this mask, an embedded n + implant is made. A resist strip step well known in the art:
After the step of providing the resist-coated strips), a pre-clean (prec
lean) step is given. The preclean step is well known in the art and is a process for reducing the oxide thickness in area 60 to about 100-200 Angstroms. After this step, a high quality dielectric layer (70-100 Å thick) is formed. This fine dielectric layer formation step results in a thick oxide area 6
0 thickness increased to 170-300 angstroms,
On the other hand, the thickness of the tunnel oxide area 62 will be 70-100 angstroms. Next, polysilicon (polysili
con) layer 36 is formed. Following this, transistors and peripheral devices are formed using standard conventional CMOS (complementary metal oxide semiconductor) processes.

Referring now to FIG. 7, there is shown a modification of the split gate structure shown in FIG. The split gate transistor 34 'according to this modification includes a semiconductor substrate 38 (preferably P-type) and a source area 40'.
And a drain area 42 'separated from the source area 40'
It consists of Source area 40 'and drain area 4
A low threshold channel area 44 'is formed between 2'. Source area 40 'is heavily doped N +
It includes an ohmic contact area 46 'and an underlying P-type doping area 72. Similarly, the drain area 42 '
Is heavily doped N + ohmic contact area 50 '
And a P-type area 74 located below it. The areas 72 and 74 are more heavily doped than the substrate 38. Split gate transistor 34 'further includes a dielectric layer 58'. This dielectric layer includes a thin tunnel dielectric portion 62 ', which is preferably made of silicon oxide material. Also, its thickness is about 70-100 angstroms (particularly preferably about 80 angstroms). Transistor 34 'further includes floating gate 36
Also included.

The principle behind the operation, operation and function of split gate transistor 34 'is that the more heavily doped regions 72 and 74 form the junctions shown at 76 and 78, And that these junctions have a higher threshold than the pn junction formed between the substrate 38 and the areas 46 ', 50'. Therefore, even if floating gate 36 is overerased, the net positive charge present there is insufficient charge to form a channel from source area 40 'to drain area 42'. Therefore, if the memory cell including the split gate transistor 34 'is not selected, no leakage current flows. The bias conditions shown in Table 3 are the three operating modes of the memory cell 30 when a split floating gate transistor 34 'is used instead of the split gate transistor 34 shown in FIG. Applies to "lead".

[0043]

[Table 3]

Operation of Memory Cell 30 When Transistor 34 'is Provided The description of "program", "erase" and "read" is given in the split gate transistor 3
This is the same as the description given above regarding the memory cell 30 in which 4 is provided.

Referring now to FIG. 8, a memory cell 80 according to another embodiment is shown. This memory cell 80
Has an embedded control gate 82, a split gate transistor 84 (preferably adopting the structure of the split gate transistor 34), a floating gate 86, and an erase node 88.
The floating gate 86 includes a first portion 86a and a second portion 86a.
It is composed of a portion 86b and a third portion 86c (FIG. 9). The explanation of the symbols and abbreviations in FIG. 8 is as follows.

LV BL is a low voltage bit line CG N +, a control gate ERL, an erase line Vsource is a split gate transistor 84.
Source terminal potential.

Memory cell 80 includes a separate erase node 88 separated from split gate transistor 84.
The memory cell 30 is substantially the same as the memory cell 30 except that

Referring now to FIGS. 9 and 10, the memory cell 80 comprises a substrate 90 (preferably P-type silicon).
A generally asymmetric source and drain areas (ie, source area 92 and drain area 94), a buried P-well area 97, a buried N-type plate 98 forming an erase node control gate, and a tunnel dielectric. It consists of a body 100 (preferably a tunnel oxide). The drain area 94 is separated from the source area 92 and a channel area 96 is formed therebetween.
The tunnel oxide is, for example, a silicon dioxide material having a thickness of 70-100 Å (preferably 80 Å). The operation of the memory cell 80 will be understood by those skilled in the art by referring to Table 4.

[0049]

[Table 4]

As mentioned above, memory cell 80 includes cell 30 except that it includes a separate erase node 88.
Is the same as Since the erasing (erasing) is performed by the erasing node 88 instead of the tunnel oxide 62 (when the split gate transistor 34 is used), the gate length reflects the low voltage property of the low voltage bit line junction (to It may be shortened. In particular, the following gate length is applied to the memory cell 80 when the split gate transistor 34 is used.

Transistor 68: 0.2 micron Transistor 70: 0.4 micron plus LV where LV is the lynch value (Lynch va) of 0.25 micron.
lue).

Reference is made to Table 4. Now, assuming that Vpp, Vcc, and Vt have the above-mentioned nominal values (nominal values), the programming is again performed in the above-described order.
By way of channel hot electron programming, by way of transistors 68 and 70.

However, during the erase mode in which the bias conditions shown in Table 4 are applied, the erase occurs (is performed) via the erase node 88. In particular, in the erase, the electrons are floating gates 86 (particularly the part 8).
6c) tunnels through the tunnel oxide 100 to the n ⁺ plate 98 and the erase line ERL (Fowle).
r-Nordheim tunnel phenomenon).

The reading of the memory cell 80 is performed in the same sequence and method as described in the case of the memory cell 30. Since separate erase nodes are used, the area occupied by split gate transistor 84 can be reduced. This is because it is only necessary to supply a relatively low voltage to the low voltage bit line LV BL.

The fourth embodiment according to the present invention uses the memory cell 80 shown in FIG. 8 and employs the split gate transistor 34 'shown in FIG. The split gate transistor 34 ′ is used instead of the split gate transistor 34. The operation of this embodiment will be understood by those skilled in the art by referring to Table 5.

[0056]

[Table 5]

The operation of the memory cell 80 having the split gate transistor 34 'is the same as the operation described above for the memory cell 80 having the split gate transistor 34.

Although the present invention has been described and illustrated using the preferred embodiments above, those skilled in the art will be able to make various modifications and changes to the above embodiments within the scope of the present invention. Let's do it.

[Brief description of the drawings]

FIG. 1 is a simplified diagram of a 4.5 transistor single poly EEPROM cell according to the prior art.

FIG. 2 is a simplified diagram illustrating a preferred memory cell embodiment of the present invention.

FIG. 3 is a plan layout diagram of a semiconductor structure corresponding (corresponding to) the preferred memory cell embodiment shown in FIG. 2;

FIG. 4 is a cross-sectional view taken along the line 4-4 of FIG. 3 and is a simplified and enlarged view. This figure shows a thick oxide (film)
And a thin oxide according to the present invention (single-poly split-gate str).
ucture).

5 is a cross-sectional view taken along line 5-5 of FIG. 3, which is a simplified and enlarged view. This figure shows a buried plate used as a control gate according to the present invention.

FIG. 6 is a simplified diagram showing an electrical equivalent circuit of the memory cell schematically shown in FIG.

7 is a simplified enlarged cross-sectional view of a modification of the single poly split floating gate structure shown in FIG.

8 is a simplified diagram of a variation of the memory cell of FIG. 2 in accordance with the present invention, which specifically includes an erase node that is separate (separated) from the select transistor.

9 is a plan layout view of a semiconductor structure corresponding (corresponding to) the modification of the memory cell shown in FIG. 8;

10 is a sectional view taken along the line 10-10 of FIG. 9 and is a simplified and enlarged view. This figure shows a part of the erase node structure of the modification of the memory cell schematically shown in FIG.

[Explanation of symbols]

 30 memory cell 32 buried control gate 34 split gate transistor 36 floating gate 38 substrate 40 source area 42 drain area 44 channel area 46,50 heavily doped N + ohmic contact area 48,52 lightly doped N-type area 54 first area of channel 44 56 Second area of channel 44 58 layer of dielectric material 68, 70 transistor 80 memory cell 88 erase node HV BL high voltage bit line CG control gate LV BL low voltage bit line ERL erase line

 ─────────────────────────────────────────────────── ─── Continued Front Page (71) Applicant 596 123 420 3901 North First Stret et San Jose, California, (72) Inventor Wench Ting San Jose Lago Vista Circle, CA 4837, USA

Claims (13)

[Claims] 1. A non-volatile memory cell, which is connected to an embedded control gate for controlling programming and retrieval (reading) operation of the cell in response to an externally applied potential, and to the embedded control gate. And a split gate transistor having a floating gate portion operable as described above. 2. An erase node for erasing the non-volatile memory cell by the split gate transistor.
The non-volatile memory cell according to claim 1, further comprising a de) portion. 3. The non-volatile memory cell of claim 1, further comprising an erase node spaced from the split gate transistor to erase the non-volatile memory cell. 4. The split gate transistor is disposed on a source region, a drain region, a channel formed between the source region and the drain region, the source region, the drain region and the channel. A single layer of a dielectric material, the floating gate portion being disposed on the layer, the layer being on one of the source and drain regions and a portion of the channel. The non-volatile memory cell of claim 1 including a dielectric tunnel region extending through the dielectric tunnel region, the dielectric tunnel region being thinner than the remainder of the layer of dielectric material. 5. The split gate transistor comprises a substrate of a first conductivity type, a source region including a first portion of a second conductivity type opposite the first conductivity type, and A drain region having a first portion of two conductivity types, the source region and the drain region being spaced apart to form a channel therebetween, the source region being the second conductive region. Further comprising a second portion of the type, the second portion of the source zone extending from the first portion of the source zone to the drain zone to form a first relatively high threshold junction, The drain area further comprises a second portion having the second conductivity type, the second portion of the drain area extending from the first portion of the drain area to the source area. Comparison of two The nonvolatile memory cell according to claim 1, wherein the nonvolatile memory cell forms an extremely high threshold junction. 6. An electrically erasable and writable read-only memory (EEPRO) including a semiconductor substrate of a first conductivity type.
M) a cell, the source region of a second conductivity type having a property opposite to that of the first conductivity type formed in the substrate, and the second region of the second conductivity type formed in the substrate. A drain region of conductive type, the source region and the drain region being spaced apart to form a channel region therebetween, the channel region extending from the drain region to the source region; And a second sub-area between the first sub-area and the source area, wherein the cell is spaced from the source area, the drain area and the channel. It is formed in the substrate and the second
A conductive type buried control gate region, a single layer of dielectric material formed over the substrate, and a floating gate disposed over the layer of dielectric material. The layer has a first dielectric tunnel region extending over at least a portion of the second subregion and the source region, the thickness of the first dielectric tunnel region being: The floating gate has a thickness smaller than that of the layer provided on the first partial region and the drain region of the channel, and the floating gate extends above the channel and above the buried control gate. A second portion extending through the first channel of the channel.
A selection transistor is formed to include a subregion of the channel, the selection transistor preventing overerasing of the floating gate from causing turn-on when the memory cell is not selected, and the second portion of the channel. And a read transistor is formed to include a region, the read transistor determining a state of the memory when the memory cell is selected. Erase-writable read-only memory (EEPROM) cell. 7. By allowing electrons to be injected into the floating gate through the dielectric layer,
The select transistor is used to program the memory cell, and electrons can be removed from the floating gate through the dielectric first tunnel region to the source region to improve the dielectric property. 7. The memory cell of claim 6, wherein the first tunnel area having is used to erase the memory cell. 8. The memory cell further comprises an erase node region of the second conductivity type, the erase node region being formed in the substrate, the embedded control gate region and the drain region, The dielectric layer further comprises a dielectric second tunnel region disposed above the erase node region and spaced from the source region, and the floating gate includes the dielectric region. A select transistor for programming the memory cell by including a third portion extending over the second tunnel region having, allowing electrons to be injected into the floating gate through the dielectric layer. Used to enable electrons to be removed from the floating gate to the erase node region through the dielectric second tunnel region. The memory cell of claim 6, wherein used for the second tunnel area to erase the memory cell having the dielectric. 9. The memory cell of claim 7, wherein the first conductivity type is p-type silicon and the second conductivity type is n-type silicon. 10. The memory cell of claim 8, wherein the first conductivity type is p-type silicon and the second conductivity type is n-type silicon. 11. The source region and the drain region each have a relatively heavily doped n ⁺ portion and a relatively lightly doped n portion, thereby improving punch-through properties. 9. The memory cell according to item 9. 12. An electrically erasable and writable read-only memory (EEP) having a semiconductor substrate of a first conductivity type.
ROM cell having a first portion of a second conductivity type opposite the first conductivity type and a second portion of the first conductivity type and formed in the substrate. A source region, a drain region having a first portion of the second conductivity type and a second portion of the first conductivity type and formed in the substrate. The second portion of the region extends from the first portion of the source region to the drain region and is more heavily doped than the substrate; and the second portion of the drain region.
Part of the drain region extends from the first part of the drain region to the source region and is more heavily doped than the substrate, the source region and the drain region being spaced apart to form a channel therebetween. A buried control gate region of the second conductivity type formed in the substrate and spaced from the source region, the drain region and the channel; A layer of a dielectric material formed above and a floating gate disposed on the monolayer of the dielectric material, wherein the layer of the dielectric material is A first portion extending over the drain region, the channel region and the source region, the floating gate extending over the channel 1 portion and a second portion extending over the buried control gate, the first portion and the second portion of the source region and the first portion and the drain region of the drain region. The second portion and each of the junctions form a junction, and these junctions are associated with a first threshold value, which is greater in magnitude than the second threshold value associated with the channel, As a result, when the memory cell is not selected, the floating gate is turned on by over-erasing the floating gate.
An electrically erasable and writable read-only memory (EEPROM) cell having a semiconductor substrate of the first conductivity type. 13. The memory cell further comprises an erase node area of the second conductivity type, the erase node area being formed in the substrate and the buried control gate area, the drain area and the source. A third portion spaced apart from the region, the layer of dielectric material extending over the erase node region, and the floating gate extending over the erase node region. And allowing electrons to be injected into the floating gate through the layer of dielectric material so that the first portion of the layer of dielectric material programs the memory cell. Used to enable electrons to be removed from the floating gate through the second portion of the layer of dielectric material to the erase node area. 13. The memory cell of claim 12, wherein said second portion of said layer of dielectric material is used to erase said memory cell.