JPH09171997A - Dry etching apparatus - Google Patents

Dry etching apparatus

Info

Publication number
JPH09171997A
JPH09171997A JP33217395A JP33217395A JPH09171997A JP H09171997 A JPH09171997 A JP H09171997A JP 33217395 A JP33217395 A JP 33217395A JP 33217395 A JP33217395 A JP 33217395A JP H09171997 A JPH09171997 A JP H09171997A
Authority
JP
Japan
Prior art keywords
wafer
electrode
plasma
insulating film
ring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33217395A
Other languages
Japanese (ja)
Inventor
Masanori Sumiya
匡規 角谷
Takashi Fujii
敬 藤井
Motohiko Kikkai
元彦 吉開
Katsuji Matano
勝次 亦野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Plant Technologies Ltd
Original Assignee
Hitachi Techno Engineering Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Techno Engineering Co Ltd, Hitachi Ltd filed Critical Hitachi Techno Engineering Co Ltd
Priority to JP33217395A priority Critical patent/JPH09171997A/en
Publication of JPH09171997A publication Critical patent/JPH09171997A/en
Pending legal-status Critical Current

Links

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  • ing And Chemical Polishing (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain a dry etching apparatus by which an etching treatment is performed uniformly by a method wherein a ring which is situated at the upper part from a wafer in a plasma and which is not situated directly above the wafer is installed so as not to come into contact width the wafer. SOLUTION: A wafer 13 is conveyed to the position of a wafer 13 inside a plasma treatment apparatus by means of a conveyance device. An insulating film 12 is formed between the wafer 13 and an electrode 10, a groove its formed on the insulating film 12, the groove is filled with a gas for wafer cooling, and the wafer 13 can be adjusted to a prescribed temperature. In addition, in order to protect the electrode 10 and the insulating film from a generated plasma, a ring 17 which is supported at a treatment-chamber wall 18 by a support 21 is installed on the whole circumference near the wafer 13. In this state, a DC bias voltage is applied to the electrode 10 by a DC power supply 11, the wafer 13 is attracted to the electrode 10 via the insulating film 12, a cooling gas is then introduced to the rear of the wafer 13, high-frequency power is applied to the electrode 10 by a high-frequency power supply 15, and the etching treatment of the wafer 13 is performed. Thereby, the etching treatment of the wafer can be performed with high uniformity.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、ドライエッチング
装置に係り、特にプラズマ中のウェハ近傍にリングを設
置したドライエッチング装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dry etching apparatus, and more particularly to a dry etching apparatus having a ring installed near a wafer in plasma.

【0002】[0002]

【従来の技術】従来のドライエッチング装置では、プラ
ズマ中でウェハ近傍にウエハに接触しない形でのリング
は設置されてなく、均一性のあまり良くないエッチング
しか得られていなかった。
2. Description of the Related Art In a conventional dry etching apparatus, no ring was provided near the wafer in the plasma so as not to come into contact with the wafer, and only etching with poor uniformity was obtained.

【0003】また、プラズマ中でウエハに接触する構造
のものはあった。
There is also a structure in which the wafer is in contact with plasma.

【0004】[0004]

【発明が解決しようとする課題】従来のドライエッチン
グ技術では、プラズマ中でウェハ近傍にウエハに接触し
ない形でのリングが設置されてなく、ウェハの高均一な
エッチング処理が不可能であった。
In the conventional dry etching technique, no ring was installed in the vicinity of the wafer in the plasma so as not to come into contact with the wafer, and highly uniform etching treatment of the wafer was impossible.

【0005】本発明の目的は、プラズマ中にウエハが接
触しない構造のリングを設置することにより、ウェハの
高均一なドライエッチング装置を提供することにある。
An object of the present invention is to provide a highly uniform dry etching apparatus for a wafer by installing a ring having a structure in which the wafer does not come into contact with plasma.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するた
め、プラズマ中にウエハに接触しない構造のリングを設
置したものである。
In order to achieve the above object, a ring having a structure that does not contact the wafer is installed in the plasma.

【0007】[0007]

【発明の実施の形態】本発明の一実施例を図1及び図2
により説明する。図1は、本発明で使用したプラズマ処
理装置の概略図である。図1において、プラズマ処理装
置は、石英窓8と処理室壁18により処理室3を大気か
ら遮断している。また、処理室壁18はアースされてい
る。また、排気口4、圧力調整弁5、排気系16により
処理室3内を真空にすることができ、かつ、処理室3内
の圧力を所定の圧力に制御することができる構造であ
る。そして、電極10内には空洞部19が設置してあ
り、空洞部19の中に温調器で温調された冷媒を流すこ
とにより電極10を温調できる構造である。
1 and 2 show an embodiment of the present invention.
This will be described below. FIG. 1 is a schematic diagram of a plasma processing apparatus used in the present invention. In FIG. 1, in the plasma processing apparatus, the processing chamber 3 is isolated from the atmosphere by the quartz window 8 and the processing chamber wall 18. The processing chamber wall 18 is grounded. Further, the inside of the processing chamber 3 can be evacuated by the exhaust port 4, the pressure control valve 5, and the exhaust system 16, and the pressure inside the processing chamber 3 can be controlled to a predetermined pressure. A hollow portion 19 is installed inside the electrode 10, and the structure is such that the temperature of the electrode 10 can be adjusted by flowing a coolant whose temperature is adjusted by a temperature adjuster into the hollow portion 19.

【0008】上記構成において、ウエハ13は図示を省
略した搬送装置により図1の処理装置の中のウエハ13
の位置に搬送される。ウエハ13と電極10の間には絶
縁膜12が設置してある。その絶縁膜12には溝があ
り、該溝にウエハ冷却用ガスをみたすことにより、ウエ
ハと電極との間で熱交換が行なわれ、ウエハを所定の温
度に調節することができる。
In the above structure, the wafer 13 is transferred to the wafer 13 in the processing apparatus shown in FIG.
Is transported to the position. An insulating film 12 is provided between the wafer 13 and the electrode 10. The insulating film 12 has a groove, and by filling the groove with a gas for cooling the wafer, heat is exchanged between the wafer and the electrode, and the wafer can be adjusted to a predetermined temperature.

【0009】電極10及びその絶縁膜12を発生プラズ
マから保護するため、支え21により処理室壁18に支
持されたリング17をウェハ近傍の全周に設置してい
る。
In order to protect the electrode 10 and its insulating film 12 from the generated plasma, a ring 17 supported by the support 21 on the processing chamber wall 18 is installed all around the wafer.

【0010】また、電極10には直流電源11が接続さ
れており、電極に直流電圧を印加できる。そして、電極
10にはコンデンサ20を介して交流電源15が接続さ
れており、交流電圧を印加できる。
A DC power supply 11 is connected to the electrode 10 so that a DC voltage can be applied to the electrode. An AC power supply 15 is connected to the electrode 10 via a capacitor 20 so that an AC voltage can be applied.

【0011】つぎに、ガス導入口1からガス流量制御弁
2によって流量を制御させたプラズマ発生用ガスを処理
室3に導入し、排気口4を介して真空ポンプおよび圧力
調整弁5によって、処理室3内の圧力をプラズマ処理す
る所定の圧力に調節する。この状態でマイクロ波発生器
6により発信されたマイクロ波がマイクロ波導波管7を
介し、石英窓8を通して処理室3に導入され、コイル9
により発生された磁場と電子サイクロトロン共鳴をおこ
し、プラズマ発生用ガスがプラズマ化される。その状態
で、電極10に直流電源11により直流バイアス電圧を
かけることにより絶縁膜12を介してウエハ13と電極
の間に静電吸着力を発生させ、ウエハ13を電極に吸着
させる。
Next, a gas for plasma generation whose flow rate is controlled by the gas flow rate control valve 2 is introduced into the processing chamber 3 from the gas introduction port 1 and is processed by the vacuum pump and the pressure adjusting valve 5 through the exhaust port 4. The pressure in the chamber 3 is adjusted to a predetermined pressure for plasma processing. In this state, the microwave generated by the microwave generator 6 is introduced into the processing chamber 3 through the microwave window 7 through the quartz window 8 and the coil 9
Electron cyclotron resonance is caused with the magnetic field generated by, and the gas for plasma generation is turned into plasma. In that state, a DC bias voltage is applied to the electrode 10 by the DC power supply 11 to generate an electrostatic attraction force between the wafer 13 and the electrode through the insulating film 12 to attract the wafer 13 to the electrode.

【0012】そののち、ウエハ裏面にウエハ冷却用ガス
を導入し高周波電源15により電極に高周波電力を印加
し、ウェハのエッチング処理を行う。該エッチング処理
により、エッチングの均一性が22.8%(リング無)か
ら6.9%(リング有)に向上できた。
After that, a wafer cooling gas is introduced to the back surface of the wafer, and high-frequency power is applied to the electrodes by the high-frequency power source 15 to perform etching processing on the wafer. By the etching treatment, the etching uniformity could be improved from 22.8% (without ring) to 6.9% (with ring).

【0013】本実施例では、支え21により処理室壁1
8に支持されたリング17をウェハ近傍の全周に設置す
ることにより、ウェハの高均一なエッチング処理ができ
る。
In this embodiment, the wall 21 of the processing chamber is supported by the support 21.
By installing the ring 17 supported by 8 around the entire circumference of the wafer, highly uniform etching of the wafer can be performed.

【0014】[0014]

【発明の効果】本発明によれば、プラズマ中でウエハよ
りも上方で、かつウエハの直上に位置しないリングを、
ウエハに接触しないように設置したことにより、ウェハ
の高均一なエッチング処理ができるという効果がある。
According to the present invention, a ring that is not located above the wafer and directly above the wafer in the plasma is
Since the wafer is installed so as not to come into contact with the wafer, there is an effect that the wafer can be highly uniformly etched.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例であるプラズマ処理装置を示
す構成図である。
FIG. 1 is a configuration diagram showing a plasma processing apparatus according to one embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1…ガス導入口、2…ガス流量制御弁、3…処理室、4
…排気口、5…圧力調整弁、6…マイクロ波発生器、7
…マイクロ波導波管、8…石英窓、9…コイル(磁場発
生器)、10…電極、11…直流電源、12…絶縁膜、
13…ウエハ、14…温調器、15…交流電源、16…
排気系、17…リング、18…処理室壁、19…空洞
部、20…コンデンサ、21…ササエ、22…電極カバ
ー。
1 ... Gas inlet, 2 ... Gas flow control valve, 3 ... Processing chamber, 4
... Exhaust port, 5 ... Pressure control valve, 6 ... Microwave generator, 7
... microwave waveguide, 8 ... quartz window, 9 ... coil (magnetic field generator), 10 ... electrode, 11 ... DC power supply, 12 ... insulating film,
13 ... Wafer, 14 ... Temperature controller, 15 ... AC power supply, 16 ...
Exhaust system, 17 ... Ring, 18 ... Processing chamber wall, 19 ... Cavity, 20 ... Capacitor, 21 ... Feed, 22 ... Electrode cover.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 吉開 元彦 山口県下松市大字東豊井794番地 日立テ クノエンジニアリング株式会社笠戸事業所 内 (72)発明者 亦野 勝次 山口県下松市大字東豊井794番地 株式会 社日立製作所笠戸工場内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Motohiko Yoshikai 794 Azuma Higashitoyo, Shimomatsu City, Yamaguchi Prefecture Inside the Kasado Plant, Hitachi Techno Engineering Co., Ltd. No. 794 Stock company Hitachi Kasado factory

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】プラズマ中でウエハよりも上方で、かつウ
エハの直上に位置しないリングを、ウエハに接触しない
ように設置し、高均一なエッチング処理を行うことを特
徴とするドライエッチング装置。
1. A dry etching apparatus, characterized in that a ring which is not above the wafer and directly above the wafer in plasma is installed so as not to come into contact with the wafer to perform a highly uniform etching process.
【請求項2】請求項1記載のドライエッチング装置にお
いて、前記リングの設置によって、電極カバーをプラズ
マから保護する構造としたことを特徴とするドライエッ
チング装置。
2. The dry etching apparatus according to claim 1, wherein the electrode cover is protected from plasma by installing the ring.
JP33217395A 1995-12-20 1995-12-20 Dry etching apparatus Pending JPH09171997A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33217395A JPH09171997A (en) 1995-12-20 1995-12-20 Dry etching apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33217395A JPH09171997A (en) 1995-12-20 1995-12-20 Dry etching apparatus

Publications (1)

Publication Number Publication Date
JPH09171997A true JPH09171997A (en) 1997-06-30

Family

ID=18251984

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33217395A Pending JPH09171997A (en) 1995-12-20 1995-12-20 Dry etching apparatus

Country Status (1)

Country Link
JP (1) JPH09171997A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014523114A (en) * 2011-06-15 2014-09-08 アプライド マテリアルズ インコーポレイテッド Hybrid laser / plasma etching wafer dicing using substrate carrier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014523114A (en) * 2011-06-15 2014-09-08 アプライド マテリアルズ インコーポレイテッド Hybrid laser / plasma etching wafer dicing using substrate carrier

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