JPH09171377A - Memory for video display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory for a video display capable of writing color- developed image data at a high speed. SOLUTION: A color code of a foreground color is stored in FGC register 14 and that of a background color is stored in BGC register 15 beforehand. 8-bit write data 17 expressing each picture element with binary are inputted to a selection circuit 16 as selection signal. The selection circuit 16 selects either FGC register 14 or BGC register 15 for every bit of the write data and outputs color codes for 8 bytes. These are simultaneously written in successive 8-byte areas starting from a specified address. A high speed color plotting is enabled by internally developing color code and simultaneously writing the multiple color codes after development.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video display memory for storing image data for displaying an image on a display device such as a display, and more particularly to a color display in which the color of each pixel is represented by a color code of a plurality of bits. And a video display memory for storing the image data.

[0002]

2. Description of the Related Art When an image is displayed on a display device such as a display, image data corresponding to the image to be displayed is written in a video display memory (hereinafter referred to as VRAM), and the image stored in this memory is written. The data is repeatedly read at a predetermined cycle and sent to the display. As a result, the image data is simply written into the VRAM once, and thereafter the display can be continuously performed. When the display content is partially changed, the image data of the VRAM may be rewritten only in that portion.

When a color image is displayed, a color code composed of a plurality of bits is assigned to one pixel,
The color to be displayed is specified for each pixel. For example, when the character represented by the character pattern is displayed in color with binary data of “1” and “0”,
“1” is converted to a color code corresponding to the front color, and “0” is converted to a color code corresponding to the background color. The VRAM stores a color code represented by a plurality of bits for one pixel. At this time, usually, the drawing target area is first painted with the background color, and then the portion corresponding to the character pattern "1" is drawn with the foreground color.

When each pixel is represented by a color code of a plurality of bits as described above, the data amount increases, so that the processing load for writing image data to the VRAM increases, and C
The use efficiency of a processing device that generates image data, such as a PU (Central Processing Unit), is reduced. Therefore, various techniques have been proposed for reducing the load on the CPU when drawing a color image.

Japanese Patent Application Laid-Open No. 61-283970 discloses an image data processing apparatus in which a conversion circuit for converting binary data of each pixel into a color code corresponding to a background color and a foreground color is provided between a CPU and a VRAM. It has been disclosed. In this device, a foreground color register for storing a color code of a foreground color and a background color register for storing a color code of a background color are provided in a conversion circuit, and the color code of a color to be drawn is registered in advance in these. The CPU sets the binary pattern data to be drawn in the conversion circuit, the bit number thereof, and the address on the VRAM where the expanded color code is to be written in the conversion circuit.

The conversion circuit holds the color code held in the foreground color register when the value is "1" from the first bit of the pattern data, and holds the color code held in the background color register when the value of the pattern data is "0". Each bit is sequentially converted into a color code. Then, the converted color codes are sequentially stored in a VRAM.
Write to. By providing the conversion circuit in this way, it is not necessary for the CPU to develop each pixel into a color code, and the burden can be reduced.

[0007]

By using a conversion circuit to develop color codes, the load on the CPU can be reduced. However, a color code composed of a plurality of bits for each pixel is transferred from the conversion circuit to the VRAM. You have to write the code. Therefore, the amount of data to be input to the VRAM is not reduced even if the conversion circuit is provided. For this reason,
It takes a long time to transfer the color code from the conversion circuit to the VRAM, and there is a problem that drawing cannot be performed at high speed.

For example, if the color expressed on the VRAM is 2
In the case of 56 colors, 8 bits (1 byte) are required for each pixel as a color code. In this case, if the one-byte binary pattern data is developed into a color code by the conversion circuit, the generated eight-byte data must be written to the VRAM, and it takes a long time to transfer the color code from the conversion circuit to the VRAM. I need it.

SUMMARY OF THE INVENTION An object of the present invention is to provide a video display memory capable of writing color-developed image data at high speed.

[0010]

According to the first aspect of the present invention, there are provided first and second color code holding means for storing a color code composed of a plurality of predetermined bits representing a color type;
A plurality of memory cells each capable of storing image data having the same number of bits as this color code and two pixels for each pixel.
When pattern data for a plurality of pixels represented by value information is input, one of the color code stored in the first color code holding unit and the color code stored in the second color code holding unit is used. Color code selecting means for selecting and outputting color codes for a plurality of pixels according to the value of each pixel of the input pattern data, and designating any one of a plurality of memory cells in parallel with the pattern data Memory cell selecting means for selecting a number of continuous memory cells equal to the number of pixels of the pattern data, starting with a specified memory cell when address information for inputting the data is inputted, and a memory selected by the memory cell selecting means. The video display memory includes parallel writing means for simultaneously writing color codes for a plurality of pixels output from the color code selection means in the cell.

That is, in the first aspect of the present invention, the holding means for holding the color codes of the foreground color and the background color is provided inside the video display memory. 2 for multiple pixels
When value pattern data is input, each pixel is developed into a foreground color code and a background color code in accordance with the value. The color codes for the plurality of pixels are simultaneously written into the memory cells consecutive from the designated address by the number equal to the number of pixels of the pattern data. Thus, VR
Since the color code is developed inside the AM, the image data to be transferred to the VRAM may be binary information.
The amount of data to be transferred to M can be reduced.

According to the second aspect of the present invention, the first and second color code holding means storing a color code composed of a predetermined plurality of bits representing a color type, and storing image data having the same number of bits as the color code. A plurality of memory cells each of which can be stored, and a plurality of pixels each of which is represented by binary information in a state where a first writing mode is designated as a writing mode when writing image data into these memory cells. When either of the color code stored in the first color code holding means and the color code stored in the second color code holding means is input when the pattern data of A color code selecting means for selecting a color code for each pixel according to the value and outputting a color code for a plurality of pixels; When address information for designating an arbitrary one of a plurality of memory cells is input in a row, a specified number of continuous memory cells equal to the number of pixels of the pattern data are selected starting from the designated memory cell. A memory cell selection unit, and a plurality of pixels output by the color code selection unit in a memory cell selected by the memory cell selection unit when pattern data and address information are input in a state where the first write mode is designated; Indicates the address information when the pattern data and the address information are input in a state where the parallel write means for simultaneously writing the color codes and the second write mode as another write mode different from the first write mode is designated. A video display memory includes a writing unit for writing pattern data to one memory cell. It is caused.

That is, in the second aspect of the present invention, when the first write mode is designated, each bit of the input pattern data is developed into a color code, and the memory which is continuous with the designated address at the head is developed. Write the expanded color code to the cell. In the state where the second write mode is specified, the input pattern data is written to the specified address as it is. Since writing can be performed in different formats by specifying the mode in this way, the video display memory can be easily used for purposes other than displaying a color image.

According to the third aspect of the present invention, three or more predetermined number of color code holding means for storing a color code consisting of a predetermined plurality of bits representing a color type, and any one of these color code holding means Selecting means for selecting two of the following;
A plurality of memory cells each capable of storing image data having the same number of bits as the color code, and two memory cells selected by the selection means when pattern data for a plurality of pixels, each pixel being represented by binary information, is input. Color code selection means for selecting one of the color codes held in the two color code holding means according to the value of each pixel of the input pattern data and outputting a color code for a plurality of pixels, When address information for designating an arbitrary one of a plurality of memory cells is input in parallel, a specified number of consecutive memory cells equal to the number of pixels of the pattern data are selected starting from the designated memory cell. At the same time, the memory cell selecting means and the color code for a plurality of pixels output from the color code selecting means are simultaneously applied to the memory cell selected by the memory cell selecting means. And it is provided in a memory for video display and parallel writing means for writing.

That is, according to the third aspect of the present invention, three or more means for holding color codes are provided, and two of them are selected and used for developing pattern data into color codes. By changing the two selected color code holding units, the color code in which the pattern data is developed can be changed, so that the color switching process can be performed at high speed.

According to the fourth aspect of the present invention, a predetermined one of the plurality of memory cells is used as the color code holding means.

That is, in the invention according to claim 4, a predetermined one of the plurality of memory cells holds a color code in advance. Then, a color code stored in advance in these memory cells is selected according to the value of the pattern data, and the developed color code is written in the memory cell specified by the address information. By using a memory cell as a means for holding a color code in this way, it is possible to easily store a large number of color codes in advance.

According to the fifth aspect of the present invention, the plurality of memory cells are a memory cell array arranged in an array, and the memory cell selecting means is designated by the address information in the memory cell array when the address information is input. Row selection means for selecting a row in which a memory cell is present, and column selection for selecting a continuous column equal to the number of pixels of the pattern data starting from the column in which the memory cell designated by the address information is input Means, and the parallel writing means comprises: a row buffer for temporarily holding the storage contents of memory cells of an arbitrary row in the memory cell array; and a row buffer for one row selected by the row selecting means. Reading means for reading the storage contents of the memory cells into a row buffer;
Rewriting means for rewriting a portion corresponding to the column selected by the column selection means in the row buffer in which the storage contents of the memory cells for one row are stored by the reading means with a color code output from the color code selection means; Row writing means for writing the contents of the row buffer rewritten by the rewriting means into the corresponding row of the memory cell array.

That is, according to the fifth aspect of the present invention, the storage contents of one row specified by the address information are read out from the memory cell array into the row buffer, and after a plurality of pixels are expanded from the column specified by the address information. The color code has been rewritten. Then, the contents of the rewritten row buffer are written in the corresponding row of the memory cell array. This makes it easy to simultaneously write color codes for a plurality of pixels corresponding to the pattern data.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION

[0021]

FIG. 1 shows an outline of the configuration of a video display memory according to an embodiment of the present invention. A video display memory (hereinafter also referred to as a VRAM) 10 includes a memory cell array 11 for storing image data, and a column address and a row address for designating a cell in the memory cell array 11 from which image data is to be read or written. It comprises a column address decoder 12 and a row address decoder 13 for decoding. Further, it has an FGC register 14 which is a register for storing a color code of a foreground color and a BGC register 15 which is a register for storing a color code of a background color.

The number of bits of the color code is composed of 8 bits, and can represent any one of 256 colors. The selection circuit 16 includes write data 17, an FGC register 14, or a BGC as data to be written to the memory cell array 11.
This circuit selects one of the registers 15. The write data 17 has a bit width of 8 bits. The timing control circuit 18 is a circuit for controlling the timing of reading from and writing to the memory cell array 11.

Address information 19 input from a CPU (not shown) is decoded by a row address decoder 13 and a column address decoder 12, respectively. The row address decoder 13 decodes a row address and designates any one row of the memory cell array 11. The column address decoder 12 decodes a column address and designates any one column of the memory cell array 11. The input write data 17 contains address information 1
1 that matches both in the row and column directions specified by 9
Data is written into one memory cell in accordance with the timing indicated by the timing control circuit 18.

The video display memory 10 has a through mode in which the write data 17 is written to the memory cell array 11 as it is, and a conversion mode in which the write data 17 is replaced with a color code and written. In the conversion mode, each bit of the 8-bit write data 17 is replaced with a color code held in the FGC register 14 or the BGC register 15, respectively. These eight-byte color codes are written into eight consecutive memory cells from the memory cell designated by the address information 19.

FIG. 2 shows an example of how 1-byte write data is converted into an 8-byte color code and written into a memory cell array. Selection circuits 21 to
Reference numeral 28 is provided for each bit of the write data 29, and a mode selection signal 31 for switching between the through mode and the conversion mode is input to each selection circuit. Also, each selection circuit has 8
The bit color code, the 8-bit color code from the BGC register 33, and the corresponding 1-bit data of the write data 29 are input. Each bit of the write data 29 is branched into two and input to each of the selection circuits 21 to 28. One of them is used as data to be written in the through mode, and the other is used to select the FGC register 32 or the BGC register 3 in the conversion mode.
3 is used as a selection signal 34 for selecting.

Assuming that the memory cell designated by the address information is the first memory cell 41, in the through mode, the eight bits of the write data 29 remain unchanged in the first memory cell.
Is written to the memory cell 41 of In the conversion mode, the selection circuits 21 to 28 output the FG signal when one bit value of the input write data 29 is “1”.
The C register 32 is selected, and when "0", the BGC register 33 is selected to output 1-byte data 42, respectively. Therefore, by providing 1-byte write data 29, an 8-byte color code is generated.

The color code of a total of 8 bytes output from these eight selection circuits 21 to 28 is simultaneously written to eight consecutive memory cells 41, 43 to 49 from the first memory cell 41 specified by the address information. Be included. In the example shown in FIG. 2, the color code of “01100110” stored in the FGC register 32 is output from the selection circuits 24, 25, 27, and 28 corresponding to the bits whose write data value is “1”. The data is written to the memory cell at the corresponding address. The color code of “10111001” stored in the BGC register 33 is output from the selection circuits 21 to 23 and 26 corresponding to the bit of the write data of “0”, and is written to the memory cell of the corresponding address. ing.

FIG. 3 shows in detail the circuit of the video display memory shown in FIG. The VRAM has a column address buffer 52 and a row address buffer 5 for inputting an address signal 51 from a CPU (not shown).
3 is provided. The write data 54 from the CPU is input via the data input buffer 55. The read data is output from the video display memory to the CPU (not shown) via the data output buffer 56. The VRAM includes a refresh controller 57 and a refresh counter 58 therein, and a refresh address 59 is sequentially generated to periodically access a memory cell so that stored contents are not lost. The VRAM includes first and second clock generators 61 and 62, and the timing of the write or read operation is controlled according to the clock signals output from these generators.

The memory cell array 63 has 1024 rows × 5
Eight memory cells are arranged in a 12-column array. The row address decoder 64 decodes address information from the row address buffer 53 and
Select any one of the rows. The column address decoder 65 decodes the address information from the column address buffer 52 and selects any one of the 512 columns. As described above, one memory cell in 1024 rows × 512 columns has eight arrays of memory cells designated by the column address and the row address, so that one-byte data is accessed at a time.

The VRAM is capable of so-called page mode access in which memory cells of one row are continuously accessed, and one row (512 × 8 bits) designated by the row address decoder 64 is sense amplifier 66.
Can be imported at once. The selection circuit 67 includes 512 selection circuit elements having three inputs and one output. That is, as many selection circuits as the number corresponding to one row which can be taken into the sense amplifier 66 are provided.

Here, the color code is composed of 8 bits, and each of the FGC register 68 for storing the foreground color and the BGC register 69 for storing the background color can store one color code. I have. The output of the FGC register 68, the output of the BGC register 69, and the write data 54 input via the data input buffer 55 are input to each of the selection circuit elements as shown in FIG. The substrate bias generator 71 is a circuit that applies a bias voltage for driving the memory cell array 63.

First, the write operation in the through mode will be described.

In the through mode, each selection circuit element 66
Selects one byte of data from the data input buffer 55 among the three inputs. Then, the one-byte data is written to the memory cell specified by the column address and the row address. As a result, various data can be written to the video display memory without being developed as a color code.

Next, the write operation in the conversion mode will be described.

As preparation before writing in the conversion mode, a color code corresponding to the foreground color is stored in the FGC register 68.
Write to. Further, a color code corresponding to the background color is written in the BGC register 69. Thereafter, an external CPU (not shown) that writes the image data designates an address for storing the image data expanded into the color code, and writes 8-bit binary image data as write data 54 to the VRAM. Each bit of the write data 54 is input as a selection signal to the eight selection circuits successively starting from the designated address, one bit at a time in order from the most significant bit.

The selection circuit to which "1" is input as the selection signal selects and outputs the 8-bit color code stored in the FGC register 68. The selection circuit to which "0" is input selects and outputs the 8-bit color code stored in the BGC register 69. The 8-byte color code data output from these eight selection circuits consecutive from the designated address is stored in the corresponding location of the sense amplifier 66 that can hold one row of data (512 × 8 bits). Is entered.

The sense amplifier 66 exchanges data with the memory cell array by validating continuous 8 bytes of data from the address specified by the row and column addresses, and simultaneously writes 8 bytes into the memory cell array. As described above, the 1-byte write data 54 is developed into 8-byte color codes inside the VRAM, and these are written to the memory cell array 63 at once through the sense amplifier 66. Thus, the amount of data transferred between the CPU and the video display memory can be reduced, and the time required for writing can be reduced. Further, since eight bytes of data are written at one time from the sense amplifier 66, the writing of eight-byte color codes to the memory cells can be performed at high speed.

In the embodiment described above, one color code is stored in each of the FGC register and the BGC register. However, a partial area of the memory cell array may be used instead. In this case, color code data for a plurality of required foreground colors and background colors are stored in advance in the memory cell array, and the foreground colors and background colors can be switched as needed. This makes it possible to change the foreground color and the background color at high speed. Further, even when a plurality of FGC registers and a plurality of BGC registers are prepared, the same operation can be performed. Further, in the embodiment, the description has been made in units of 8 bits, but the number of bits of the color code is not limited to this.

[0039]

As described above, according to the first aspect of the present invention, since the binary pattern data is developed into the color code inside the video display memory, the image data to be transferred to the video display memory is Data volume can be reduced.
Also, since the color codes for a plurality of pixels after internally developed are simultaneously written in the memory cells, the color codes after the development can be stored at high speed. These enable high-speed drawing of color image data.

According to the second aspect of the present invention, there are provided a mode for writing binary data as it is and a mode for developing binary data into a color code and writing the color code. The video display memory can be used for both other purposes.

Further, according to the third aspect of the present invention, the color code in which the pattern data is developed can be changed by changing the two selected color code holding means, so that the color can be switched at high speed. It can be carried out.

According to the fourth aspect of the present invention, since the memory cells are used as the color code holding means for holding the color codes, it is possible to easily store a large number of color codes in advance.

According to the fifth aspect of the present invention, the stored contents of one row specified by the address information are read out from the memory cell array to the row buffer, and only a plurality of pixels are expanded from the column specified by the address information. The color code has been rewritten. Then, the contents of the rewritten row buffer are written in the corresponding row of the memory cell array. This makes it easy to simultaneously write color codes for a plurality of pixels corresponding to the pattern data.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a video display memory according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an example of a state in which 1-byte write data is converted into an 8-byte color code and written into a memory cell array.

FIG. 3 is a block diagram showing the configuration of a video display memory shown in FIG. 1 in more detail;

[Explanation of symbols]

 11, 63 Memory cell array 12, 64 Row address decoder 13, 65 Column address decoder 14, 32, 68 FGC register 15, 33, 69 BGC register 16, 21, 28, 67 Selection circuit 17, 29, 54 Write data 18 Timing control Circuit 19, 51 Address information 66 Sense amplifier I / O gate

Claims (5)

[Claims] A first and a second color code holding means for storing a color code composed of a predetermined plurality of bits representing a type of a color, and storing image data having the same number of bits as the color code. A plurality of memory cells, and a color code and a second color code stored in the first color code holding means when pattern data for a plurality of pixels, each pixel being represented by binary information, is input. A color code selection unit that selects one of the color codes held in the holding unit according to the value of each pixel of the input pattern data and outputs a color code for the plurality of pixels; When address information for designating an arbitrary one of the plurality of memory cells is input, the designated memory cell is equal to the number of pixels of the pattern data starting from the designated memory cell. Memory cell selecting means for selecting a large number of continuous memory cells; parallel writing means for simultaneously writing the color codes for the plurality of pixels output by the color code selecting means in the memory cells selected by the memory cell selecting means; A video display memory, comprising: 2. A first and a second color code holding means for storing a color code composed of a predetermined plurality of bits representing a color type, and image data having the same number of bits as the color code. A plurality of memory cells and pattern data of a plurality of pixels each of which is represented by binary information in a state where a first writing mode is designated as a writing mode for writing image data into these memory cells are input. When one of the color code stored in the first color code holding unit and the color code stored in the second color code holding unit is used, the color code is stored in accordance with the value of each pixel of the input pattern data. A color code selection unit for selecting and outputting a color code for the plurality of pixels, and a color code selection unit that is in parallel with the pattern data in a state where the first write mode is specified. When address information for designating an arbitrary one of the plurality of memory cells is input in a row, a specified number of consecutive memory cells equal to the number of pixels of the pattern data are selected starting from the designated memory cell. A memory cell selection unit to be selected; and a memory cell selected by the memory cell selection unit when the pattern data and the address information are input in a state where the first write mode is designated. Parallel writing means for simultaneously writing the color codes for the plurality of pixels to be output; and the pattern data and the address information in a state where a second writing mode as another writing mode different from the first writing mode is designated. Write pattern data to one memory cell indicated by address information when is input Video display memory, characterized in that it comprises a viewing means. 3. A color code holding means provided with a predetermined number of three or more color codes each storing a predetermined plurality of bits representing a color type, and any two of these color code holding means are selected. Selecting means; a plurality of memory cells each capable of storing image data having the same number of bits as the color code; and selecting when plural pixels of pattern data representing each pixel by binary information are input. A color code for selecting one of the color codes held in the two color code holding means selected by the means according to the value of each pixel of the input pattern data and outputting a color code for the plurality of pixels Selecting means; a memory designated when address information for designating any one of the plurality of memory cells is inputted in parallel with the pattern data Memory cell selecting means for selecting a number of continuous memory cells equal to the number of pixels of the pattern data starting from the first pixel, and the plurality of pixels output by the color code selecting means to the memory cell selected by the memory cell selecting means. A video display memory, comprising: a parallel writing means for simultaneously writing color codes for the respective minutes. 4. The video display memory according to claim 1, wherein said color code holding means uses a predetermined one of said plurality of memory cells. 5. The memory cell array according to claim 1, wherein the plurality of memory cells are memory cell arrays arranged in an array, and the memory cell selecting means is configured to, when the address information is input, select a memory cell of the memory cell array designated by the address information. Row selection means for selecting an existing row, and column selection means for selecting a continuous column equal to the number of pixels of the pattern data, starting from the column where the memory cell specified by the address information is input, and Wherein the parallel writing means includes a row buffer for temporarily storing the memory contents of an arbitrary row of the memory cells in the memory cell array, and a row buffer for one row selected by the row selection means. Reading means for reading the stored contents of the memory cells into the row buffer; and the reading means stores the stored contents of the memory cells for one row. Rewriting means for rewriting a portion of the row buffer corresponding to the column selected by the column selection means to a color code output by the color code selection means,
2. A row writing means for writing the contents of a row buffer rewritten by the rewriting means into a corresponding row of the memory cell array.
A video display memory according to claim 3.