JPH09167195A - Neuro element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a neural network using a radius base function in simple configuration and to easily produce a neuro element by multiplying outputs provided from a differential amplifier equipped with plural transistors. SOLUTION: Concerning the neuro element for consisting of the neural network while using the radius base function, a differential amplifier circuit 11 is provided with a constant voltage source 21, two resistors RC, two bipolar transistors Q1 and Q2 , two variable resistors RE and constant current source 22. In this case, the input to the virtual node of neural network is defined as an input to any one of transistors Q1 and Q2 at least. Then, collector voltages generated by collector currents I1 and I2 of both the transistors Q1 and Q2 become the inputs of multiplier circuit part 13, and the multiplier circuit part 13 finds the product of these two voltages and outputs that product.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a neural element for constructing a neural network imitating the nervous system of the human brain, and more particularly to a neural element which can be easily realized by a semiconductor integrated circuit.

[0002]

2. Description of the Related Art An information processing apparatus (neurocomputer) having a neural network imitating the nervous system of the human brain has been receiving attention. Such a neurocomputer can obtain an ambiguous solution in information processing that Neumann-type computers are not good at by changing the connection strength between many neurons according to a predetermined learning algorithm.

As a conventional example of a neuro element necessary for realizing a neural network as a device rather than a program, a device using an EEPROM has been proposed (JP-A-3-144785). With this neuro element,
Multiply each input signal by the respective coefficient and enter the sum of them into a threshold function such as a sigmoid function,
The calculated value of the function is used as the output of the neuro element.

On the other hand, unlike the threshold function, a neural network using a radial basis function has also been devised. As a configuration for realizing this kind of neural network by hardware, a Gaussian function is a radial vector. Only neural networks with basis functions are known (“A Gaussian Synapse Circuit For Analog VLSINe
ural Networks ")

[0005]

The circuit of the neuro element for constructing the neural network having the Gaussian function as the radial basis function is complicated and its manufacture is not easy.

The present invention has been made in view of such circumstances, and a neural network using a radial basis function can be realized by hardware having a simple structure to prevent malfunction, and at a simple process. It is an object of the present invention to provide a neuro element that can be manufactured and has a high yield.

[0007]

A neuro element according to claim 1 of the present invention is a neuro element for constructing a neural network using a radial basis function, which has two transistors, and the neural network A differential amplifier having an input to a virtual node of at least one of the transistors as an input, and a multiplier for multiplying outputs of the both transistors obtained from the differential amplifier. .

A neuro element according to claim 2 of the present invention comprises:
The radial basis function according to claim 1, wherein f (b, x) is
= A / {1 + cosh (bx)} (where A: constant,
b: parameter determined by the learning rule).

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments.

FIG. 1 is a schematic diagram showing an example of the configuration of a general neural network using a radial basis function. In this example, a one-dimensional output vector is obtained from a two-dimensional input vector. ing. The neural network includes an input layer having a first input node 1a and a second input node 1b, a first intermediate node 2a and a second intermediate node 2b.
And an output layer having an output node 3.

The input value in [1] is input to the first input node 1a, and the value converted using the parameter t [1] [1] is input to the first intermediate node 2a and the parameter t [2] [1]. ]
The value converted by using is output to the second intermediate node 2b. On the other hand, the input value in is input to the second input node 1b.
[2] is input, and the value converted using the parameters t [1] [2] is input to the first intermediate node 2a and the parameter t
[2] The value converted using [2] is the second intermediate node 2b.
Respectively. Note that t [1] [1], t
[2] [1], t [1] [2], t [2] [2] are learning rules for radial basis functions (for example, stochastic gradient descent method, reference “Characterization of complexities in Czochralski”).
crystal growth by nonlinear forecasting ", T. Miyano
76 (5), 1 September 1994), et al., J. Appl. Phys.

The first intermediate node 2a has a radial basis function f
H (1) is calculated using (b, x) as in the following (Equation 1) and output to the output node 3. Also, the second intermediate node
2b is also h using the radial basis function f (b, x).
[2] is calculated as in the following (Equation 2) and output to the output node 3. Note that b [1] and b [2] are parameters determined by the learning rule of the radial basis function.

[0013]

[Equation 1]

The output node 3 calculates and outputs the output value out [1] as in the following (formula 3). Note that c
[1] and c [2] are parameters determined by the learning rule of the radial basis function. out [1] = c [1] · h [1] + c [2] · h [2] (Equation 3)

In such a neural network configuration, the Gaussian function is used as the radial basis function in the conventional example, but in the present invention, the radial basis function f (b, x) as shown in the following (Equation 4) is used. ) Is used. f (b, x) = A / {1 + cosh (bx)} (Equation 4) where A: constant, b: parameter determined by learning rule cosh (bx) = {exp (bx) + exp (-b)
x)} / 2

In the above example, the input vector is two-dimensional and the output vector is one-dimensional, but the input and output dimensions are not limited to these values and may be arbitrary.

FIG. 2 is a circuit diagram showing a hardware configuration of the neuro element of the present invention. This circuit includes a differential amplifier circuit section 11, a bias section 12, and a multiplication circuit section 13. The differential amplifier circuit unit 11 includes a constant voltage source 21, two resistors R _c , and two bipolar transistors Q ₁ and Q ₁ .
_{It has two} , two variable resistors R _E, and a constant current source 22.
The bias unit 12 also has two power supplies 23 for applying a bias voltage and an input signal source 24. Such a circuit configuration example is known. The transistors Q ₁ and Q
₂ may be a MOS transistor.

The collector of the transistor Q ₁ is connected to the constant voltage source 21 via one resistor R _c . The base of the transistor Q ₁ is connected to a series circuit of the input signal source 24 and one power supply 23 whose one end is grounded. The emitter of the transistor Q ₁ is connected to the constant current source 22 whose one end is grounded through one variable resistor R _E. The collector of the transistor Q ₂ has a constant voltage source 21 via the other resistor R _c.
Connected to The base of the transistor Q ₂ is connected to the other power supply 23 whose one end is grounded. The emitter of the transistor Q ₂ is connected to the constant current source 22 via the other variable resistor R _E. Both of these transistors Q ₁ ,
The characteristics of Q ₂ are the same. Both variable resistors R _E are variable resistors whose resistance value can be adjusted according to a control voltage from the outside (not shown).

Each power supply 23 sets the operating voltage of the circuit.
A constant bias voltage V_BIASIs applied. Also type
The signal source 24 is an input signal as a time-varying input signal.
Pressure v _inIs applied. The two input terminals of the multiplication circuit unit 13 are
Both transistors Q₁, Q_TwoConnect to each collector of
Have been. That is, both transistors Q₁, Q_TwoCollection of
Current I₁, I_TwoThe collector voltage generated by
It is an input of the path unit 13, and the multiplication circuit unit 13
Calculate the product of voltage and output the product. Where both tran
Jista Q₁, Q_TwoHave the same on-resistance and both variable resistors R_E
If the resistance values of the
Force is collector current I₁, I_TwoProportional to the product of

By the way, in the circuit shown in FIG. 2, when the value of both variable resistors R _E is 0, the transistors Q ₁ and Q _{2 are}
The collector currents I ₁ and I ₂ flowing in the
Integrated Circuit Engineering (2) ”(Corona Publishing Co., Ltd. Yanai, Nagata) 47
As shown on the page, the following (Equation 5), (Equation 6)
Becomes However, in (Equation 5) and (Equation 6), α is the current amplification factor, I _EE is the current value of the constant current source 22, q is the charge amount of electrons, k is the Boltzmann constant, and T is the temperature.

[0021]

(Equation 2)

The input voltage v _in is a voltage proportional to the value shown in the following (formula 7) when the first intermediate node 2a in the neural network shown in FIG. 1 is taken as an example.

[0023]

(Equation 3)

FIG. 3 is a block diagram showing a configuration of a circuit for generating v _in which is an input signal. The configuration example shown in FIG. 3 has n parameters t [1] [1], ..., T [1].
This shows a general generation circuit that inputs [n] and generates v _in . For example, when generating v _in proportional to the value of (Equation 7), n = 2.

The v _in generation circuit shown _in FIG. 3 has n subtractors.
It has 31 and n squarers 32, a summer 33 and a square root calculator 34. The i (1 ≦ i ≦ n) th subtractor 31 receives the input value in
The difference between [1] and the parameter t [1] [i] is obtained, and the difference is output to the corresponding i-th squarer 32. i-th 2
The multiplier 32 obtains the squared value of the input difference and outputs the squared value to the summer 33. The adder 33 adds the squared values from all the squarers 32 and outputs the added value to the square root calculator 34. The square root calculator 34 obtains the value of the square root of the sum value from the adder 33, and the input voltage v _in proportional to the square root value.
Is output.

Based on the above (formula 5) and (formula 6), I ₁ ,
When the product of I ₂ is calculated, the multiplication value I ₁ × I ₂ is as shown in (Equation 8) below.

[0027]

(Equation 4)

FIG. 4 shows the relationship of the above (formula 8) with v on the horizontal axis.
₃ is a graph in which I ₁ and I ₂ are plotted on the vertical axis and _in . The graph is symmetric about the vertical axis, ie v _in = 0, and v _in
= Maximum at 0 take (αI _EE) ^2/4.

Here, when the resistance value of the variable resistor R _E is increased from 0, the shape of the graph gradually expands as shown by the broken line in FIG. This is the same as the above (Equation 8).
The same effect as the case where the parameter b is introduced into the equation (9) below is obtained.

[0030]

(Equation 5)

In this (Equation 9), since both α and I _EE are constant values, the numerator value of (Equation 9) is a constant, and the values of I ₁ and I ₂ are the above-mentioned (Equation 4). Equivalent to. Also, the collector currents I ₁ and I of both transistors Q ₁ and Q ₂ are
An output proportional to the product of ₂ is obtained by the multiplication circuit unit 13.
Therefore, by using the circuit configuration as shown in FIG.
It is possible to realize a neuro element using the radial basis function f (b, x) shown in (Equation 4). In this case, the parameter b of the radial basis function shown in (Equation 4) can be changed by changing the resistance value of the variable resistor R _{E in} the circuit shown in FIG.

FIG. 5 is another circuit diagram showing the hardware configuration of the neuro element of the present invention. This is a circuit in which both variable resistors R _E of FIG. 2 are removed and a variable resistor R _B is attached to the bases of both transistors Q ₁ and Q ₂ . Both variable resistors R _B
By changing, it is possible to obtain the same effect as the circuit of FIG.

As described above, in the present invention, the radial basis function shown in (Equation 4) can be realized only by the circuit of FIG. 2 having the differential amplifier, the multiplier, etc. which can be easily manufactured by the integrated circuit. it can.

In the neuro element using the Gaussian function as the radial basis function, the above-mentioned document “A Gaussian Synapse Cir” is used.
As shown in "Cuit For Analog VLSI Neural Networks", the gate width and gate length of the transistor must be changed in order to change the half-value width of the Gaussian function. Since the half-width is fixed and cannot be changed later, in the neuro element of the present invention, the control voltage applied from the outside to the variable resistance R _E (emitter resistance of the transistor) is changed. By adjusting the magnitude of the resistance value, an arbitrary half width can be obtained for the radial basis function shown in (Equation 4).

[0035]

As described above in detail, since the neuro element of the present invention is configured to include the differential amplifier and the multiplier that multiplies two outputs obtained from the differential amplifier, the radial basis A neural network using a function can be realized by hardware having a simple structure, and a neuro element having a radial basis function can be easily manufactured by, for example, a semiconductor integrated circuit.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a configuration of a neural network using a radial basis function.

FIG. 2 is a circuit diagram showing a hardware configuration of a neuro element of the present invention.

FIG. 3 is a block diagram showing a configuration of a circuit that generates an input voltage v _in .

FIG. 4 is a graph showing a relationship between an input voltage v _in and a multiplication value I ₁ · I _{2 of} collector currents I ₁ and I ₂ .

FIG. 5 is a circuit diagram showing a hardware configuration of the neuro element of the present invention.

[Explanation of symbols]

1a first input node 1b second input node 2a first intermediate node 2b the second intermediate node 3 output node 11 the differential amplifier circuit 12 bias unit 13 multiplying circuit Q _1, Q ₂ bipolar transistor R _E, R _B variable resistor

Claims (2)

[Claims] 1. A neuro element for constructing a neural network using a radial basis function, which has two transistors, and inputs to a virtual node of the neural network is at least one of the both transistors. And a multiplier for multiplying the outputs of the both transistors obtained from the differential amplifier. 2. The radial basis function is f (b, x) = A
The neuro element according to claim 1, wherein the neuro element is / {1 + cosh (bx)} (where A is a constant and b is a parameter determined by a learning rule).