JPH09166650A - Diagnostic method for skew between signals and semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a diagnostic method in which the time of a diagnosis can be shortened by latching a signal on the other side to be compared with a delayed signal on one side and with a signal before being delayed and judging whether a skew between two signals is within a tolerance or not, on the basis of latched data. SOLUTION: A first delay gate 21 delays a signal A on one side, and a second delay gate 22 delays a signal B on the other side by twice the delay amount of the gate 21. Latch circuits 23, 24 latch the delay signal A' of the gate 21 by the signal B and a delayed signal B'. When the phase difference of the signals A, B is within a tolerance, the signal A' is latched by the signal B and the signal B'. Then, latched data are set respectively to L (a low level) and H (a high level). When the phase difference of the signals A, B is different, the latched data are set both to L or H. Outputs from the latch circuits 23, 24 are input to an OR gate 30 from the exclusive NOR gate 25, and they are ORed so as to be output as an alarm signal ALM from an output terminal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit technique, and more particularly to a technique effectively used for diagnosing skew (phase shift) between signals.

[0002]

2. Description of the Related Art Conventionally, in a system including a plurality of LSIs, when a plurality of signals are transmitted from one LSI to another LSI, a skew (phase shift) between the signals is set within a preset allowable range. It is important to be inside. Therefore, conventionally, a dedicated measuring device such as an oscilloscope is connected to the output terminal of the LSI on the signal transmission side to compare the phases of the output signals to diagnose the skew.

[0003]

In the skew diagnosis method as described above, a high-performance measuring device is required to guarantee the low skew of the system, and it takes a long time to perform the diagnosis, and the It was revealed that there is a problem that it is difficult to improve the measurement accuracy because the measurement error occurs due to the large influence of the jig used at that time.

An object of the present invention is to provide a technique capable of diagnosing skew between signals without using a dedicated measuring device.

Another object of the present invention is to provide a technique for diagnosing skew between signals with less measurement error.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, the present invention delays at least one of the two signals to be compared whether or not there is skew by using an appropriate delay means, and compares the delayed signal with the signal before being delayed. The signal is latched, and it is determined whether or not the skew of the two signals is within the allowable range based on the latched data.

In order to implement the above method, first delay means for delaying the first signal of the first and second signals for comparing whether or not there is skew, and the delay of the first delay means. Second delay means for delaying the second signal having a delay amount larger than the delay amount, and the first delay means delayed by the second signal before the delay.
Latching means for latching the first signal, and second latching means for latching the first signal delayed by the first delay means by the second signal delayed by the second delay means. An inter-signal skew diagnostic circuit comprising a determination means for determining whether the skew of the two signals is within an allowable range based on the latch data of the first latch means and the second latch means. It was done.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. In FIG. 1, 10 is an output circuit provided inside the LSI, 11 is an output terminal for outputting a signal from each output circuit 10 to the outside of the LSI, and 20 is
Although not particularly limited, it is an alarm circuit that detects a phase difference between signals output from two adjacent output circuits 10 and outputs an alarm signal when the phase difference does not fall within a preset range.

The alarm circuit 20 delays one (A) of the signals output from the two output circuits 10.
Delay gate 21, a second delay gate 22 that delays the other signal (B) by twice the delay amount (tpd) of the first delay gate 21 (2tpd), and is delayed by the first delay gate 21. A first latch circuit 23 and a second latch circuit 24 for respectively latching the signal A ′ with the other signal B before delay and the signal B ′ after delay, and output signals of these latch circuits 23, 24. And an exclusive NOR gate 25 that takes the exclusive OR of The delay amount tpd of the first delay gate 21 is set equal to the allowable range of the phase difference between the two signals.

Next, the operation of the alarm circuit 20 will be described with reference to FIG.
This will be described with reference to FIG. Two signals A and B are shown in FIG.
The timing is shown when the phase difference is within the allowable range. When the phase difference between the two signals A and B is “0”, the signal A ′ on the comparison side that has passed through the first delay gate 21 has a delay of tpd with respect to the signal B before the delay on the reference side. . Then, the delayed reference side signal B ′ that has passed through the second delay gate 22 has a delay of tpd with respect to the signal A ′. Therefore, when the phase difference between the two signals A and B is within the allowable range, the signal B before the delay (clock of the latch circuit 23) and the delayed signal B ′ (clock of the latch circuit 24) are the signal A. 'Is the latch circuit 23, 24
Latch data becomes L (low level) and H (high level), respectively.

On the other hand, the comparison side signal A with respect to the reference side signal B
3 is delayed by more than the allowable range, the comparison-side signal A ′ passing through the first delay gate 21 becomes later than the reference-side delayed signal B ′, as shown in FIG. Therefore, at this time, when the signal A ′ is latched in the latch circuits 23 and 24 with the signal B before delay and the signal B ′ after delay, both latch data become L (low level).

The reference side signal B with respect to the comparison side signal A
When the phase is delayed by the allowable range or more, the comparison-side signal A ′ passing through the first delay gate 21 is earlier than the reference-side undelayed signal B as shown in FIG. Therefore, at this time, when the signal A ′ is latched in the latch circuits 23 and 24 by the signal B before delay and the signal B ′ after delay, both latch data become H (high level). Latch circuit 2
Table 1 shows the states of the 3, 24 latches.

[0016]

[Table 1]

As a result, from the exclusive NOR gate 25 which receives the outputs of the latch circuits 23 and 24 as an input, when the phase difference between the two signals A and B is within the allowable range, it becomes a low level and the phase difference. It can be seen that when is out of the allowable range, a high level signal is output.
Further, in this embodiment, the signals output from the exclusive NOR gates 25 of the plurality of alarm circuits 20 provided inside the LSI are put into the OR gate 30 and their ORs are taken to generate an alarm from a common output terminal. Signal A
It is configured to output as LM. This makes it possible to easily obtain a diagnostic result of signal-to-signal skew without connecting a dedicated measuring device to the outside.

Next, another embodiment of the alarm circuit 20 will be described with reference to FIGS. The alarm circuit of this embodiment, as shown in FIG. 5, is a one-shot based on the signals A and B, and set / reset type flip-flops FF1 and FF2 whose input signals are signals A and B from two output circuits. It is composed of a pulse generation circuit PGT that generates a pulse, and latch circuits LAT1 and LAT2 that latch the output signals of the flip-flops FF1 and FF2 by the pulse from the pulse generation circuit. The flip-flops FF1 and FF2 have the same configuration, and one (F
F1) has a delay gate DLY1 on the input side of the signal B, and the other (FF2) has a delay gate DL on the input side of the signal A.
By providing Y2, the initial state is set to be symmetric, and the flip-flop FF1 is set.
Is supplied to the latch circuits LAT1 and LAT2, and the non-inverted output signal is supplied to the latch circuits LAT1 and LAT2 from the FF2.

Now, the operation of the alarm circuit 20 will be described with reference to FIGS. In FIG. 6, two signals A,
The timing when the phase difference of B is "0" is shown. In the RS flip-flops FF1 and FF2, the output level is determined by the signal that comes in later. 2
When the phase difference between the two signals A and B is “0”, the delay gate D
The signal b after passing through LY1 has a delay of tpd with respect to the other signal a (= A). Therefore, if the phase difference between the signals A and B is within the allowable range, the signal b is always a
Since it is input later, the output c becomes low level in the flip-flop FF1, and the latch circuit LAT1 latches low level by the one-shot pulse d.
On the flip-flop FF2 side, the delay gate DL
The signal a'after passing Y2 is the other signal b '(= B)
Will have a delay of tpd. Here, since the flip-flop FF2 has an inverted output, the signal a ′ that comes in later becomes a reset signal, and the output of the flip-flop FF2 becomes low level. Therefore, 2
When the phase difference between the two signals A and B is within the allowable range, the one-shot pulse d causes the latch circuit LAT2.
Latches low level. Therefore, the expected output values under normal conditions are both L (low level) as shown in Table 2.

[0020]

[Table 2]

On the other hand, when the phase of the signal A is delayed with respect to the signal B by the allowable range or more, the flip-flop FF
The input signals a, b; a ', b'of 1, FF2 have a relationship as shown in FIG. As shown in the figure, when the phase of the signal A is delayed by more than the allowable range, the signals a and a ′ are b,
It will be input after b '. Therefore, the output c of the flip-flop FF1 is at the high level and the output c'of the FF2 is at the low level, and the data latched by the latch circuits LAT1 and LAT2 by the one-shot pulse d becomes H and L as shown in Table 2.

If the phase of the signal B lags the signal A by more than the allowable range, the flip-flop FF
1, the input signals a and b of FF2; a ′ and b ′ have a relationship as shown in FIG. In this case, the signals b, b'are a,
It will be input after a '. Therefore, the output c of the flip-flop FF1 becomes low level, the output c'of the FF2 becomes high level, and the data latched by the latch circuits LAT1 and LAT2 by the one-shot pulse d becomes L and H as shown in Table 2.

Therefore, the latch circuits LAT1, LAT
If the output of 2 is put into an OR gate, a low level is output when the phase difference between the two signals A and B is within the allowable range, and a high level signal is output when the phase difference is out of the allowable range. Can be made.

In the above embodiment, a specific LSI
However, the present invention is not limited thereto, but the present invention is not limited thereto.
For example, as shown in FIG. 9, signal-to-signal skew in an LSI configured to supply a signal from a signal generation circuit CKG to a plurality of functional blocks BL1, BL2, BL3 in one LSI chip via an amplifier circuit AMP. It can also be applied when diagnosing.

Furthermore, from one LSI to another LS
10 as well as a system for supplying a signal to I.
As shown in, it can also be applied to the case of diagnosing signal-to-signal skew in a system configured to supply signals from a plurality of LSIs to one LSI.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in the above-described embodiment, the skew between the signals output from the two adjacent output circuits is detected, but the skew between the signals output from the output circuits at relatively distant positions is detected. It may be configured. Alternatively, an arbitrary one signal may be used as a reference, and the skew may be diagnosed by detecting the phase difference between the reference signal and the signal output from another output circuit.

[0027]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the skew between the signals can be diagnosed without using a dedicated measuring device, the diagnostic time can be shortened, and it is not necessary to connect the measuring device to the LSI, which results in a measurement error. It is possible to diagnose a small signal skew.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of an inter-signal skew diagnostic circuit according to the present invention,

FIG. 2 is a time chart showing timing when the phase difference between two signals to be compared is within an allowable range,

FIG. 3 is a time chart when the phase of the signal on the comparison side lags behind the phase of the signal on the reference side by an allowable range or more

FIG. 4 is a time chart in the case where the phase of the reference side signal lags behind the phase of the comparison side signal by an allowable range or more,

FIG. 5 is a block diagram showing a second embodiment of an inter-signal skew diagnosis circuit according to the present invention,

FIG. 6 is a time chart showing the timing when the phase difference between two signals to be compared is “0”,

FIG. 7 is a time chart when the phase of one signal lags the phase of the other signal by an allowable range or more;

FIG. 8 is a time chart when the phase of one signal leads the phase of the other signal by an allowable range or more,

FIG. 9 is a block diagram showing an embodiment of a semiconductor integrated circuit including a signal skew diagnostic circuit according to the present invention;

FIG. 10 is a block diagram showing an embodiment when the inter-signal skew diagnosis circuit according to the present invention is applied to a system including a plurality of LSIs.

[Explanation of symbols]

 10 Output Circuit 11 Output Terminal 20 Alarm Circuit 21 First Delay Means 22 Second Delay Means 23, 24 Latch Means 25 Judging Means (Exclusive NOR Gate)

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shuichi Ishii 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center

Claims (6)

[Claims] 1. At least one of the two signals to be compared for skew is delayed by suitable delay means, and the other signal to be compared is latched by the delayed signal and the signal before being delayed. Then, based on the latch data, it is determined whether or not the skew of the two signals is within an allowable range. 2. A first delay means for delaying the first signal of the first and second signals for comparing whether or not there is skew, and a delay amount larger than the delay amount of the first delay means. Second delay means for delaying the second signal, and first latch means for latching the first signal delayed by the first delay means by the second signal before being delayed. Second latch means for latching the first signal delayed by the first delay means by the second signal delayed by the second delay means, the first latch means and the second latch A semiconductor integrated circuit comprising: a signal-to-signal skew diagnostic circuit including a determination unit that determines whether the skew of the two signals is within an allowable range based on the latch data of the unit. 3. A pair of flip-flops each having a first input terminal and a second input terminal, a pair of latch means for respectively latching one output signal and the other inverted output signal of these flip-flops, and said flip-flop. A first input terminal for delaying a signal input to one first input terminal of the
Delay means, a second delay means for delaying a signal inputted to the second input terminal of the other flip-flop, a judging means for judging latch data of the pair of latch means, and a signal to be compared. And a pulse generation circuit for generating a one-shot pulse, and two signals to be compared are input to the first and second input terminals of the pair of flip-flops, respectively, and the pulse generated by the pulse generation circuit is generated. According to the semiconductor integrated circuit, there is provided an inter-signal skew diagnostic circuit configured to latch the output signals of the pair of flip-flops in the pair of latch means. 4. The semiconductor integrated circuit according to claim 2, wherein the determination means is a logic gate circuit which takes an exclusive OR of the output signals of the pair of latch means. 5. A logic gate circuit comprising a plurality of inter-signal skew diagnostic circuits according to claim 2, 3 or 4, and a logical gate circuit for taking the logical sum of the output signals of these diagnostic circuits and an output signal of the logical gate circuit. A semiconductor integrated circuit comprising an output terminal for outputting to the outside. 6. A semiconductor integrated circuit comprising the inter-signal skew diagnosis circuit according to claim 2, and one or more semiconductors which operate by receiving a signal output from the semiconductor integrated circuit. An integrated circuit.