JPH0916640A - Circuit simulator and block relaxation repetitive simulating method - Google Patents

Abstract

PURPOSE: To improve the efficiency of convergence for a block relaxation repetitive simulating method. CONSTITUTION: A net list reading means 4 reads out a net list indicating the connecting relation of elements in an object circuit, a transistor(TR) group extracting means 5 extracts a TR group having a minimum unit function, a circuit dividing means 6 divides the object circuit into plural partial circuits in each TR group, and a signal propagation flow graph extracting means 7 recognizes a signal flow direction from an input terminal up to an output terminal based upon the connecting relation of TR groups. An analyzing means 8 executes the parallel analysis of plural partial circuits by a direct method or a relaxation method and analyzes the whole circuit by an iterative solution method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit simulator and a simulation method, and is particularly suitable for application when a computer is used to perform numerical simulation of a nonlinear large-scale circuit or system such as a large-scale integrated circuit. It is something.

[0002]

2. Description of the Related Art When manufacturing an integrated circuit or the like, it is necessary to sufficiently verify the electrical characteristics thereof, and a numerical simulation of circuit operation by a computer is indispensable. However, as integrated circuits become denser and larger in scale, the time taken to simulate one circuit becomes extremely long. Especially, due to the complicated non-linear characteristics, linearization equations based on Newton's method can be converted directly into LU decomposition methods. It has become time-consuming to solve based on the solution of the normal matrix.

For this reason, the conventional circuit simulator performs parallel processing by using a parallel computer system in which a plurality of processors are connected to each other in order to accurately and quickly simulate a large-scale nonlinear circuit. For example, as shown in FIG. 14, to divide the circuit to be partial circuit i, j, a k, external nodes P _i at the boundary, P _j, P _k to the external node voltages v _i, v _j, v _k And each subcircuit i, j, k
The block relaxation iterative simulation method to analyze was used.

That is, in this block relaxation iterative simulation method, as shown in step S1 of FIG. 15, a target circuit is divided into partial circuits i, j, k, and in step S2, the partial circuits i, j, k are divided. Load, step S
In step 3, the external node voltages v _i , v _j and v _k are set.

Next, as shown in step S4, the analysis of the partial circuits i, j, k is performed in parallel by the processors PE _i , PE _j , PE _k provided corresponding to the partial circuits i, j, k. To do.

Next, as shown in step S5, the external node voltages v _i ′, v _j ′, v _k ′ obtained by the analysis of the partial circuits i, j, k in step S4 are the external node voltages set in step S3. It is determined whether or not the voltages converge to the node voltages v _i , v _j , and v _k, and if they do not converge, the process returns to step S3, and the operations of steps S3 to S5 are repeated until they converge.

Next, the operation of steps S3 to S5 will be described with reference to FIG.
Will be described in more detail with reference to. For the circuit as shown in FIG. 14, a linear simultaneous equation as shown in equation (1) is established.

[0008]

(Equation 1)

[0009] Here, A _i: partial circuit i admittance circuit matrix B _i between the internal nodes of: admittance circuit matrix between internal nodes and external nodes of the partial circuit i C _i: external nodes and internal partial circuit i Admittance circuit matrix between the nodes D: Admittance circuit matrix between external nodes of the external circuit x _i : Internal (node voltage) variable vector of the partial circuit i v: External (node voltage) variable vector b _i : of the partial circuit i Internal (current source) power supply vector d: External (current source) power supply vector.

This equation (1) is developed into the following equations (2) to (6). A ₁ x ₁ + B ₁ v = b ₁ ... (2) Formula A ₂ x ₂ + B ₂ v = b ₂ ... (3) Formula: A _i x _i + B _i v = b _i ... (4 ) _{formula: A n x n + B n} v = b n ··· (5) formula _{Dv = d- (C 1 x 1} + C 2 x 2 + ··· + C n X n) ··· (6) equation first , The external variable vector v in step S100 of FIG.
To the initial value v ₀ .

Next, as shown in steps S101 to S10n, the equations (2) to (5) are analyzed by the processors PE _{1 to} PE _n with respect to the external variable vector v given in step S100. Thus, the internal variable vectors x _{1 to} x n of the respective partial circuits _{1 to n} are obtained. Then, when the internal variable vectors x _{1 to} x _n converge to a predetermined value,
The internal variable vectors x _{1 to} x _n are transmitted to the host computer.

Next, as shown in steps S200 and S210, in the host computer, each of the processors PE _{1 to} PE
Based on the internal variable vectors x _{1 to} x _n transmitted from _n , the external variable vector v is obtained by the analysis of the equation (6). Then, as shown in step S220, it is determined whether or not the external variable vector v has converged.

Next, as shown in step S230, when the obtained external variable vector v is not sufficiently close to the initial value v ₀ , the process returns to step S100 and the obtained external variable vector v is set as the initial value v ₀ . Repeat the process.

[0014]

In the conventional block relaxation iterative simulation method, even if the target circuit to be simulated is the same, the convergence speed of the iteration is high due to the circuit division method and the relaxation iteration variable selection method. It was different. Therefore, in order to perform the block relaxation iterative simulation efficiently in parallel, it is necessary to equalize the block sizes and minimize the communication volume between blocks.

For example, the matrix A to be solved is divided into the form of A = B-C (7). Here, the matrix B is a matrix in which Bx = d (8) can be easily solved, for example, a diagonal matrix or a lower triangular matrix.

A = L + D + U (9) In the Gauss-Jacobi method, B = D and C =-(L
+ U), and in the Gauss-Seidel method, B = (L +
D) and C = -U. L is a lower triangular matrix, D is a diagonal matrix, and U is an upper triangular matrix.

Here, x ^{k + 1} = −B ⁻¹ cx ^k + c ⁻¹ b (10) The condition for the relaxation iteration to converge is that the spectral radius ρ (B ⁻¹ C) <1. It is a formula (11).

Next, let us consider the degree of connection of variables in a two-dimensional matrix.

[0019]

(Equation 2)

In the equation (12), in the Gauss-Seidel method, the spectrum radius ρ (B ^-1 C) is as shown in the equation (13).

[0021]

(Equation 3)

In the equation (13), a ₁₂ and a ₂₁ are a ₁₁
And a ₂₂ are larger than that, it means a tight coupling. Further, when a ₁₂ and a ₂₁ are smaller than a ₁₁ and a ₂₂ , they are loosely coupled.
In particular, when a ₁₂ = 0, ρ (B ⁻¹ C) = 0 and converges once.

Next, the above concept is extended to a block, and the state where the blocks x ₁ , x ₂ and x ₃ are connected as shown in FIG. 17 is considered.

[0024]

(Equation 4)

In equation (14), x ₂ and x ₃ are tightly coupled, so x ₂ and x ₃ are blocked, and the order of variables is changed to equation (15) in order to use the Gauss-Seidel method. Rearrange.

[0026]

(Equation 5)

In equation (15), the blocks of x ₂ and x ₃ ,

[0028]

(Equation 6)

That is, if the equation (16) is solved by solving the direct modulus matrix, the original matrix can be solved by one relaxation iteration. As described above, the variable division method has a great influence on the convergence speed of the relaxation iteration.

However, in the conventional simulation method, although a method of partially optimizing the target circuit has been considered, the circuit division method, the relaxation iterative variable selection method, or the parallel processing efficiency improvement is applied to the entire circuit. From the viewpoint, a simulation method that was systematically performed was not considered.

Therefore, an object of the present invention is to improve the convergence efficiency of the block relaxation iterative simulation method by optimizing the division of the circuit viewed from the entire target circuit and the selection of relaxation variables. Is to provide a method.

[0032]

In order to solve the above-mentioned problems, the order in which a target circuit is divided into a plurality of partial circuits, and the selection of external nodes connecting each divided partial circuit is transmitted to the target circuit. Then, the potential of the external node and the voltage of the internal node of each of the partial circuits are obtained in parallel.

The partial circuits are assigned to a plurality of processors and processed in parallel. In the point / block relaxation method, the potentials of the internal node and the external node are obtained by the LU decomposition method at each step of iteration.

In the relaxation method for solving the external nodal equation, the processing in the processor is performed by the Gauss-Seidel method, and the processing between the processors is performed by the Gauss-Jacobi method. On the other hand, in the block relaxation method, a parallel computer in which a plurality of processors are connected to each other is used to divide a target network into partial circuits connected at external nodes and analyze the system.
Extract the signal propagation flow graph between the circuit groups with the signal input terminal as the start point and the signal output terminal as the end point, follow the signal propagation flow graph with priority in the depth direction to extract the external node, and set the initial potential to the external node. Given the input current to each partial circuit obtained by using the initial potential, each partial circuit is analyzed in parallel by each processor using the direct method, and a procedure for newly obtaining the potential of the external node is performed. Repeat until the change in the potential at the node is below the allowable level.

A signal propagation flow graph between circuit groups having a signal input terminal as a start point and a signal output terminal as an end point is extracted, and a non-connected external node graph leaving only external nodes is extracted from this signal propagation flow graph, Subgraphs with more external nodes than the given number are subdivided to less than a given number, and for each subgraph, iterative solution is performed by incorporating it into the partial circuit that has the same most external nodes as the external nodes that make up the subgraph. .

The target circuit is divided into a plurality of partial circuits, and external nodes are incorporated in the partial circuit having the largest degree of connection. The degree of connection is the ratio of the number of external nodes of the partial circuit to the number of external nodes that match the partial circuit.

The target circuit is divided into a plurality of partial circuits, and the external nodes to which the largest number of partial circuits are connected are incorporated into all the partial circuits to which the external nodes are connected. Signal propagation flow graph extraction means for recognizing the direction of signal flow from the input terminal to the output terminal based on the connection relationship of the transistor groups, and analysis for performing partial circuit analysis based on the output of the signal propagation flow graph extraction means And means.

The analysis means analyzes in parallel by the same number of processors as the partial circuits. An assembling means for incorporating an external node connecting a partial circuit into a partial circuit having the largest degree of connection and an analyzing means for analyzing the partial circuit incorporating the external node by the incorporating means.

[0039]

[Function] By extracting each partial circuit and selecting the external node connecting each divided partial circuit in the order in which the signal is transmitted in the target circuit, the convergence efficiency when analyzing each partial circuit is improved. , The simulation time can be shortened.

By assigning the partial circuits to a plurality of processors and processing them in parallel by the direct method or the relaxation method, the simulation time can be further shortened. In the relaxation method that solves the external nodal equation in the point / block relaxation method, the processing in the processor is performed by the Gauss-Seidel method, and the processing between the processors is performed by the Gauss-Jacobi method, which improves the convergence efficiency and optimizes the parallel processing. Can be achieved at the same time.

In the relaxation block method, a signal input terminal is used in a system having a mechanism for dividing a target circuit network into partial circuits connected at external nodes by using a parallel computer in which a plurality of processors are connected to each other. The signal propagation flow graph between the circuit groups having the start point and the signal output terminal as the end point is extracted, the external node is extracted by tracing the signal propagation flow graph with priority in the depth direction, and the initial potential is given to the external node. Using the input current to each sub-circuit obtained by using the initial potential, each sub-circuit is analyzed in parallel in each processor using the direct method, and the procedure for newly finding the potential of the external nodal is described as follows. Repeat until the change is below the allowable value.

A signal propagation flow graph between circuit groups having a signal input terminal as a start point and a signal output terminal as an end point is extracted, and an unconnected external node graph leaving only external nodes is extracted from this signal propagation flow graph, Subgraphs with more external nodes than the given number are subdivided to less than a given number, and for each subgraph, iterative solution is performed by incorporating it into the partial circuit that has the same most external nodes as the external nodes that make up the subgraph. .

By dividing the target circuit into a plurality of partial circuits and incorporating an external node in the partial circuit having the largest degree of connection, the mutual relationship between the variables in each partial circuit is strengthened, and each partial circuit is analyzed. In this case, the convergence efficiency can be improved.

By setting the connection degree as the ratio of the number of external nodes of the partial circuit and the number of external nodes that match the partial circuit,
The degree of connection can be easily obtained, and the process of incorporating an external node in a partial circuit can be easily performed.

High-speed processing is possible by obtaining the potential of the external node by the LU decomposition method. By dividing the target circuit into multiple partial circuits, and incorporating the external nodes to which the most partial circuits are connected to all the partial circuits to which the external nodes are connected, mutual variables between variables in each partial circuit The relationship can be further strengthened, and the convergence efficiency at the time of analyzing each partial circuit can be improved.

By analyzing the extracted partial circuits based on the direction of signal flow from the input terminal to the output terminal, the convergence efficiency at the time of analyzing each partial circuit is improved and the simulation time is shortened. be able to.

By performing the analysis in parallel with the same number of processors as the partial circuits, it is possible to further shorten the simulation time. By incorporating the external node that connects the partial circuits into the partial circuit with the largest degree of connection and performing the partial circuit analysis, the mutual relationship between the variables in each partial circuit becomes stronger, and when analyzing each partial circuit. The convergence efficiency of can be improved.

The external nodes to which the largest number of partial circuits are connected are incorporated into all the partial circuits to which the external nodes are connected, and the partial circuits are analyzed to determine the mutual relationship between the variables in each partial circuit. Can be made even stronger,
It is possible to improve the convergence efficiency when analyzing each partial circuit.

[0049]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A circuit simulator according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a circuit simulator according to an embodiment of the present invention.

In FIG. 1, the parallel computer 3 includes a plurality of processors PE _{1 to} PE _n connected in a two-dimensional grid. Each processor PE ₁ -PE _n can communicate with any processor PE ₁ -PE _n via the network. Further, each of the processors PE _{1 to} PE _n can send the current operating status to the host computer 1 via the bus 2.

Further, in FIG. 2, reference numeral 4 is a netlist reading means for reading a netlist showing the connection relation of elements of the target circuit, 5 is a transistor group extracting means for extracting a transistor group having a minimum unit function,
6 is a circuit dividing means for dividing the target circuit into the partial circuits of the number of processors PE _{1 to} PE _n of the parallel computer 3 of FIG. 1 in the unit of the transistor group, and 7 is based on the connection relationship of the transistor groups from the input terminals. Signal propagation flow graph extraction means for recognizing the direction of signal flow to the output terminal, and 8 is an analysis means for analyzing partial circuits in parallel and determining convergence.

Next, the operation of the circuit simulator according to the embodiment of the present invention will be described. In FIG. 3, the target circuit to be simulated is composed of, for example, MOS transistors M _{1 to} M ₉ , a resistor R ₁ , capacitors C ₁ and C _{2, and the} like. Read the netlist showing the connection relations of.

Next, the functional group is recognized from the target circuit, and the transistor group extracting means 5 creates the transistor groups TG _{1 to} TG ₃ . In this case, in general, the MOS transistors M _{1 to} M ₉ are divided at the gate input portions to form the transistor groups TG ₁ to TG ₁ .
Creation of TG ₃ is performed. For example, the transistor group TG ₁ includes MOS transistors M ₁ and M ₂ , a resistor R ₁ and a capacitor C ₁ , and the transistor group TG ₂ includes MOS transistors M ₃ , M ₄ and M ₇ ,
The transistor group T is composed of the capacitor C _2.
G ₃ is composed of MOS transistors M ₅ and M ₆ . The transistor groups TG _{1 to} TG ₃ have a minimum unit function such as a logic gate.

Next, in FIG. 4, the circuit dividing means 6 shown in FIG. 2 is used with the transistor groups TG _{1 to} TG ₁₀ as a unit.
By the processor PE _{1 to} PE of the parallel computer 3 of FIG.
_The target circuit is divided into _n sub-circuits CB _{1 to} CB ₄ . At this time, each of the partial circuits CB _{1 to} CB ₄ has a substantially equal size, and the target circuit is divided so that the number of external nodes P _{1 to} P ₅ connecting the partial circuits CB _{1 to} CB ₄ is minimized. To do. For example, the partial circuit CB ₁ is composed of the transistor groups TG _{1 to} TG ₃ , the partial circuit CB ₂ is composed of the transistor groups TG _{4 to} TG ₆ , and the partial circuit CB ₃ is composed of the transistor groups TG ₇ and TG ₈ . The partial circuit CB ₄ is a transistor group TG ₉ ,
It is composed of TG ₁₀ . The external node P ₁ connects the partial circuit CB ₁ and the partial circuit CB _3, and the external node P 1
₂ connects the partial circuit CB ₁ and the partial circuit CB ₂ , the external node P ₃ connects the partial circuit CB ₂ and the partial circuit CB _3, and the external node P ₄ connects the partial circuit CB ₂ and the partial circuit CB ₄ . The external node P ₅ is connected to the partial circuit CB ₃ and the partial circuit C.
It is connected to B ₄ .

Next, each transistor group TG ₁ -T
Regarding G ₁₀ , the gate terminals of the MOS transistors M _{1 to} M ₉ in FIG. 3 are group inputs, the nodes connected to the gate terminals of the other transistor groups TG _{1 to} TG ₁₀ are group outputs, and the signal input terminals 9 and 10 are start points. , Each of the transistor groups TG ₁ having the signal output terminals 11 and 12 as end points
Create a group signal propagation flow graph between ~ TG ₁₀ .

Next, in the group signal propagation flow graph, the external node flag is set for the external node when the circuit division is performed. Then, the signal propagation flow extracting means 7 in FIG. 2 traces the external node flag to obtain necessary information such as the connection and disconnection state of the external node and the signal propagation order.

For example, in the signal propagation flow graph shown in FIG. 5, when the blocks B _{0 to} B ₇ are connected by the external nodes x _{1 to} x ₈ , the signal propagation flow graph is traced with priority in the depth direction, and met. The external nodes x _{1 to} x ₈ are arranged in this order. That is, as shown in FIG. 6, the external nodes x _{1 to} x
_Rearrange the order of ₈ with priority in the depth direction.

FIG. 7 is a flow chart showing a process for rearranging the order of the external nodes x _{1 to} x _{8 in} the depth direction. First, the rearrangement table is initialized in step S10, and the external node of the block B ₀ corresponding to the root of the tree is stacked in the stack register in step S11.

Next, as shown in step S12, if there is a stack in the stack register, the process proceeds to step S13, the external node x ₁ ~x ₈ from the stack register extraction first-in first-out basis, retrieved external nodes x ₁ ~
Register x ₈ in the rearrangement table.

Next, as shown in step S14, if the blocks B _{0 to} B ₇ connected to the external nodes x _{1 to} x ₈ registered in the rearrangement table have external nodes x _{1 to} x ₈ ,
Proceeds to step S15, and registered in the reordering table one of the external nodes x ₁ ~x ₈ of the block B ₀ ~B _7, stacking remaining external nodes x ₁ ~x ₈ in the stack register. Then, the process returns to step S14, the block B ₀ .about.B ₇ for connecting to an external node x ₁ ~x ₈ registered in the reordering table to external nodes x ₁ ~x ₈ is eliminated, repeated operation of step S15.

[0061] On the other hand, in step S14, when the block B ₀ .about.B ₇ for connecting to an external node x ₁ ~x ₈ registered in the reordering table no external node x ₁ ~x _8, the flow returns to step S12. Then, the above operation is repeated until there is no stack in the stack register.

After the above operation is performed, an equation for each of the partial circuits CB _{1 to} CB ₄ according to the block relaxation iterative algorithm is created based on the information from the external node flag of the group signal propagation flow graph. . And FIG.
₁ is loaded into each of the processors PE _{1 to} PE _n of the parallel computer 3 of FIG.

Next, a simulation method according to the first embodiment of the present invention will be described. This first embodiment is called a point / block relaxation simulation, and the convergence efficiency is improved by arranging the external node variables of the external node voltage vector v _{0 in} the depth direction first.

When the point / block relaxation simulation is performed, the circuit is divided and the divided nodes, that is, the external node variables are collected to form an edged block diagonal (BBD) matrix as shown in FIG. This edged block diagonal (B
The BD) matrix gives an equation for each of the partial circuits CB _{1 to} CB ₄ . In addition, here, the circuit is divided into four,
The case where four processors PE _{1 to} PE ₄ perform processing in parallel has been described.

In FIG. 9, first, as shown in step S20, the external node variables of the external node voltage vector v ₀ are arranged in the depth direction priority in the signal propagation flow graph.

Next, as shown in step S21, a predicted value is given to the external node voltage vector v ₀ . Next, as shown in step S22, the value (1
The equation 9) is solved by the LU decomposition method for each of the partial circuits CB _{1 to} CB ₄ using the processor PE _i (i = 1, 2, 3, 4).

A _i v _i = j _i −B _i v ₀ (i = 1, 2, 3, 4) Equation (19) Next, as shown in step S23, equation (20) is calculated. , And the obtained value is j ₀₀ .

J ₀ −C ₁ v ₁ −C ₂ v ₂ −C ₃ v ₃ −C ₄ v ₄ (20) Equation Next, in step S 24, the processor PE _i (i Equation (21) is assigned to = 1, 2, 3, 4).

D ₀ v ₀ = j ₀₀ Equation (21) Next, as shown in step S 25, each processor PE
Within _i (i = 1, 2, 3, 4), each processor PE _i (i = 1,
Between (2, 3, 4), the equation (22) is solved by the highly parallel Gauss-Jacobi method.

D _0i v _0i = j _0i (i = 1, 2, 3, 4) (22) Next, as shown in step S 26, the obtained external node voltage vector v ₀ ′ is predicted. The above processing is repeated until the _value is sufficiently close to the external nodal voltage vector v ₀ given as a value.

As described above, according to the first embodiment of the present invention, when the external nodal matrix D ₀ is solved, the external nodal variables are arranged in the order in which the signal is transmitted and solved by the Gauss-Seidel method, and the outside thereof is By solving with the Gauss-Jacobi method, both the speed of convergence and the effect of parallel processing can be expected.

Next, a simulation method according to the second embodiment of the present invention will be described. This second embodiment is called block relaxation simulation and is shown in FIG.
As shown in FIG. ₅ , the external node variables v _{01 to} v ₀₄ of the external node voltage vector v ₀ are incorporated into a partial circuit having a high degree of connection to analyze the partial circuit.

The procedure for incorporating the external node variable into the partial circuit will be described below. In step S30 of FIG. 11, the unconnected external node subgraphs EB _{j to} EB of FIG.
_{Take one j + 3} arbitrarily. Here, the unconnected external node subgraphs EB _{j to} EB _{j + 3} are common subcircuits CB.
It is a set of external nodes v _{p to} v _{p + 5} connecting _{i + 1 to} CB _{i + 4} .

Next, in step S31, if there are unconnected external node subgraphs EB _{j to} EB _{j + 3} , step S31
And the extracted unconnected external node subgraph EB _j ~
All partial circuits CB _{i + 1 to} CB _{i + 4} connected to EB _{j + 3}
About, the connection degree is calculated. Here, the connection degree is a ratio between the number of external nodes v _{p to} v _{p + 5} of the partial circuits CB _{i + 1 to} CB _{i + 4} and the number of matching external nodes v _{p to} v _{p + 5} .

Next, the analysis procedure of the partial circuit after incorporating the external node into the partial circuit will be described. In FIG. 13, the external nodes are incorporated into the partial circuit by the procedure of steps S40 to S43, and as shown in FIG. 12, the external node variables v _{01 to} v ₀₁ of the external node voltage vector v _0.
04 is incorporated into the internal node voltages variable vector v ₁ to v ₄ partial circuit CB ₁ to CB _4. Also, the partial circuit CB ₁
To CB ₄ of internal nodes and admittance circuit matrix between the external node B ₁ ~B _4, partial circuit CB ₁ admittance circuit between the external nodes and internal nodes of the to CB ₄ matrix C ₁ -C _4,
The external node matrix D ₀ is incorporated in the admittance circuit matrix A _{1 to} A ₄ between the internal nodes of the partial circuits CB _{1 to} CB ₄ .

Next, as shown in step S44, a predicted value is given to the external node voltage vector v ₀ . Next, as shown in step S45, the value obtained from the determinant of FIG.
3) by using the processor PE _k , the partial circuit CB ₁
Calculate for each CB ₄ .

[0077]

(Equation 7)

Next, as shown in step S46, (2
4) by using the processor PE _k , the partial circuit CB ₁ ~
Solve by the LU decomposition method for each CB ₄ . _{A kk v k = j k '} ··· (24) formula Next, as shown in step S47, the external node voltages vector v _k obtained is close enough to the external node voltages vector v ₀ given as a predicted value The above process is repeated until.

As described above, according to the second embodiment of the present invention, by incorporating the unconnected external node subgraph in the subcircuit having the deepest relation, the mutual relation between the variables in the block becomes strong. The convergence ability of the block relaxation iterative method can be improved.

Next, a simulation method according to the third embodiment of the present invention will be described. This third embodiment is called an overlap block relaxation simulation, in which a subgraph of unconnected external nodes is incorporated into an appropriate subcircuit, and other partial circuits are integrated in the unconnected external node subgraph. The external node variables that are connected the most are overlapped and incorporated into all the connected partial circuits. The analysis of the partial circuit after incorporating the external node variable is performed in the same manner as the block relaxation simulation described above.

As described above, according to the third embodiment of the present invention, the size of each partial circuit increases, but by overlapping the most appropriate external node variable with the partial circuit, the tail non-connected external By incorporating the nodal subgraph into the most related subcircuit, the mutual relation between the variables in the block becomes stronger, and the convergence ability of the block relaxation iterative method can be further enhanced.

[0082]

As described above, according to the present invention,
The block relaxation iterative method by parallel processing is effective for high-speed simulation of large-scale circuits. In the block relaxation iteration, even if the target circuit is the same, the convergence speed greatly differs depending on the circuit division method and the variable separation method.

In the present invention, by extracting the signal propagation flow graph of the circuit and recognizing the situation of the external node graph to be divided, the circuit division and the variable separation are optimally performed from a global perspective, and the block relaxation iteration method is used. The convergence speed can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a circuit simulator according to an embodiment of the present invention.

FIG. 2 is a block diagram showing functions of the circuit simulator according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a transistor group according to an embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a partial circuit according to an embodiment of the present invention.

FIG. 5 is a diagram showing a signal propagation flow graph according to an embodiment of the present invention.

FIG. 6 is a diagram showing the contents of a stack register according to an embodiment of the present invention.

FIG. 7 is a flowchart showing a process of arranging variables based on a signal propagation flow graph according to an embodiment of the present invention.

FIG. 8 is a diagram showing a block diagonal matrix according to the first exemplary embodiment of the present invention.

FIG. 9 is a flowchart showing a simulation method according to the first embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a partial circuit having a non-connected external node according to an embodiment of the present invention.

FIG. 11 is a flowchart showing a procedure for incorporating an unconnected external node subgraph according to the first embodiment of the present invention.

FIG. 12 illustrates a block diagonal matrix according to a second exemplary embodiment of the present invention.

FIG. 13 is a flowchart showing a simulation method according to a second embodiment of the present invention.

FIG. 14 is a block diagram showing a configuration of a conventional partial circuit.

FIG. 15 is a flowchart showing a conventional simulation method.

FIG. 16 is a flowchart showing parallel processing of a conventional simulation method.

FIG. 17 is a diagram showing a combined state of blocks.

[Explanation of symbols]

 1 Host Computer 2 Bus 3 Parallel Computer 4 Netlist Reading Means 5 Transistor Group Extracting Means 6 Circuit Dividing Means 7 Signal Propagation Flow Extracting Means 8 Convergence Determining Means

Claims (9)

[Claims] 1. A system having a mechanism for dividing and analyzing a target circuit network into partial circuits connected at external nodes by using a parallel computer in which a plurality of processors are connected to each other, and applying an initial potential to the external nodes. Then, each processor solves each partial circuit in parallel using the direct method, and using this result, the external node potential equation is assigned to each processor and analyzed in parallel using the relaxation method to calculate the potential of the external node. Updated,
This is a point / block relaxation simulation method that is repeated until the change in this potential falls below the allowable level. 2. An external node variable of an external node potential equation by extracting a signal propagation flow graph between circuit groups having a signal input terminal as a start point and a signal output terminal as an end point, and tracing the signal propagation flow graph preferentially in the depth direction. 2. The point / block relaxation simulation method according to claim 1, further comprising: 3. In the execution of the relaxation method, the processing in the processor is performed by the Gauss-Seidel method,
The point / block relaxation simulation method according to claim 2, wherein the processing between the processors is performed by a Gauss-Jacobi method. 4. A system having a mechanism for dividing and analyzing a target circuit network into partial circuits connected at external nodes using a parallel computer in which a plurality of processors are connected to each other, wherein a signal input terminal is a starting point and a signal is a signal. The signal propagation flow graph between the circuit groups with the output terminal as the end point is extracted, the external node is extracted by tracing the signal propagation flow graph with priority in the depth direction, and the initial potential is given to the external node to set the initial potential. Using the input current to each partial circuit obtained by using each sub-circuit in parallel in each processor using the direct method, the procedure of newly finding the potential of the external node allows the change in the potential of the external node. A block relaxation simulation method characterized by repeating until: 5. A signal propagation flow graph between circuit groups having a signal input terminal as a start point and a signal output terminal as an end point is extracted, and a non-connected external node graph in which only external nodes are left is extracted from this signal propagation flow graph. However, subgraphs with more external nodes than the specified number are subdivided until the number of external nodes is less than the specified value, and for each subgraph, it is repeated by incorporating it into a partial circuit that has the same number of external nodes as the external nodes that make up the subgraph The block relaxation simulation method according to claim 4, wherein the solution is obtained. 6. The potential of the external node and the voltage of the internal node of each of the partial circuits are obtained by incorporating the external node into the partial circuit having the largest degree of connection, and the degree of connection is the number of external nodes of the partial circuit. 6. The block relaxation simulation method according to claim 5, wherein the ratio is the number of external nodes that match the partial circuit. 7. The iterative solution method according to claim 5, wherein in order to perform an overlapping block relaxation simulation method in which variables are overlapped in each partial circuit to increase the convergence speed, an iterative solution is performed. In a subgraph, a method that iteratively solves by incorporating the external node, which is connected to the largest number of partial circuits, among all the external nodes that make up the subgraph, into all the partial circuits connected to the external node. 8. The netlist reading unit according to claim 2, which reads a netlist indicating a connection relationship between elements of a target circuit, a circuit group extracting unit that extracts a circuit group having a function of a minimum unit, and the circuit group. As a unit, a circuit dividing means for dividing the target circuit into a plurality of partial circuits, and a signal propagation flow graph extracting means for recognizing a flowing direction of a signal from an input terminal to an output terminal based on a connection relationship of the circuit groups. , Based on the output of the signal propagation flow graph extraction means,
A circuit simulator comprising: an analyzing unit that analyzes the partial circuits in parallel by the same number of processors as the partial circuits. 9. The netlist reading unit according to claim 5, which reads a netlist indicating a connection relationship between elements of a target circuit, a circuit group extracting unit that extracts a circuit group having a function of a minimum unit, and the circuit group. As a unit, a circuit dividing unit that divides the target circuit into a plurality of partial circuits, an external node that is connected to each partial circuit, an assembling unit that is incorporated into the partial circuit having the largest degree of connection, and an external node that is formed by the assembling unit. A circuit simulator comprising: an analyzing unit that analyzes an incorporated partial circuit.