JPH0916474A - Device and method for controlling input/output - Google Patents

Abstract

PURPOSE: To improve data transfer performance by parallelly operating the input/output operations of a channel adapter module and a device adapter module using a cache memory as much as possible. CONSTITUTION: When a staging amount to the cache memory 44 by the device adapter module 20 in the case of performing mishit in the channel adapter module 16 reaches a fixed amount, the channel adapter module 16 is reactivated and a hash table 58 is set to a hittable state. Since a hit response is obtained as a cache state, the reactivated channel adapter module 16 performs input/ output between a channel device 18 and the cache memory 14, that is cache write or cache read, parallelly to the staging of the device adapter module 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output control device for controlling input / output between a channel of a host computer and a device by using a cache mechanism, and in particular, an asynchronous communication between a channel adapter side and a device adapter side. The present invention relates to an input / output control device for performing input / output control.

[0002]

2. Description of the Related Art Conventionally, as an input / output control device for asynchronously transferring data between a device and a channel via a cache memory, for example, there is one shown in FIG. FIG.
In the magnetic disk controller 1000, the channels 1018-1, 1018 of the host computer 1012 are
-2, channel adapter modules (CA modules) 1016-1 and 1016-2 are provided, and device adapter modules (DA modules) 1020-1 and 1020- are provided for devices 1014 such as magnetic disk devices.
2 are provided.

A cache function engine module (CFE module) 1026 and a resource manager module (RM module) 1022 are provided. The resource manager module 1026 is the job table 10
Cache function engine module 102
6 has a hash table 1058. The memory of each module is configured by the common memory 1028, and in addition to the cache memory 1044, the cache allocation information area 106
It stores 0.

The cache allocation information area 1060 includes channel adapter modules 1016-1 and 1016-2 and device adapter modules 1020-1 and 1020-.
2 becomes the common control information area referred to. Furthermore, each module is connected by a bus, uses the cache memory 1044 using an internal command, manages the data of the device 1014 in track units, and controls the input / output.

The write operation in the conventional device of FIG. 14 will be described. Now I / O from channel unit 1018-1
When the command write is issued, the channel adapter module 1016-1 requests the cache function engine module 1026 to determine the cache state. That is, the device logical address “CCHD” specified by the I / O command write is converted into a hash address through a hash function, and it is searched whether “CCHD” is registered in the hash address of the hash table 1050. Here, CC is a cylinder address, H is a head address, and D is a device number.

When the track data designated by the I / O command from the channel device 1018-1 by referring to the hash table 1050 does not exist in the cache memory 1044, the device adapter 1020-1 operates by a bypass operation that does not operate the cache. The control unit performs a write operation on the device 1014. Further, the read operation of the conventional device is performed by the I signal from the channel unit 1018-1.
When the / O command read is issued and the track data does not exist in the cache memory 1044 and a miss occurs, the read data is transferred to the channel unit 1018-1 after staging from the device 1014 to the cache memory 1044.

[0007]

However, in such a magnetic disk controller in which the channel adapter module and the device adapter module operate asynchronously, the channel adapter module side misses the I / O command. In this case, there is a problem that it is necessary to exchange information with the device adapter module at all times, resulting in a lot of waste in processing.

The present invention has been made in view of the above conventional problems, and effectively utilizes the fact that the channel adapter module and the device adapter module can operate asynchronously, and uses the cache memory for the channel adapter module and the device. It is an object of the present invention to provide an input / output control device and method for improving the data transfer performance by making the input / output operations of the adapter module as parallel as possible.

[0009]

FIG. 1 is a diagram illustrating the principle of the present invention. First, the present invention relates to a channel adapter module (CA module) 16 that is coupled with a channel device 18,
The channel adapter module 1 has a device adapter module (DA module) 20 coupled to the device 14, and a cache function engine module (CFE module; cache control module) 26 that manages the cache memory 44 based on the hash table 56.
6, the input / output control between the channel device 18 and the cache memory 44 and the input / output control between the cache memory 44 and the device 14 by the device adapter module are asynchronously performed via the resource manager module (resource manager module) 22. Targets the input / output control device.

When the track data does not exist in the cache memory 44 in response to the inquiry from the channel adapter module 16, the control unit of the cache function engine module 26 responds with a mishit, and the track data is newly added to the cache memory 44. The storage area is allocated and the information of the storage area is stored in the allocation information area 52 dedicated to the channel adapter module.

In response to an inquiry from the device adapter module 20, track data is stored in the cache memory 4
If it does not exist in the memory area 4, a mishit is responded, a new storage area for track data is further allocated in the cache memory 44, and information on the storage area is stored in the allocation information area 54 dedicated to the device adapter module. When the control unit of the channel adapter module 16 receives a mishit response from the cache function engine module 26, the controller of the channel adapter module 16 requests staging to the device adapter module 20 via the resource manager module 22, disconnects the channel, and disconnects the device during staging. When a restart request from the adapter module 20 is received, the channel adapter 18 is rejoined and the cache function engine module 26 is queried to obtain a hit response and a staging response. Input / output with the channel device 18 is performed in parallel with the staging of the device adapter module 20 while confirming the amount of staged data by referring to the common control information area 56 of the module 20.

When the device adapter module 20 receives a mishit response from the cache function engine module 26 in response to a cache status inquiry based on a staging request, the device adapter module 20 requests the device 14 to read the track data and sends it to the cache memory 44. After staging, when the amount of data due to staging reaches a predetermined value, the channel adapter module 16 is requested to restart via the resource manager module 22.

Here, the device adapter module 20
The control unit notifies the end of staging to the cache function engine module 26 and sets the contents of the hash table 58 corresponding to the track data that has been staged to the hit enable state. The control unit of the channel adapter module 16 also notifies the cache function engine module 26 of the end of input / output with the channel device 18, and the LRU corresponding to the track data that has been input / output.
The link information for LRU control is set in the contents of the table. At this time, when the other track data in the write hit state is evicted, the device adapter module 20 is requested to write the eviction data to the device 14 (write back) via the resource manager module 22.

The channel adapter module 16, the device adapter module 20, the cache function engine module 26 and the resource manager module 22 are
It is connected to the common memory 28 via a bus. The common memory 28 is separated into a basic storage 42 and a cache memory 44, and a channel adapter dedicated allocation information area 52, a device adapter dedicated allocation information area 54, and a CA-DA common control information area 56 are stored in the basic storage 42. .

The cache memory 44 is composed of a non-volatile memory and a volatile memory. The non-volatile memory is used to store write hit track data, and the volatile memory is used to store read hit track data.
The data transfer rate between the device adapter module 20 and the device 14 is sufficiently higher than the data transfer rate between the channel device 18 and the channel adapter module 16. A disk array unit is used as such a device 14. The disk array unit has one disk module connected to multiple ports.
It has a plurality of ranks. The disk array units are connected in two paths via at least two device adapter modules 20.

Further, the disk array unit is composed of a disk array having a plurality of disk drives and a control module, and the control module is provided with a cache mechanism. Further, according to the present invention, input / output control between the channel device 18 and the cache memory 44 by the channel adapter module 16 and input / output control between the cache memory 44 and the device 14 by the device adapter module 20 are performed via the resource manager module 22. And provide an input / output control method that is performed asynchronously. This input / output control method is performed in the following procedure.

In response to an inquiry of the cache status from the channel adapter module 16 based on the input / output request of the channel device 18, the cache function engine module 26 gives a mishit when the track data is not present in the cache memory 44. In response to this, a new track data storage area is further allocated on the cache memory 44, and the information of the storage area is stored in the allocation information area 52 dedicated to the channel adapter.

Upon receiving a mishit response from the cache function engine module 26, the channel adapter module 16 requests the device adapter module 20 for staging via the resource manager module 22 and disconnects the channel. Upon receiving the staging request from the channel adapter module 16 side, the device adapter module 20 inquires of the cache function engine module 26 about the cache state.

A cache function engine module 2 which receives an inquiry from the device adapter module 20.
When the track data does not exist in the cache memory 44, 6 responds to the device adapter module 20 with a mishit, further allocates a new track data storage area in the cache memory 44, and assigns the storage area allocation information to the device. Allocation information area 5 for adapter only
4 is stored.

Cache Function Engine Module 26
The device adapter module 20 receiving the mishit response from the device requests the device 14 to read the track data and stages it in the cache memory 44. When the amount of data due to staging reaches a predetermined value, the device adapter module 20 sends it via the resource manager module 22. It requests the channel adapter module 16 to restart.

The channel adapter module 16 which has received the restart request from the device adapter module 20 side
Re-joins the channel device 18 and inquires of the cache function engine module 26 about the cache state, and when a hit response and a response during staging is obtained, it is staged by referring to the CA-DA common control information area 56. Inputting / outputting with the channel device 18 is performed in parallel with staging of the device adapter module 20 while confirming the data amount.

[0022]

According to such an input / output control device and method of the present invention, an area dedicated to the channel adapter module and an area dedicated to the device adapter module are provided as the cache allocation information areas managed by one job table. Therefore, the channel adapter module and the device adapter module recognize the allocation state of the cache memory for the job without interfering with each other,
Cache operations can be performed in parallel.

When the staging for the device adapter module cache memory is completed, the hash table is set to the hit enable state. For this reason, the restarted channel adapter module obtains a hit response when inquiring about the cache status.
Input / output between the channel device and the cache memory, that is, cache write or cache read can be performed.

Further, since staging is responded at the same time as the hit response, the channel adapter module refers to the staging state for the CA-DA common control information area and confirms that the track data staging has reached a certain amount. Then, cache write and cache read can be performed in parallel with staging.

For this reason, even if a cache miss occurs, high-speed input / output control can be performed in a state close to a mere cache hit by the parallel operation of the channel adapter module and the device adapter module.

[0026]

2 is a block diagram showing an embodiment of an input / output control device of the present invention, and a disk controller is taken as an example of the input / output control device. In FIG. 2, the disk controller 10 includes a channel adapter module 1
6-1 and 16-2 are provided, and channel units 18-1 and 1 of the host computer 12 are provided via the channel bus.
It is connected to 8-2. Also, the disk controller 10
In this embodiment, the disk array units 14-1 and 14-2 are connected as the devices controlled by the above.

Device adapter modules 20-11 and 20-12 are provided for the disk array unit 14-1.
Are provided and are connected via two device buses. Similarly, for the disk array unit 14-2, the device adapter modules 20-21, 20-2
2 are provided and are connected via two device buses. Channel adapters 16-1, 16-2 and device adapters 20-11, 20-12, 20-21, 20-2
A resource manager module 22, a cache function engine module (cache control module) 26, and a common memory 28 are provided between the two.

The resource manager module 22 has a job table 50, and the cache function engine module 26 has a hash table 58 and an LRU (not shown).
Have a table. Each module provided in the disk controller 10 has internal buses 30-1, 30-2, 3
2-1 and 32-2 are connected to each other, and based on the exchange of internal commands, between the channel units 18-1 and 18-2 of the host computer 12 and the disk array units 14-1 and 14-2. Input / output control is performed using a cache memory built in the common memory 28.

FIG. 3 shows the disk array unit 14 of FIG.
-1 is an example. Disk array unit 14-1
Is the disk array control logic 34-1, 3
4-2 and cache mechanisms 36-1 and 36, respectively.
-2 is provided. A disk array 38 is provided under the disk array control logics 34-1 and 34-2.
Is provided.

The disk array 38 has a four-rank configuration of ranks R0 to R3, and six disk drives are provided for each rank. For example, the rank R0 is provided with the disk drives 40-00 to 40-05. The five disk drives 40-00 to 40-05 are connected to the ports P0 to P5 from the disk array control logics 34-1 and 34-2 by two paths.

Similarly, for the remaining ranks R1, R2 and R3, six disk drives 40-
10-40-15, 40-20-20-40-25, 40-3
0-40-35 are provided. Disk drive 40-
For any of ranks R0 to R3 of 00 to 40-35, five disk drives of ports P0 to P4 are used, for example, as a RAID3 or RAID5 disk array, and the disk drives 40-05 provided to the port R5, 40-15, 40-25, 40-35
Is a spare disk drive.

Here, the disk array 38 having a structure of 4 ranks and 6 ports is called one cluster, and in the disk array of FIG. 2, the disk array units 14-1, 1 are used.
4-2 has a two-cluster configuration. The number of cluster configurations of this disk array unit can be set to an appropriate number as needed, and a disk adapter module for two paths may be provided on the disk controller 10 side for each cluster. An example of the disk array unit 14-1 of FIG. 3 is F649 manufactured by Fujitsu Limited.
A 3-disk array device can be used.

FIG. 4 is an explanatory diagram of a memory map of the common memory 28 provided in the disk controller 10 of FIG.
The common memory 28 is composed of a basic storage 42 and a cache memory 44. Common memory 28 is 3
It has a 2-bit address space, 00000000 to 01FFFFFF is allocated to the basic storage 42, and the rest is used as the address space of the cache memory 44.

The cache memory 44 is a non-volatile memory 4
6 and a volatile memory 48. Non-volatile memory 4
The area 6 is, for example, one third of the cache memory 44. The non-volatile memory 46 is used as a storage area for write hit data. Therefore, even if the track data is updated by the cache write in the cache memory 44 and the device power is cut off without being written back to the disk array unit side, the updated track data is stored in the nonvolatile memory 46. It is saved and remains valid even after the power is turned on, and rewriting data can be guaranteed.

The volatile memory 48 is used as a storage area for read hit data. That is, when the track data is staged from the disk array unit on the device side by the read operation by the I / O command from the channel device of the host computer, it is staged in the volatile memory 48. If a write operation is performed by an I / O command from the channel device, volatile memory 4
When the track data stored in 8 is to be rewritten, it is rewritten after the cache block is allocated to the non-volatile memory 46 and transferred to the memory. Of course, the track data may be rewritten in the area of the volatile memory 48 and then transferred to the area of the non-volatile memory.

FIG. 5 is an explanatory diagram of the contents stored in the basic storage 42 of the common memory 28 and the cache blocks in the non-volatile memory 46 and the volatile memory 48 of the cache memory 44. Together, the job table 50 of the resource manager module 22 is shown. And a hash table 58 of the cache function engine module 26.

First, in the job table 50 managed by the resource manager module 22, I from the channel unit 18-1 or 18-2 of the host computer 12 is input.
When the / O command is issued, the job code is registered. Normally, one I / O command is composed of a series of CCW chains, and the job table 50 registers the correspondence relationship of CCW chains corresponding to job codes.

Therefore, the I / O command included in one CCW chain is managed as one job code by the job table 50, and one job code is assigned with a cache block for storing track data in the cache memory 44. Done. Corresponding to the job table 50, in the basic storage 42,
A CA allocation information area 52 for storing cache memory allocation information dedicated to the channel adapter modules 16-1 and 16-2 is provided. In the CA allocation information area 52, the cache address of the cache block allocated corresponding to the job code specified in the job table 50 is registered. Therefore, the channel unit 18-
1 or 18-2, when the I / O command is received, the job code is referred to by recognizing the job code, and the CA allocation information area 52 is referred to by this job code to assign to this job code. It is possible to know the cache address indicating the position of the cache block, that is, the allocation state of the cache memory 44.

Further, in correspondence with the job table 50, the device adapter 20-1 is stored in the basic storage 42.
A DA allocation information area 54 storing allocation information of the cache memories 44 dedicated to 1 to 20-22 is provided. DA
The address of the cache memory 44 of the cache block allocated corresponding to the job code of the job table 50 is also registered in the for-use allocation information area 54.

Further, the basic storage 42 stores CA-DA which stores control information which can be commonly referred to by the channel adapter modules 16-1 and 16-2 and the device adapter modules 20-11 to 20-22.
A common control information area 56 is provided. In the CA-DA common control information area 56, for example, the data amount of staging by the read operation of the disk array unit for the cache block of the assigned cache address is registered.

Therefore, the channel adapter module 1
6-1, 16-2 and device adapter module 20-
11 to 20-22 are CA-DA common control information areas 56.
By referring to, the input / output state of the cache memory 44 operating individually can be recognized.
The hash table 58 managed by the cache function engine module 26 is an address indicating the track data to be cached, for example, the disk array units 14-1 and 14-2 from the host computer 12 side.
C is the cylinder address when is viewed as a logical device
C, head address is H, and device number is D,
The track address is defined by "CCHD".

The cache function engine module 26 obtains a hash address by passing the track address "CCHD" through a hash function, and checks whether or not the obtained hash address exists in the hash table 58. At the time of a miss hit where the hash address does not exist in the hash table 58, the area of the obtained hash address is secured and the track address “CCH
"D" is registered, and at the same time, if it is a write command, the cache block 60 is assigned to the nonvolatile memory 46 of the cache memory 44, and if it is a read command, the cache block 62 is assigned to the volatile memory 48.

As the allocation information of the cache block 60 or 62, the cache address of the allocated cache block is registered in the CA allocation information area 52 when a cache state determination request is issued from the channel adapter module side. On the other hand, if the device adapter module requests the cache status, the cache address of the allocated cache block is registered in the DA allocation information area 54.

In the hash address area of the hash table 58, a flag and pointer registration area is further provided, and the cache area allocated by the hash address is effectively present in the cache memory 44 in the flag area and a cache hit occurs. Set when enabled. Since the track data managed by the hash address is LRU-controlled according to the LRU table (not shown) in the pointer area, pointer information for linking to the LRU table in this LRU control is stored. Specifically, the pointer information for the LRU table is registered so that the most recently referenced hash address will be the head position of the link of LRU control.

When there is no space in the hash table 58 when setting the pointer information for this LRU control,
The oldest cache block that has not been referenced for the longest time at the end of the LRU table will be evicted. When a cache block is flushed, if the flushed cache block is a write block of the non-volatile memory 46, the data is different from the track data on the disk array unit side. The write-back control for writing back the cache block that has been written to the disk array unit is performed.

The nonvolatile memory 46 and the volatile memory 48 of the cache memory 44 of FIG. 5 allocate cache blocks 60 and 62 for storing track data, and the cache blocks 60 and 62 are, for example, 64 KB.
Has the size of. Also, the cache block 60,
62 is divided into sub blocks of 16 KB each. Right
Therefore, the cache blocks 60 and 62 can be input / output to / from the disk array unit in 16 KB block units. On the other hand, the data transfer between the channel adapter modules 16-1 and 16-2 and the channel units 18-1 and 18-2 of the host computer 12 is performed with the host block of 4 KB as the minimum unit.

Here, the channel adapters 16-1, 16-
The data transfer rate on the second side is, for example, 4 Mbps, while the device adapter modules 20-11 to 20-
Disk array units 14-1 and 14-2 by 22
The data transfer rate between and is sufficiently high at 20 Mbps. Since the data transfer rate on the device side is sufficiently high as described above, in the present invention, even when the cache memory 44 becomes a mishit due to an input / output request from the channel unit, the disk array unit 14-
After staging the corresponding track data from the side of 1 and 14-2, cache write or cache read is apparently enabled in the same manner as in the cache hit state.

Moreover, the channel adapter module 16-
1, 16-2 side and device adapter module 20-1
Since 1 to 20-22 side can operate asynchronously,
By performing the input / output control of the track data using the cache memory 44 as parallel processing as possible, the input / output control using the cache memory at a higher speed can be realized.

Next, the disk controller 10 of the present invention.
The input / output control in (1) will be described separately for the write operation and the read operation. FIG. 6 shows the contents of the common memory 28 of the disk controller 10 of FIG. 2 corresponding to FIG. 5, in order to explain the input / output control operation of the disk controller 10, and further includes a channel unit on the left side, a channel adapter module, The case where the input / output control by the device adapter module is assigned by the resource manager module 22 is taken as an example, and the reference numerals are the channel unit 18, the channel adapter module 16, and the device adapter module 20 for simplification. Further, the disk array units 14-1, 14-2
Are simply shown as the device 14.

FIG. 7 is a time chart of the write operation of the disk controller 10 of FIG. First, the channel unit 18 of the host computer 12 is the I / O command
It is assumed that the light 64 is issued. The channel adapter module 16 which has received this I / O command write 64
Notify the resource manager Mojar 22. When the I / command write 64 is the first command of the CCW chain, the resource manager module 22 registers the new job code and its CCW chain relationship in the job table 50.

The channel adapter module 16 is an I / O
Since the logical track address of the device 14 is received by the command write 64, the cache function engine module 26 is requested to determine 6 whether the requested track data exists in the cache memory 44.
Perform Step 6. Here, the track address is a logical track address assigned from the host computer 12 by viewing the device 14 as a logical device, and is “CCHD”.
Given by The cache function engine module 26 that has received the determination request 66 from the channel adapter module 16 obtains the cache address by passing the track address “CCHD” through the cache function, and refers to the hash table 58 with the obtained hash address.

At this time, if the corresponding track address "CCHD" is not registered in the hash table 58 and there is no track data in the cache memory 44,
Respond with a mishit 68. The channel adapter module 16 which has received the response of the miss hit 68 from the cache function engine module 26 makes a staging request 70 for the missed track data to the resource manager module 22. When the staging request 70 is made, the channel adapter module 16 makes the disconnection 65 of the connection with the channel unit 18.

Upon receiving the staging request 70, the resource manager module 22 makes a staging request 72 to the device adapter module 20. The device adapter module 20 that has received the staging request 72
The cache function engine module 26 is requested to determine whether the track data of the designated track address “CCHD” exists in the cache memory 44.

Cache Function Engine Module 26
Obtains the cache address by passing the track address “CCHD” given to the cache determination request 74 through the cache function, and refers to the hash table 58. At this time, since the track address “CCHD” is not registered in the hash table 58, a mishit 78 is returned.

At the same time, the cache function engine module 26 performs a cache allocation process 76 for securing a cache block for storing a track data storage area by staging from the device adapter module 20 and a registration process in the hash table 58. To do. When the cache allocation processing / hash table registration processing 76 is performed, the cache address of the cache block allocated corresponding to the job code is registered in the DA allocation information area 54 as shown in FIG. In this case, since it is a cache write I / O command, the cache block 114 is allocated to the area of the non-volatile memory 46 as shown in FIG.

The device adapter module 20 receiving the response of the mishit 78 from the cache function engine module 26 issues a track data read command 80 to the device 14. In response to this, the track data read operation 82 is performed from the device 14, the device adapter module recognizes the address of the cache block allocated in the cache memory 44 by referring to the DA allocation information area 54, and transfers from the device 14. The staging of the received track data in the cache memory is performed.

In the staging 84 for the cache memory 44, when the staging data amount reaches a predetermined fixed amount, the device adapter module 2
0 requests the resource manager module 22 to restart the channel adapter module 16. Therefore, the resource manager module 22 instructs the channel adapter module 16 to restart 88.

The channel adapter module 16 is recombined with the channel channel unit 18 by restarting 90.
Then, the channel unit 18 issues the I / O command write 92 again. In response to this I / O command write 92, the restarted channel adapter module 16 requests the cache function engine module 26 to determine 94 whether or not track data exists in the cache memory 44. At this time, hash table 5
8 has already been registered in the track address “CCHD” during the cache allocation process 76 prior to the staging process of the device adapter module 20, but since the flag state of the hash table 58 is not in the hit enable state, the track data Respond 96 during hit / staging.

At this time, the cache function engine module 26 executes the cache allocation processing 95, and registers the cache address of the already allocated cache block currently being staged in the DA allocation information area 54. The channel adapter module 16 having received the response of 96 during hit / staging from the cache function engine module 26 refers to the CA-DA common control information area 56, and performs the staging 84 by the device adapter module 20 to execute the cache memory 4
It is determined whether or not the staging data amount for the allocated cache block 4 has reached a predetermined fixed amount.

When the staging data amount reaches a certain amount, the cache address of the cache memory 44 allocated by referring to the DA allocation information area 54 is recognized, and the track data by the write transfer 98 from the channel unit 18 is received. The cache write 100 is performed. In this state, the staging 84 by the device adapter module 20 and the cache write 100 by the channel adapter module 16 are simultaneously performed in parallel to the allocation area of the same cache block allocated to the cache memory 44. That is, a certain amount of staging for the allocated cache block,
For example, when it reaches 16 KB, the cache write by the channel adapter module 16 is started from the head of the staging block.

After the read operation 82 of the device 14 is completed, the staging 8 by the device adapter module 20 is performed.
When 4 ends, cache function engine module 2
6 and the resource manager module 22 are notified of the staging completion 102. End of this staging 102
In response, the cache function engine module 26 sets the flag of the corresponding hash address in the hash table 58 to the hit state flag set 104.
I do.

Further, when the cache write 100 by the channel adapter module 16 is completed by the completion of the write transfer 98 from the channel unit 18, the disconnection 108 is performed in response to the completion 106 in the channel unit 18.
Also, the end 110 is notified to the resource manager module 22 and the cache function engine module 26. The cache function engine module 26, which has received the notification of the end 110, connects the corresponding hash address of the hash table 58 that has been written to the head position of the LRU table for the track link 11 for LRU control.
Do 2

FIG. 9 is a flow chart of the read operation of the disk controller 10 of FIG. In this read operation, the I / O command read 116 is received from the channel unit 18, the cache memory 44 becomes a miss in response to the determination request 118 of the channel adapter module 16, and the device adapter module 20 performs staging. After the channel adapter module 16 is restarted by the restart request 138 when the predetermined value is reached and the cache state is determined, the cache read 152 is performed by the read transfer 150 from the channel device. Therefore, the read operation accompanying the read command is performed by the channel unit 18 and the channel adapter 16.
The write operation is basically the same as that shown in FIG.

Even in the read operation of FIG. 9, the cache read 152 by the restart of the channel adapter module 16 is performed in parallel from the middle of the staging 136 by the device adapter module 20, and the staging at the time of a cache miss is involved. The read operation can be completed faster. FIG. 10 shows a cache block allocation state of the cache memory 44 in the read operation of FIG. 9, and the cache allocation block 166 is secured in the volatile memory 48 provided in the cache memory 44 during the read operation.

Next, the channel adapter module 1 for realizing the write operation of FIG. 7 and the read operation of FIG.
6. The control processing in each of the device adapter module 20 and the cache function engine module 26 will be described. FIG. 11 is a flowchart of the control processing of the channel adapter module 16 of FIG. First, in step S1, it is checked whether or not an I / O command is received from the channel unit 18. If an I / O command is received, in step S2 the cache function engine 2
6 is requested to determine the cache state.

If a hit response is obtained from the cache function engine module 26 in step S3, cache write or read is performed in step S4, and the end processing is performed in step S5. In the case of a mishit, staging is requested to the resource manager module 22 in step S6, and channel coupling is released in step S7.

In this state, the system waits for a restart request from the resource manager module 22 in step S8. When the restart request is received, the channel unit 18 is reconnected in step S9 and the I / O command of the I / O command is received in step S10. After the receipt, the cache function engine module 26 is requested to determine the cache state again in step S11.

When a hit response is obtained in step S12 in response to this determination request, it is checked in step S13 whether staging is in progress. If staging is in progress, the CA-DA common control information area 56 is referred to in step S14, and when a certain amount of staging is reached, step S16.
Perform a cache write or read with, and when finished,
The termination process is performed in step S17, and step S1 is performed again.
Return to

FIG. 12 shows the device adapter module 20.
3 is a flowchart of the control process of FIG. First, step S1
Then, the presence / absence of a staging request from the resource manager module 22 is checked. If there is a staging request, the cache function engine module 26 is requested to determine the cache state in step S2. Then, in step S3, the presence or absence of a hit is checked. If it is a mishit, a read command is issued to the device 14 in step S4, and staging is performed on the cache address recognized by referring to the DA allocation information area 54 in step S5. To do.

Subsequently, in step S6, it is checked whether or not a certain amount of staging is reached. When the certain amount of staging is reached, in step S7, the resource manager module 22 is sent to the channel adapter module 16
Request a restart of. Then, in step S8, it is checked whether or not staging is completed. When staging is completed, the completion is notified to the cache function engine module 26 and the resource manager module 22 in step S7.

FIG. 13 is a flow chart of the control processing of the cache function engine module 26 of FIG. First, in step S1, it is checked whether or not there is a processing request from another module, and if there is a processing request, step S2
Then, it is checked whether or not it is a determination request from the channel adapter module 16. If the determination request is from the channel adapter module 16, the process proceeds to step S3, the hash table is searched, and it is determined in step S4 whether or not there is a hit.

If it is a hit, it is checked in step S15 whether staging is in progress. Since it is not in staging, in step S17 a hit is returned to the channel adapter module to cause cache write or cache read to the cache memory. Step S4
If it is a mishit in step S5, the mishit is returned to the channel adapter module in step S5, the cache memory is allocated in step S6, and the CA allocation information area 52 is allocated with the allocation information, that is, Register the address of the allocated cache block.

On the other hand, if the hash table is hit and the staging is in progress in step S5, this is a determination request from the channel adapter module due to a restart request from the channel device module side, so the process proceeds to step S16. , It will respond to the channel adapter module that it is in a hit state and is in staging.

If the processing request is not the determination request of the channel adapter module in step S2, it is checked in step S8 whether the determination request is from the device adapter module. If the determination request is from the device adapter module 20, the process proceeds to step S9, the hash table 58 is searched, and it is determined in step S10 whether or not there is a hit.

If it is a mishit, step S
In step 11, a response is sent to the device adapter module with a mishit, and in step S12, the cache memory 44 is allocated. When the allocation is completed, DA is calculated in step S13.
The allocation information is registered in the for-use allocation information area 54. Of course, when allocating the cache memory in step S12,
The track data is registered at the hash address obtained by passing the track address “CCHD” through the hash function.

On the other hand, in response to the determination request from the device adapter module 20 in step S10, when the hash table 58 is searched for a hit state, the hit is returned to the device adapter module in step S14. If the content of the processing request is not the determination request from the device adapter module 20 in step S8, it is checked in step S18 whether staging is completed. If it is determined that staging has ended, step S
At 9, the flag of the corresponding hash address in the hash table 58 is set to the hit state.

If the staging is not completed in step S18, it is checked in step S20 whether the cache read or write is completed. If the cache read or the cache write is finished, the hash address which has been accessed is connected to the head position of the LRU table.
Performs link registration of track data for RU control.

Further, the resource manager module 2 of FIG.
In No. 2, the channel adapter registers with the job table 50 when it receives an I / O command, selects a device adapter module when making a staging request, and further receives a restart request, the channel adapter. Overall management of each module such as module selection will be performed.

In the above embodiment, the disk array unit using the magnetic disk drive as the device is taken as an example, but an appropriate direct access device (DA) such as an optical disk drive or a magnetic tape track is used.
SD) can be used. Although one host computer is taken as an example of the host computer on the channel adapter side, input / output control of a multi-computer device connected to a plurality of host computers can be performed by increasing the number of channel adapters. Further, the present invention is not limited by the numerical values shown in the embodiments.

[0080]

As described above, according to the present invention, the area dedicated to the channel adapter module and the area dedicated to the device adapter module are provided as the storage areas of the allocation information of the cache memory managed by one job table. Therefore, the channel adapter module and the device adapter module can recognize the allocation state of the cache memory and perform the cache operation in parallel without mutual interference.

Further, when the cache memory becomes a mishit in response to an input / output request and the device adapter module is staged, the channel adapter module is restarted when the staging amount to the cache memory reaches a certain amount. In addition, the hash table is set to the hit enable state so that the restarted channel adapter module can perform the same cache write or cache read as the cache hit state in parallel with the staging of the device adapter module. By enabling parallel operation of the device adapter module, high-speed I / O control can be performed in the same state as a cache hit even if it is a mishit, and the performance of I / O processing with an external storage device is greatly improved. Improve It is possible.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing an embodiment of an operating environment of the present invention.

FIG. 3 is an explanatory diagram of the disk array unit of FIG.

FIG. 4 is an explanatory diagram of a memory map of the common memory in FIG.

5 is an explanatory diagram of the basic storage and the cache memory of FIG.

FIG. 6 is a block diagram showing the present invention in a functional configuration.

FIG. 7 is a time chart of the write operation of FIG.

8 is an explanatory diagram of cache block allocation in the write operation of FIG. 7.

9 is a time chart of the read operation of FIG.

10 is an explanatory diagram of cache block allocation in the read operation of FIG.

11 is a flowchart of the channel adapter module control process of FIG.

12 is a flowchart of the device adapter module control process of FIG.

13 is a flowchart of the cache function engine module control process of FIG.

FIG. 14 is a block diagram of a conventional device.

[Explanation of symbols]

10: Disk controller (input / output control device) 12: Host computer (upper device) 14: Device 14-1, 14-2: Disk array unit 16, 16-1, 16-2: Channel adapter module (CA module) 18 , 18-1, 18-2: Channel units (channel devices) 20, 20-11, 20-12, 20-21, 20-2
2: Device adapter module (DA module) 22: Resource manager module (RM module) 26: Cache function engine module (CFE module) 28: Common memory 30-1, 30-2, 32-1, 32-2: Internal bus 34-1, 34-2: Disk Array Control Logic 36-1, 36-2: Cache Mechanism 38: Disk Array 40-00-40-35: Disk Drive 42: Basic Storage 44: Cache Memory 46: Nonvolatile Memory 48 : Volatile memory 50: Job table 52: CA dedicated allocation information area 54: DA dedicated allocation information area 56: CA-DA common control information area 58: Hash table 60, 62: Cache block 114, 166: Cache allocation block

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] May 27, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 16

[Correction method] Change

[Correction contents]

[Procedure amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0002

[Correction method] Change

[Correction contents]

[0002]

2. Description of the Related Art Conventionally, as an input / output control device for asynchronously transferring data between a device and a channel via a cache memory, for example, there is one shown in FIG. FIG.
In the magnetic disk control device 1000, the channel unit 1018-1 of the host computer 1012,
1018-2 for channel adapter module (CA
Modules 1016-1 and 1016-2 are provided, and a device adapter module (DA module) 1020-1, 1 is provided for a device 1014 such as a magnetic disk device.
020-2 is provided.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0005

[Correction method] Change

[Correction contents]

The write operation in the conventional device of FIG. 14 will be described. Now I / O from channel unit 1018-1
When the command write is issued, the channel adapter module 1016-1 requests the cache function engine module 1026 to determine the cache state. That is, the device logical address “CCHD” specified by the I / O command write is converted into a hash address through a hash function, and it is searched whether “CCHD” is registered in the hash address of the hash table 1058 . Here, CC is a cylinder address, H is a head address, and D is a device number.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction contents]

When the track data specified by the I / O command from the channel unit 1018-1 by referring to the hash table 1058 does not exist in the cache memory 1044, the device adapter 1020-1 operates by a bypass operation that does not operate the cache. The control unit performs a write operation on the device 1014. In the read operation of the conventional device, when an I / O command read from the channel unit 1018-1 is issued and the track data does not exist in the cache memory 1044 and a miss occurs, the device 1014 causes the cache memory 104 to read.
Channel unit 1018-
Read data is transferred to 1.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0031

[Correction method] Change

[Correction contents]

Similarly, for the remaining ranks R1, R2 and R3, six disk drives 40-
10-40-15, 40-20-20-40-25, 40-3
0-40-35 are provided. Disk drive 40-
For any of ranks R0 to R3 of 00 to 40-35, five disk drives of ports P0 to P4 are used as a disk array of RAID3 or RAID5, for example, and disk drives 40-05 provided in port P5 , 40-15, 40-25, 40-35
Is a spare disk drive.

Claims (19)

[Claims] 1. A channel adapter module connected to a channel device, a device adapter module connected to a device, and a cache control module for managing a cache memory based on a hash table, and between the channel device and the cache memory by the channel adapter module. In the input / output control device for asynchronously performing the input / output control of the device and the input / output control between the cache memory and the device by the device adapter module via the resource manager module, the cache control module includes the channel adapter. When the track data does not exist in the cache memory in response to the inquiry from, a mishit is returned to the channel adapter, and a new track data storage area is allocated in the cache memory. The information in the storage area is stored in the information area dedicated to the channel adapter, and when the track data does not exist in the cache memory in response to the inquiry from the device adapter, a mishit is returned to the device adapter, and the cache memory is further returned. A control unit for newly allocating a storage area for track data and storing information in the storage area in the information area dedicated to the device adapter is provided, and the channel adapter module receives a mishit response from the cache control module. At this time, the device adapter module is requested for staging via the resource manager to disconnect the channel, and when a restart request is received from the device adapter module during staging, the device is reconnected to the channel device and cache When the control module is queried and a hit response and a response during staging are obtained, the input / output with the channel device is performed while referring to the common control information area of the channel adapter module and the device adapter module to confirm the amount of staged data. In parallel with the staging of the device adapter module, the device adapter module requests the device to read track data and receives the cache data when receiving a mishit response from the cache control module. An input / output control device comprising: a staging unit in a memory; and a control unit for requesting a restart of the channel adapter module via the resource manager when a data amount due to the staging reaches a predetermined value. 2. The input / output control device according to claim 1, wherein
The control unit of the device adapter module notifies the cache control module of the end of staging,
An input / output control device that sets the contents of a hash table corresponding to track data that has been staged to a hit possible state. 3. The input / output control device according to claim 1, wherein
The control unit of the channel adapter module notifies the cache control module of the end of the input / output control with the channel device, and sets the link information of the LRU control to the content of the LRU table corresponding to the track data that has been input / output. An input / output control device characterized by the above. 4. The input / output control device according to claim 3,
When setting the link information of the LRU control in the hash table, when the other track data in the write hit state is evicted, the control unit of the cache control module writes the evict data to the device. An input / output control device that requests a device adapter module via the resource manager module. 5. The input / output control device according to claim 1, wherein
The channel adapter module, the device adapter module, the cache control module and the resource manager module are connected to a common memory via a bus, and the common memory is separated into a main storage and a cache memory, and the main storage has a channel. An input / output control device characterized by storing a dedicated allocation information area of an adapter, a dedicated allocation information area of a device adapter, and a common control information area of a channel adapter and a device adapter. 6. The input / output control device according to claim 5,
The cache memory includes a non-volatile memory and a volatile memory, and the non-volatile memory is used for storing write hit track data, and the volatile memory is used for storing read hit track data. I / O controller. 7. The input / output control device according to claim 1, wherein
An input / output control device characterized in that a data transfer rate between the device adapter module and the device is sufficiently higher than a data transfer rate between the channel and the channel adapter module. 8. The input / output control device according to claim 1, wherein
The input / output control device, wherein the device is a disk array unit. 9. The input / output control device according to claim 8, wherein
The input / output control device, wherein the disk array unit is provided with a plurality of ranks, with a disk module connected to a plurality of ports as one rank. 10. The input / output control device according to claim 8, wherein the disk array units are connected by two paths through at least two device adapter modules. 11. The input / output control device according to claim 8, wherein the disk array unit comprises a disk array having a plurality of disk modules and a control module, and the control module has a cache mechanism. Input / output control device characterized by. 12. A channel adapter module connected to a channel device, a device adapter module connected to a device, and a cache control module for managing a cache memory based on a hash table, and between the channel device and the cache memory by the channel adapter module. And an input / output control between the cache memory and the device by the device adapter module are asynchronously performed via a resource manager module. For inquiries about the cache status from the channel adapter module,
When the track data does not exist in the cache memory, the cache control module responds to the channel adapter module with a mishit, further allocates a new track data storage area in the cache memory, and allocates information of the storage area to the channel. Stored in the information area dedicated to the adapter, the channel adapter module, when receiving a mishit response from the cache control module, requests staging to the device adapter module via the resource manager to disconnect the channel, Upon receiving the staging request from the channel adapter module side, the device adapter module inquires of the cache control module about the cache state, and receives an inquiry from the device adapter module. When the track data does not exist in the cache memory, the cache control module responds to the device adapter with a mishit, further allocates a new track data storage area in the cache memory, and allocates the storage area allocation information. The device adapter module, which is stored in the allocation information area dedicated to the device adapter and receives a mishit response from the cache control module, requests the device to read the track data and stages it in the cache memory. When the amount reaches a predetermined value, the channel adapter is requested to restart via the resource manager, and the channel adapter module receiving the restart request from the device adapter module side rejoins the channel device. When a hit response and a response during staging are obtained by inquiring with the cache control module together with the channel device while confirming the amount of staged data by referring to the common control information area of the channel adapter module and the device adapter module. The input / output control method is performed in parallel with the staging of the device adapter module. 13. The input / output control method according to claim 12, wherein when the staging from said device adapter module is completed, said cache control module stores the contents of the hash table corresponding to the track data which has been staged. An input / output control method characterized by setting to a hit enable state. 14. The input / output control method according to claim 12, wherein when the input / output control between the channel adapter module and the channel device is completed, the cache control module is used to complete the input / output. An input / output control method characterized in that link information for LRU control is set in the contents of the LRU table corresponding to data. 15. The input / output control method according to claim 14, wherein when the cache control module sets the link information of LRU control in the hash table, the other track data in a write hit state is expelled. When performing, the input / output control method is characterized in that the device adapter module is requested to write the eviction data to the device via the resource manager module. 16. The input / output control method according to claim 12, wherein the device adapter module, the device adapter module, the cache control module, and the resource manager module are connected to a common memory via a bus, and the common memory is connected to the common memory. Is separated into a main storage and a cache memory, and the channel adapter dedicated allocation information area, the device adapter dedicated allocation information area, the channel adapter and device adapter common control information area, and the cache memory are stored in the main storage. Characteristic input / output control method. 17. The input / output control method according to claim 16, wherein the cache memory is composed of a non-volatile memory and a volatile memory, and the non-volatile memory is used for storing track data which is write hit. An input / output control method, wherein the volatile memory is used to store read hit track data. 18. The input / output control method according to claim 12, wherein a data transfer rate between the device adapter module and the device is set with respect to a data transfer rate between the channel and the channel adapter module. An input / output control device characterized by being made sufficiently high. 19. The input / output control method according to claim 18, wherein the device is a disk array unit.