JPH0916469A - Processor system provided with address assignment and address lock function suited to memory composed of synchronous dram - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a processor system capable of increasing the opportunities of utilizing a low address fixed mode to plural memory banks divided into physical bank groups and constituted of a synchronous DRAM or the like. SOLUTION: The plural memory banks are divided into plural logic groups across the physical bank groups and addresses are assigned by an interleave system for respective logic group units. When a series of requests outputted from respective requesters are provided with the plural requests for accessing the same low address of the same memory bank, the respective requesters request the lock of the low address for the plural requests and the request is stored in an RA management part 78. When the following request supplied from the other requester requests access to the low address other than the locked low address of the memory bank provided with the locked low address, a priority circuit 96 gives the prescribed number of the requests of a lock origin priority over the request and selects them.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor system having a plurality of memory banks each composed of a synchronous dynamic memory (hereinafter simply referred to as a synchronous DRAM or a synchronous memory) or a memory similar thereto.

[0002]

2. Description of the Related Art Conventionally, an SRAM having a short access time has been used for a main memory device which requires high speed and high throughput.
In most cases, (static RAM) was used. The SRAM requires the same time (about ten and several nanoseconds) to access any address in the chip, but if it is a DRAM (dynamic type RAM), it takes one hundred and ten nanoseconds. Thus, the SRAM has a much shorter access time than other memory chips.

However, SRAM is used for other memory chips (D
Since the degree of integration is lower and the chip price is higher than that of RAM) etc., if a large-capacity main memory is configured, the price may be several tens of times higher. In particular, since the main memory of a vector processing type supercomputer is required to have high performance and large capacity, the above problem becomes remarkable.

However, in recent years, various high speed memories have been proposed. For example, high-throughput memory chips called synchronous DRAM have come on the market. For example, "Transistor Technology," 1993, 1
See the January issue, pages 324 to 331 (hereinafter referred to as the first reference). A characteristic of the synchronous DRAM is that a memory storage location is accessed by a row address and a column address. Normally, to access each storage location, a row address RA is applied and then a column address CA is applied ( See FIG. 13A). However, in order to access a plurality of storage locations having the same row address and different column addresses, it is sufficient to apply the row address once and then apply the column addresses sequentially in synchronization with the clock. Therefore, these storage locations can be accessed faster than the normal access method (FIG. 13B).
reference). Hereinafter, this operation will be referred to as a row address fixed mode or a row address fixed and column continuous access mode.

Here, in FIG. 13, a synchronous DRAM is used.
Clock cycle of 15 nanoseconds and row address R
The time from the input of A until the column address CA can be input is 2 clocks, and the time from the input of the column address CA to the first data output (in the case of read) (this is called CAS latency). 2 clocks,
Further, it is assumed that the precharge time required when the row address RA is input again is 2 clocks and the access pitch in the row address fixed mode is 1 data / clock. RAS (in FIG. 13, since RAS is a negative logic operation signal, it is described with an overline.
In the present specification, simply referred to as RAS without overlining) is a row address assert signal,
(In FIG. 13, since CAS is a negative logic operation signal, it is described with an overline, but in this specification, it is simply expressed as CAS without an overline). , RAS, C
Two addresses sequentially supplied to this memory by the trigger of AS are taken in the chip as a row address RA and a column address CA, respectively.

As a memory similar to the synchronous DRAM, there is a DRAM with cache. This is a DRAM and a cache that are configured in the same integrated circuit. The results of research for applying the cached DRAM to the vector type supercomputer are, for example, W. -C. Hsu and J.
E. Smith, "Performance of Cached DRAM Organization
s in Vector Supercomputers, "Proc. of the 20th Ann
ual International Symposium on Computer Architectu
re, pp327-336, IEEE (hereinafter referred to as the second reference)
Is shown in This reference deals with two types of DRAM with cache. According to this document, even in these two types of memory,
It is understood that the same operation as the row address fixed and column address continuous access mode can be performed. In this document, two types of new address allocation are specifically evaluated for use in a computer system composed of a plurality of memory banks and a plurality of vector processing computers.

FIG. 15 shows an example of address allocation by block interleaving, which is one of those address allocations. Addresses starting from "0" are sequentially assigned to memory bank numbers (BK #) "0" to "3" by the interleave method, and addresses "16" to "31" are assigned to the memory bank numbers (BK #) "4". This is a method of allocating to "7" and thereafter for each address "16" to the next four memory banks in an interleaved manner. By performing such address allocation, four blocks capable of reading / writing four data at a time by continuous address access are prepared. With this, up to 4
An opportunity of memory access can be given to one memory access means. FIG. 14 shows an example of address allocation using the most general interleaving method for comparison.

Since a high throughput is required for the main memory of the conventional vector type supercomputer,
In many cases, a main memory is composed of a plurality of memory banks and addresses are assigned to the memory banks by using an interleave method. The interleave method is generally used to increase the memory throughput in continuous access by allocating continuous addresses to different memory banks. Conventionally, various interleave schemes have been proposed or adopted in products. An example of such an interleave method is Japanese Patent Laid-Open No. 5-16575.
No. 16 or corresponding US Pat. No. 5,392,44
3 (hereinafter referred to as the third reference).

[0009]

In the second reference, two address allocations are made by using a computer system in which a plurality of memory banks can be accessed from any of a plurality of computers through an interconnect network as a model. Has been evaluated.

However, in many commercially available vector type supercomputers, as described in the above third reference, the plurality of memory banks constituting the main memory device are arranged in a plurality of physical bank groups. And the processor is coupled to the main memory by the memory controller,
The storage control device has a plurality of priority control circuits respectively provided corresponding to one physical bank group, each priority control circuit, from the plurality of request circuits operating independently of each other in the processor,
A plurality of requests for accessing any of the memory banks in the physical bank group connected to the priority control circuit are supplied in parallel, and each priority control circuit selects one request from the requests.

According to a study by the present inventor, the relationship between a plurality of memory banks and a plurality of request circuits that constitute a main memory in such a super computer is described in Reference 2 above.
Since the block interleave described in the second reference is different from that described in the above, the block interleave described in the second reference is not changed as it is into a plurality of physical bank groups adopted in the conventional vector type supercomputer. It cannot be applied to a main memory device having a memory bank.

Further, according to a study by the present inventor, when a memory having a fixed row address mode, such as the synchronous DRAM or the cache DRAM, is used as a main memory of a computer, a plurality of independent request circuits are provided. Frequently, an access from will sequentially access storage locations having different row addresses in the same memory bank. As a result, the row address to be accessed changes frequently in each memory bank, reducing the opportunity to use the advantage of the row address fixed mode.

Therefore, an object of the present invention is to provide an address allocation suitable for accessing a plurality of memory banks, which are composed of a memory operable in a fixed row address mode and are divided into a plurality of bank groups, in the fixed row address mode. Is to provide a processor system having.

Another object of the present invention is a processor capable of reducing the number of row address changes caused by access from a plurality of request circuits to a plurality of memory banks composed of memories operable in a fixed row address mode. It is to provide a system.

[0015]

In order to achieve the above object, a processor system according to the present invention is provided with M (M is an integer of 2 or more) memory banks, each of which has M (M
Is an integer greater than or equal to 2)
A storage device including a plurality of memory banks, a plurality of request circuits that respectively output a memory access request to the storage device, and a plurality of physical bank groups connected to the storage device and the plurality of request circuits, respectively. Corresponding to one of the plurality of request circuits, which arbitrates a plurality of memory access requests output in parallel from the plurality of request circuits and transfers one of the plurality of memory access requests to a corresponding physical bank group. Each of the memory banks is composed of a memory having a plurality of storage locations accessed by a row address and a column address, the memory having the same row address and different column addresses. The row address is applied once to the group of memory locations, and the column of the group of memory locations is applied. The plurality of memory banks are configured to be continuously accessible by continuously applying a dress, and M memory banks having the same memory bank number in the same physical bank group belong to the same logical bank group. Are divided into N logical bank groups each consisting of M memory banks, each of which is M ×
A plurality of address blocks composed of L (L is an integer of 2 or more) addresses are sequentially allocated to different logical groups, and M × L addresses belonging to each address block are logical groups to which the address blocks are allocated. Are allocated according to an interleaving method to sequentially different M memory banks belonging to
L addresses are assigned to each of the M memory banks belonging to the logical group, and among the plurality of addresses assigned to each memory bank, the L addresses belonging to the same address block have the same row address. It has an address and is allocated to a plurality of storage locations having different column addresses.

In a more desirable aspect of the present invention, the integer L is smaller than the total number of a group of storage locations having the same row address and different column addresses in each memory bank, A group of storage locations having the same row address and different column addresses are assigned a plurality of storage locations to which addresses belonging to the first address block are allocated and addresses belonging to at least one other address block. A plurality of storage locations being stored.

The feature of the present invention described above, that is, having the same row address in each memory bank,
The group of storage locations having different column addresses is the first
Of the memory bank, the memory bank includes a plurality of storage locations assigned addresses belonging to the address block and a plurality of storage locations assigned addresses belonging to at least one other address block. It is also applicable to processor systems that are not divided into groups.

In another desirable mode of the processor system according to the present invention, the priority control circuit includes at least one memory to which access is to be permitted among a plurality of memory access requests output in parallel from the plurality of request circuits. A circuit for selecting an access request, and a plurality of row address storage devices respectively provided corresponding to one of the plurality of memory banks,
Each row address storage device stores the row address of a storage location within its corresponding memory bank accessed by a preceding memory access request that was recently allowed by the selection circuit to access the corresponding memory bank. A row address assigned to a storage location in a memory bank accessed by each of the plurality of memory access requests output in parallel by the plurality of request circuits, and a plurality of row address storage devices,
A detection circuit for detecting a match between row addresses stored in one row address storage device corresponding to the memory bank, and a detection result by the detection circuit for each of the plurality of memory access requests, A circuit for controlling selection by the selection circuit.

More preferably, the control circuit preferentially selects another memory access request for which a match has been detected by the detection circuit, over one memory access request for which a match has not been detected by the detection circuit. And has a circuit for controlling the selection circuit.

More preferably, each request circuit is:
A circuit that sequentially outputs a series of memory access requests, and a lock request that requests to lock one row address in one of the plurality of memory banks, and outputs the lock request after the one memory bank is locked. A lock / unlock request circuit that outputs an unlock request for unlocking the row address of one memory bank, the priority control circuit being included in one of the plurality of request circuits. In response to the lock request output from the lock / unlock request circuit, information indicating that the row address specified by the lock request of the memory bank specified by the lock request is locked by the request circuit is displayed. The memory for storing and responding to an unlock request subsequently output from the lock / unlock request circuit A lock information storage device that stores information indicating that the row address in the link has been unlocked, and each of the plurality of memory access requests output in parallel by the plurality of request circuits is Whether the memory bank to be accessed satisfies the first condition that the memory bank has a row address locked by a request circuit other than the request circuit that issued the memory access request, and When the access request satisfies the first condition, it is determined whether or not the second address that the row address specified by the memory access request matches the row address locked by the other request circuit. , Information stored in the lock information storage device It has a circuit for detecting, depending on the detection result by the detection circuit for each of the memory access request plurality of and a circuit for controlling the selection by the selection circuit by.

More specifically, the control circuit outputs one of the request circuits, and the control circuit detects one of the detection circuits that satisfies the first condition and does not satisfy the second condition. To preferentially select another memory access request output from another request circuit and detected by the detection circuit unless at least one of the first and second conditions is satisfied, rather than the memory access request. A circuit for controlling the selection circuit is included.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION

(1) Outline of Device FIG. 1 shows a main configuration of a vector processor according to the present invention.

This vector processor has an arithmetic unit (AL
U) 1, a vector register unit (VRU) 2 including a plurality of vector registers (not shown), memory access pipelines (PL0, PL1) 3 and 4, a storage control unit (SCU) 5, and a main memory And a device (MS) 6.

Main memory access instructions in the vector processor of this embodiment include a load instruction and a store instruction. The load instruction is an instruction to store vector data from the main storage device 6 into any of the vector registers. The store instruction is an instruction to store vector data in the main storage device 6 from any of the vector registers.

The vector register unit 2 is composed of two vector data control modules (VDM0, VDM1) 7, 8. These execute different vector instructions in parallel. Vector data control module 7 or 8
Are two vector data control units (VDC0,
VDC1 and VDC2, VDC3) 9, 10 or 1
It consists of 1 and 12.

The vector data control modules 7 and 8 are
They are connected to different memory access pipelines 3 and 4, respectively. The vector data control units 9 and 10 (or 11 and 12) respectively respond to the same memory access instruction to access vector data to be accessed designated by the instruction by so-called two-element parallel operation. It outputs an access request. Specifically, the vector data control unit 9 accesses the even-numbered element of the group of the vector data so as to access the leading data of the even-numbered element of the group (leading vector element, here, the 0-th element). The memory access pipe includes an access request including a base address indicating an address of an element), a stride indicating an interval between addresses of consecutive even-numbered vector elements, and a vector length indicating the number of a group of even-numbered vector elements to be accessed. Output to the memory requester 17 in the line 3. Similarly, the vector data control unit 10 sends a memory access request to the memory requester 18 in the memory access pipeline 3 in order to access an odd-numbered element of the group of vector data.
Output to The vector data control units 11 and 12 supply similar access requests to the memory requesters 19 and 20 in the memory access pipeline 4 in response to vector instructions different from the above instructions.

The vector register unit 2 further has a plurality of vector registers (not shown), and stores vector data read from the main storage device 6 by a memory access instruction or vector data to be written in the main storage device 6 in the main storage. Between the device 6 and any of the vector registers, the vector data control module 7 (or 8), the paths 21, 22 (or 23, 24), the requesters 17, 18 (in the memory access pipeline 3 (or 4)). Or 19, 20), paths 25, 26 (or 27, 28), and the main storage controller 5. Each vector register can also be read or written in two elements in parallel so that two elements operate in parallel. Circuit parts related to reading and writing of these vector registers are well known and are not shown for simplification.

Memory access pipeline 3 (or 4)
Requester (RQ0, RQ1 (or RQ2, RQ
3) 17, 18 (or 19, 20) responds to the memory access request from the vector data control unit 9, 10 (or 11, 12) to each of a group of vector elements designated by the respective request. The memory access request is output to the main storage controller 5 via the paths 25 and 26 (or 27 and 28), respectively.

The storage control unit (SCU) 5 carries out contention arbitration between the memory access requests output by the memory requesters 17 to 20, and then the main storage unit (MS).
6 to those memory access requests.

The main memory (MS) 6 is composed of four physical bank groups (RBG0 to RBG3) 33 to 36. Each of the physical bank groups 33 to 36 has four memory banks (BK0 to BK3, BK4 to BK7, B).
K8-BK11, BK12-BK15) 52-55, 5
6 to 59, 60 to 63, and 64 to 67.

Each physical bank group 33 to 36 can process one request in one machine cycle. Therefore, the entire main memory 6 can process four requests in parallel per cycle.

The above device configuration and its operation are the same as those of a known device. In this embodiment, each memory bank is composed of a memory similar to a synchronous DRAM such as a synchronous DRAM or a cache DRAM. Each memory bank stores a plurality of elements of a group of vector elements that can be successively accessed by a memory access request for vector data from the vector data control module 7 or 8, as described later.
Addresses are assigned to each memory bank so that the chances of reading from each memory bank are increased in a row address fixed mode that is characteristic of a synchronous DRAM or the like in which a column address is changed without repeatedly applying a row address RA. .

Further, the storage control unit 5 responds to any memory bank while accessing a group of vector elements by a memory access request from any of the vector data control modules 7 (or 8). When a request is sent from another vector data control module 8 (or 7), the access conflict from these two vector data control modules 7 and 8 is given an opportunity to use the row address fixed mode of the synchronous DRAM. It is configured to arbitrate access requests from these vector data control modules in an increasing manner.

For example, if it is known that any of the vector data control modules, for example 7, will continue to access a row address of a previously accessed memory bank, that vector data control module will be used for that memory bank. The access right from the module 7 is given priority over the access request from the other vector data control module 8. By doing so, the number of times the row address is changed for the memory bank can be reduced, and the throughput of the memory is improved as a whole. However, if a plurality of accesses from the same vector data control module 7 are successively given access rights, another vector data control module 8
Since the access from sank, the number of times the access right is continuously given to the same vector data control module is limited to a certain number or less.

(2) Address allocation In FIG. 2, RBG # indicates the physical bank group number of the physical bank groups 33 to 36 in FIG.
# Indicates the number of each memory bank 52-67 in the physical bank group to which it belongs, BK # indicates the number of each memory bank 52-67 in all the physical bank groups, and LBG # will be described below. , Shows the number of the logical bank group to which each memory bank belongs. In the following description, each physical bank group will be referred to as a physical bank group RB using the number of the physical bank group, for example, “0”.
Sometimes called G0. Each logical bank group also uses the number of that logical bank group, for example 0, to LBG0.
It may be called. The same applies to each memory bank.

A logical bank group is a group of memory banks defined across all physical bank groups. Specifically, the i-th (i = 0, 1, 2, or 3) logical group LBGi is composed of the i-th memory bank of each physical bank group. The memory banks belonging to each logical bank group all belong to different physical bank groups. The number LBG # of the logical bank group to which each memory bank belongs is the memory bank number B in the physical bank group of that memory bank.
Equal to Ka #. Therefore, each memory bank can be specified by the combination of the physical bank group number RBG # and the in-physical memory bank number BKa # or the combination of the physical bank group number RBG # and the logical bank group number LBG #.

The address allocation shown in FIG. 2 is a kind of block interleaving and is realized as follows. A plurality of address blocks each consisting of consecutive 64 addresses are sequentially allocated to different logical groups, and the 64 addresses in each address block are interleaved into four memory banks belonging to the logical group to which the address blocks are allocated. To allocate.
That is, the 64 addresses from the addresses 0 to 63 forming the first address block are set to the memory banks BK0, BK4, B belonging to the logical bank group LBG0.
Allocate to K8 and BK12 by the interleave method. Second
64 to 127 that form the address block of
64 addresses up to logical bank group LBG1
Memory banks BK1, BK5, BK9, BK1 belonging to
Similarly, it is sequentially assigned to 3. 64 addresses from the addresses 128 to 191 forming the third address block are similarly allocated to the memory banks BK2, BK6, BK10, BK14 belonging to the logical bank group LBG2. Address 19 that constitutes the fourth address block
64 addresses 2 to 255 are assigned to the memory banks BK3, BK7, B belonging to the logical bank group LBG3.
Allocate to K11 and BK15 sequentially. Then, the 64 addresses starting from the address 256 forming the next address block are again converted into the logical bank group LBG.
Memory banks BK0, BK4, BK8, BK belonging to 0
Allocate to 12. Subsequent addresses are assigned in the same manner.

Here, each memory bank is composed of one synchronous DRAM, and each storage position in the memory is accessed by a row address RA and a column address CA. The range that the row address RA and the column address CA can take is not limited to a specific value in this embodiment, but here, for the sake of more specific description, the column address CA starts from 0. 512 to 511
Suppose we can take a number of values. In FIG.
RA and CA refer to the row address and column address assigned to the storage location in the memory bank to which each address is assigned. For example, row addresses 0 and column address 0 of four memory banks in the logical bank group LBG0 are assigned to addresses 0 to 3. Similarly, row addresses 0 and column address 1 of four memory banks of the logical bank group LBG0 are allocated to addresses 4 to 7. As can be seen from the figure, addresses 0 to 255 include 16 memory banks in the logical bank groups LBG0 to LBG3.
Row address 0, column address 0 to row address 0, column address 15 are assigned. Similarly, addresses 256 to 2047 are assigned row address 0, column address 16 to row address 0, and column address 511 of 16 memory banks in the logical bank groups LBG0 to LBG3. Further, row addresses 1 and later of these memory banks are assigned to the subsequent addresses 2048 and subsequent addresses.

More generally, assuming that the number of physical bank groups is N and the number of memory banks in the physical bank group is M, a plurality of addresses each consisting of M × L (L is an integer of 2 or more) addresses. Blocks are sequentially assigned to different logical groups, and M × L addresses belonging to each address block are assigned to sequentially different ones of M memory banks belonging to the logical group to which the address block is assigned according to an interleaving method. .

That is, in the N memory banks belonging to the i-th (i = 1, 2, ..., Or M) logical group,
From the ((i-1) + N (j-1)) * M * L + 1) th address to the ((i + N (j-1)) * M * L) th address (j = 1, ...). Of the address blocks are sequentially assigned to different memory banks according to the sequential interleaving method. As a result, L addresses are assigned to each of the M memory banks belonging to each logical group. FIG.
In the example shown in, N, M, and L are equal to 4, 4, and 16, respectively. Of the plurality of addresses assigned to each memory bank, L addresses belonging to the same address block are assigned to a plurality of storage locations having the same row address and different column addresses.

A computer system having a plurality of memory banks divided into a plurality of physical bank groups and having access rights arbitrated by a priority circuit for each physical bank group is shown above. By using the address allocation by block interleaving, it is possible to increase the chance of utilizing the row address fixed mode of the synchronous DRAM.

For example, when one of the vector data control modules 7 (or 8) accesses a series of continuous addresses, for example, a continuous address starting from address 0, the memory banks BK0, BK4, BK8, BK12.
A memory access request is issued only to Since the vector data control module 7 (or 8) operates in element parallel and accesses two addresses in one cycle, requests for addresses 0 and 1 are issued to the memory banks BK0 and BK4 in the first cycle, In the next cycle, the memory banks BK8 and BK12 will have addresses 2, 3
To the memory banks BK0 and BK4 in the next cycle. At this time, it is necessary to first set the row address 0 in the memory bank to which the first four requests are issued, but when the next four requests are issued to these memory banks, the previously set row address is used. Therefore, it is not necessary to newly set the row address 0, and only the column address needs to be set. Therefore, it is possible to use the row address fixed mode in which only the column address is changed and the sequential access is performed without changing the row address.

Further, in this embodiment, the total number L of addresses (equal to 16 in the present example) belonging to the same address block and allocated to the same row address of the same memory bank is the same row address of the same memory bank. It is chosen to be less than the total number of storage locations it has (512 in this example). More preferably, the total number L is selected to be an integer fraction, specifically 1/32, of the total number (512 in this example) of storage locations having the same row address in the same memory bank. As a result, the same row address in each memory bank is assigned to addresses belonging to a plurality of address blocks.

As will be described later, the present embodiment example is configured to operate as follows. When a plurality of requests in the series of memory requests generated by the access request from the vector data module 7 or 8 access the same memory bank, from the time when the memory request that first accesses that memory bank is executed. The memory bank is locked for the series of memory accesses until the memory request that last accesses the memory bank is executed. While the memory bank is locked, memory requests for other vector data modules in that memory bank are de-prioritized for access. As a result, while a plurality of addresses belonging to the locked row address of the memory bank are accessed, the chance of performing the operation in the row address fixed mode for the memory bank is increased.

However, this results in a situation in which such locked memory banks continue to be occupied by the same requestor. Therefore, it is not desirable to process memory access requests from different requesters as evenly as possible.

Addresses belonging to the same memory bank and the same address block are generally likely to be continuously accessed by one requester. Therefore, when multiple addresses to which the same row address is assigned belong to multiple address blocks, the row address is locked for a longer period than when the address of that row address belongs to one address block. Becomes shorter. In this embodiment, while aiming to use the row address fixed mode as frequently as possible,
In order to avoid excessive occupation by a specific requester, it is desirable to select the address block size so that an address belonging to a plurality of address blocks is allocated to one row address.

(3) Requester Referring to FIG. 3, in the request generation unit 300, a group of even-numbered vector elements in the vector data to be accessed given from the vector data control unit 9 via the path 21 is set. Base address, stride,
And the vector length, the addresses of a group of even-numbered vector elements in the main storage device 6 are sequentially calculated, requests including the addresses are sequentially generated at a rate of one every cycle, and stored in the request register 316 via the line 303. To do. The request generated by the request generation unit 300 includes, as shown in the request register 316, a request flag REQ indicating that the request is a valid request, an ST flag indicating whether the request is a request for storing, The number P of the memory access pipeline to which the requester that issued this request belongs
The L #, the memory address, and the store data included in this request when this request is a store request are included. Of these pieces of information, except for the memory access pipeline number PL # and the address, they are given from the corresponding vector data control unit 9, and the requester 17 adds the memory access pipeline number PL # and the address. The memory access pipeline number PL # is
0 and 1 are taken for the memory access pipelines 3 and 4, respectively. Further, the request generation unit 300 sets the element number ELM # indicating the element number of the vector data requested by the corresponding vector data control module 7 by the line 304, Output to 305. This element number ELM # corresponds to the requester 17 for a group of even-numbered vector elements (or a group of odd-numbered vector elements) that are continuously accessed by the requester 17.
The number indicating the number of the request currently being processed in the group of requests output by (1), starting from 0. The internal structure of the request generation unit 300 for generating such a request is publicly known, and a description thereof is omitted here for simplification.

The requester 17 uses the request register 3
Row address lock bit RL as shown in 16
Also, it is characterized in that the row address unlock bit RUL is generated as follows. In the request counting circuit 301, in response to the base address, stride, vector length given via the path 21 and the element number given from the request generation unit 300 via the path 305, the logic accessed by the request currently being processed is accessed. NR0, which is the total number of requests that are currently being processed and the subsequent requests that will be issued consecutively by the requester and that will be issued consecutively by the requester (hereinafter, this is also called the number of consecutive access requests for the same logical bank group). To calculate. For example, the base address is "0", the stride is "2", and the vector length is "3".
2 ", the element number of the request currently being processed is" 0 ", that is, in the case of the first request, the logical bank group (LBG0) accessed by this request has addresses" 0 "," 2 ", Since 32 requests to “4”, ..., “62” access continuously, N
R0 becomes “32”.

In the memory bank counting circuit 302, the path 2
Within the logical bank group accessed by the request currently being processed in response to the base address, stride and vector length via 1 and the element number ELM # being currently processed given from the request generation unit 300 via the path 305. Out of the memory banks belonging to, the total number of memory banks accessed by this request and the subsequent request issued by this requester following this request (hereinafter, this number is also referred to as the number of accessed memory banks in the logical group) NBK To calculate. For example, when the base address is "0", the stride is "2", the vector length is "32", and the number (element number) of the request currently being processed is "0", the logic accessed by this request is shown in FIG. In the bank group (LBG0), all requests access the memory bank BK0 or BK2, so NBK becomes “2”.

Referring to FIG. 16, the RL / RUL bit generation unit 308 receives the above number (NR0, NBK) via the paths 306 and 307, and requests the number register 310 and the memory bank number register 311 respectively.
To hold. Also, the element number (ELM #) currently being processed is received from the request generation unit 300 via the path 304 and held in the element number register 309.

In this circuit, the RA lock bit RL is set to "0" for the last request of the same memory bank in the logical bank group among the requests successively accessing each logical bank group. , The RA unlock bit RUL is set to “1”, the RA lock bit (RL) is set to “1” for all other requests, and the RA unlock bit RUL is set.
The RA lock bit RL and the RA unlock bit are generated for each request so that is set to “0”.

In the present embodiment, when the same memory bank is accessed by a plurality of addresses in a series of addresses output from one requester, it is assumed that those plurality of addresses belong to the same row address. doing. Therefore, this RL / RUL bit generation unit 308
Sets the RA lock bit to 1 for a memory access request other than the last of a plurality of memory access requests that access the same row address, and sets the RA unlock bit RUL to 1 for the last memory access request. ing. If a series of memory access requests output from the same requester access multiple addresses belonging to multiple row addresses in the same memory bank, one of the row addresses in those series of addresses is FIG. 16 may be modified to carry out the processing described above for a plurality of addresses to which it belongs.

Specifically, the comparator 401 has the element number E
It is determined whether the LM # is “0”, that is, the request generated by the request generation unit 300 is the first request. Selector 4 if this is the first request
05, NR0 of the request number register 310 is selected. If the request is not the first request, the variable register 400 is selected.

Further, the comparator 402 uses the selector 4
It is determined whether the output of 05 is the element number ELM # or less. Further, the adder 407 adds the output of the selector 405 and NR0 which is the content of the request number register 310. When the output of the selector 405 is equal to or smaller than the element number ELM #, the selector 406 selects the output of the adder 407, and the output is stored in the variable register 400 by the variable N.
Store as a new value of R. When the output of the selector 405 is larger than the element number ELM #, the selector 406
Causes the output of the selector 405 to be selected.

As a result of the above processing, the variable register NR always holds a number "1" larger than the maximum element number of the requests which successively access the logical bank group accessed by the request currently being processed. To be done.

Further, the subtracter 408 allows the selector 4
From the output of 06 to the content N of the memory bank number register 311
BK is drawn. Element number ELM # in comparator 404
Is greater than or equal to the output of this subtractor. Comparator 403
At, it is determined whether the element number ELM # is smaller than the variable NR. The output of the AND gate 409 which receives the outputs of the two comparators 403 and 404 is output to the line 315 as the RA unlock bit RUL via the RA unlock register 313. Further, the output of the inverter 410 receiving the output of this AND gate is set to the RA lock bit R
Line 3 via RA lock bit register 312 as L
It outputs to 14. As a result, the two comparators 403, 40
When both determinations in 4 are satisfied, the RA lock bit RL becomes "0" and the RA unlock bit RUL becomes "1". In other cases, the RA lock bit RL is "1" and the RA unlock bit RUL is "0".
become.

The request generated by the request generation unit 300 and the RL and RUL generated by the RL / RUL bit generation unit 308 are passed through paths 303, 314 and 31 respectively.
5, and is merged by the request register 316 into a memory access request. Thus, as mentioned above, for each request, the RA lock bits RL, R
The A unlock bit RUL is generated. Requester 1
The same applies to 8 to 20.

(4) Storage Control Unit (SCU) As shown in FIG. 4, the storage control unit 5 has four request buffer units 37-40 having the same structure and four request buffer units 37-40 corresponding to the four requesters 17-20. It is composed of four priority control units (PR0 to PR3) 44 to 47 having the same structure corresponding to the physical bank groups 33 to 36. In FIG. 4, a path for transferring the vector data read from the main memory 6 in response to the load instruction to the vector register unit 2 (FIG. 1) is omitted for simplification.

(4A) Request Buffer Unit In the request buffer unit 37, the address decoding unit 41, as shown in FIG.
Holds the request supplied by the requester 17 via line 25. The address in the request is shown in Figure 2.
Address conversion is performed so that it can be accessed by the address allocation specialized for the synchronous DRAM shown in FIG. Generate request to include. The address in the memory bank consists of a row address RA and a column address CA. The obtained new request is held in the request register 69.

The address before conversion is divided into five fields and converted. In the present embodiment, as can be seen from the address allocation shown in FIG. 2, the physical bank group physical bank number RBG # is determined by the fifth field (lowest field) ADR5 of the address before conversion.
In this embodiment, the physical bank group has four physical banks, and thus the lowest field ADR5 has 2 bits. Bank number BKa in the physical bank group physical bank according to the third field ADR3 of the address
# Is decided. Physical bank group Since the total number of banks in the physical bank is 4, the third address field ADR3 also has 2 bits in this embodiment. As shown in FIG. 2, since the bank number in the physical bank group physical bank changes in a cycle of 64, the total number of bits of the fourth and fifth address fields is 6 bits.
Therefore, the fourth address field ADR4 consists of 4 bits. The column address CA is determined by the second and fourth fields of the address before conversion. In the present embodiment,
As described with reference to FIG. 2, since it is assumed that there are 512 column addresses for the same row address RA, the column address CA is 9 bits. Therefore, the second address field ADR2 consists of 5 bits. The first address field ADR1 before conversion is used as it is as the row address RA. As a result, in this embodiment, the addresses before conversion from 0 to 2047 correspond to the storage position of the row address RA = 0 in any memory bank of any physical bank group physical bank. The column address CA changes from 0 to 511 with respect to these addresses. Address is 204
When the number exceeds 7, the row address increases by 1 and 2048
The row address is incremented by 1 each time the number of rows is exceeded.

Returning to FIG. 4, the request buffer unit 37
Holds the request issued from the requester 17 temporarily, and under the control of the request sending control unit 43, the physical bank group physical bank number RBG # in the request.
The request is sent to one of the priority control units 44 to 47 pointed to by the path via one of the paths 48 to 51. The internal configurations of the request buffer 42 and the request transmission control unit 43 are disclosed in detail in the above-mentioned third reference document. Here, the detailed description is omitted for simplification. The techniques described therein are incorporated herein by reference.

(4B) Priority Control Unit Each of the priority control units 44 to 47 is simultaneously supplied with a maximum of four requests from the request buffer units 37 to 40. That is, the four requests output by the four requesters 17 to 20 in the two memory access pipelines 3 and 4 are simultaneously sent to the priority control units via the four request buffer units 37 to 40. Occurs. When a plurality of requests are received at the same time, each priority control unit arbitrates the memory access conflict among them and sequentially selects the requests, and the priority control unit selects one of the physical bank bank groups 33 to 36. Send those requests one after another.

The present embodiment is characterized in that two requests related to the memory access pipelines 3 and 4 are arbitrated so as to increase the number of times the row address fixed mode, which is a characteristic of the synchronous DRAM, is used. There is. More specifically, for this purpose, a row address lock circuit is provided, and a request from another access pipeline requests another row address of a memory bank having a row address locked by a certain memory access pipeline. When trying to access, another request is prioritized over the request.

Referring to FIG. 6, each priority control unit, eg, 44, includes an RA management unit 78, a bank busy management unit 79, request registers 88 to 91, 98,
And a priority circuit 96. The request registers 88 to 91 are request buffer units 37 to 4 respectively.
In the request register provided corresponding to 0, the RA match bit RM and the RA change prohibition bit RI generated by the RA management unit 78 for the subsequent requests sent from one of the request buffer units 37 to 40, respectively.
And a bank busy bit BB generated for the subsequent request by the bank busy management unit 79 in combination and held. When the request held in one of these request registers 88-91 is not immediately selected by the priority circuit 96, the unselected request is repeated in one of the paths 48-51. The request register is supplied and holds the request repeatedly every cycle. During this period, the RA management unit 78 is
, The RA match bits RM and R depending on the request newly selected by the priority circuit 96.
A new value of the A change prohibition bit RI is determined every cycle. Similarly, the bank busy management unit 79 newly generates a bank busy bit BB for each of those requests.

The RA management unit 78 stores a request that recently accessed the memory bank corresponding to each of the four memory banks in the physical bank bank group corresponding to this priority control unit, and the paths 48 to 51 are stored. Request buffer unit 3 via any one of, for example, 48
Each time a new subsequent request is sent from the device 7, the row address RA of the previous request stored corresponding to the memory bank having the memory bank number BKa # in the physical bank group designated by the subsequent request.
And the row address RA of the subsequent request are compared. If these row addresses match, one of the request registers 88 to 91 corresponding to the request buffer unit 37 that has sent the subsequent request has a value of “1” via the path 80. RA match bit RM with ".

Further, in the RA management section 78, if the two row addresses match as a result of the comparison, and the memory bank is locked by the preceding request, the subsequent request is performed as follows. The value of the RA change prohibition bit RI to be supplied to the request register 88 is set to 1. That is, the RA management unit 78
Is a request for access to a group of even-numbered vector elements issued by any requester in any of the memory access pipelines, eg 4, 4, eg 19, A preceding request that has already been executed accesses an existing memory bank, and a subsequent request of the group of requests that is to be executed will also access that memory bank, and that memory bank When the row address RA specified by these preceding request and the subsequent request for accessing the memory address coincide with each other, the row address is locked with respect to the memory bank. If a row address in a memory bank is locked for a memory access pipeline, in this example 4,
Based on the memory request from another memory access pipeline, in this example 3, a subsequent request to be executed, for example issued by the request buffer 37, will have a different row address in this memory bank. When accessing the storage location, the RA change prohibition bit RI given to this subsequent request is set to "1" in order to prohibit changing the RA for this subsequent request. Details of the RA management unit 78 will be described later.

In the bank busy management section 79, for each memory bank of the corresponding physical bank group, when the bank is in the busy state, the bank busy time BT representing the time expected to be in the busy state continues.
Is stored. When a subsequent request is supplied from one of the paths 48 to 51, for example, 48 as described above, the physical bank group designated by the subsequent request is the memory bank number BKa # in the physical bank.
The bank busy time BT stored in association with the memory bank having the following is referred to, and if the memory bank is busy, one of the paths 84 to 87, in the present example, 84.
A bank busy bit BB having a value of 1 is supplied to one of the request registers 88 to 91, which is 88 in this example, via the.
Details of the bank busy management unit 79 will be described later.

The priority circuit 96 selects one of the four requests in the request registers 88 to 91 every cycle. At this time, the RA match bit RM, the RA change prohibition bit RI, and the bank busy of these requests are set so that the four memory banks in the corresponding physical bank bank group are continuously accessed without changing the row address as much as possible. Select the request using bit BB. Details of the priority circuit 96 will be described later.

The request selected by the priority circuit 96 is set in the request register 98. Among the requests, the column address CA, the row address RA, the request selection success signal SS, and the memory bank number BKa # in the bank group are stored in the main storage device 6 via the paths 99 to 102 and the path 29 that bundles them. Sent. In addition, as described later,
Various signals of this request are also sent to the RA management unit 78 and the bank busy management unit 79.

(4C) Priority Circuit Referring to FIG. 11, in the priority circuit 96, the request registers 231 to 234 receive the requests from the request registers 88 to 91 via the paths 92 to 95, respectively. That is, the request register 23
1 or 232 sequentially holds a group of requests issued from the requesters 17 or 18 in the memory access pipeline 3. Similarly, the request register 233 or 234 sequentially holds a group of requests issued from the requester 19 or 20 in the memory access pipeline 4. A variety of information constituting the request is shown in the request register 231.

The selector 239 uses the request register 2
If both 31 and 232 have valid requests,
Select signal 2 given by the priority register 243
According to 44, either one is selected, and when only one has a valid request, the valid request is selected without depending on the select signal 244 indicated by the priority register 243. Selector 24
Similarly, 0 selects one request from the request registers 233 and 234 according to the value of the priority register 246.

The selector 239 supplies to the priority register 243 via the path 245 a register identification number having a value of 0 or 1 indicating which of the request registers 231 and 232 holds the selected request. . Priority register 243
Selects the value obtained by inverting the register identification number
9 as a select signal via the path 244.
As a result, the selector 239 basically registers the register 231.
And 232 are selected alternately. Other request register 2
33, 234, the selector 240, and the priority register 246 operate in exactly the same manner.

The requests selected by the selectors 239 and 240 are transferred to the request registers 249 and 250 via the paths 241 and 242, respectively. Since the request registers 231 and 232 hold the request from the memory access pipeline 3, and the request registers 233 and 234 hold the request from the memory access pipeline 4, the request register 249.
Holds the selected request from the memory access pipeline 3, and the request register 2
A selected one of the requests from the memory access pipeline 4 is held in 50.

The requests held in the request registers 249 and 250 are sent to the Req conversion circuits 290 and 291 via the paths 251 and 252, respectively. R
The eq conversion circuit 290 sets the request flag Req of the request to 0 when the request sent to the eq conversion circuit 290 is a valid request but the memory bank requested by the request is busy (BB = 1). In the circuit, this invalidates this request. Since the bank requested by this request cannot be executed because it is busy, it is excluded from the selection targets in this priority circuit 96. The same applies to the Req conversion circuit 291.

The switch 253 is used for the request register 2
This is a circuit for selecting one of the two requests held in 49 and 250, and is a PL priority management unit 299.
Is a circuit for giving a select signal 286 for controlling this switch, which is one of the characteristic circuits of this embodiment. The operation conditions for controlling the request selection by the switch 253 by this circuit are as follows.

(1) Among valid requests, a request that increases the number of operations in the row address fixed mode is prioritized over a request that does not.

The condition (1) is specifically set as follows.

(1A) A request for accessing the same row address as the recently accessed row address is given priority over a request for accessing a row address different from the recently accessed row address for each memory bank.

More specifically, the condition (1A) is the following condition.

(1AA) For a memory bank having a row address locked by a memory access request from one memory access pipeline, a request from the other memory access pipeline has a row address different from the locked row address. When accessing an address, the request from the one memory access pipeline is given priority over the request.

More specifically, this condition (1AA) is set as follows.

(1AAA) For a memory bank having a row address locked by a memory access request from one memory access pipeline, a request from the other memory access pipeline has a row address different from that locked row address. When accessing an address, a predetermined number n (n is a plural number) of valid requests from the one memory access pipeline are selected, and then the request from the other memory access pipeline is selected.

(2) Both of the memory access requests from the two memory access pipelines are valid, and the above condition (1) (or more specific condition (1) is satisfied).
When A) to (1AAA)) are not applicable, memory access requests from those memory access pipelines are selected with almost the same priority.

(3) When the memory access request from one memory access pipeline is valid and the memory access request from the other memory access pipeline is invalid, the valid request is the above condition (1) (or When the more specific conditions (1A) to (1AAA)) are not satisfied, the valid request is selected.

(4) An invalid request is not selected. However, if there is no other valid request that can be selected,
An invalid request may be selected.

The operations of the switch 253 and the PL priority management section 299 will be described in detail below. Switch 2
Reference numeral 53 denotes request registers 249 and 25 depending on the select signal from the PL priority management unit 299.
A valid request is selected from either 0, the selected request is sent to the path 97, and the request selection success signal SS indicating that the selection of the valid request is successful and the memory access pipeline of the selected request. The number PL # and PL # are sent to the inter-PL priority management unit 299 via the path 254. In addition, switch 25
3 selects the request registers 249 and 250, respectively, and notifies the selectors 239 and 240 of that fact via the paths 500 and 501, respectively. The request selected by the switch 253 is deleted from the request registers 249 and 250, and the request not selected is directly stored in the request registers 249 and 250.
Is held.

The PL priority management section 299 includes:
Requests are sent from request registers 249 and 250 via lines 258 and 259, respectively. However, the request flag Req in those requests is not sent. Instead, it is sent from Req conversion circuits 290, 291 via lines 292, 293. As shown in FIG. 12, in the inter-PL priority management unit 299, the decoder 257 causes the switch 253 (see FIG. 1) via the path 254.
1) The memory access pipeline number PL # in the selected request given from 1) is decoded, and when this number is 0, 1 is assigned to paths 261 and 262, respectively.
When 0 is output and this number is 1, the paths 261 and 261 are
0 and 1 are output to 62, respectively.

The NOT gate 287 is supplied with the RA match bit RM of the request from the memory access pipeline 3 from the request register 249 via the path 258. Similarly, the NOT gate 288 has a path 259.
RA match bit RM of the request from the memory access pipeline 4 from the request register 250 via
Is given. AND gate 600 is provided with R output from NOT gate 287 and lines 258 and 611.
An L update prohibition signal RI is given. Similarly, the AND gate 601 is supplied with the output of the NOT gate 288 and the RL update prohibition signal RI of the request from the memory access pipeline 4 supplied via the line 259. AN
The D gate 263 has a request flag Req provided via the line 292 by the Req update circuit 290 for the memory access pipeline 3, a request selection success signal SS provided from the switch 253 via the lines 254 and 255, and an AND gate 600. The output 260 and the output 262 of the decoder 257 are input. Similarly, the AND gate 270 has a request flag Req provided via the line 293 by the Req update circuit 291 for the memory access pipeline 4 and a line 25 from the switch 253.
4, the request selection success signal SS, the output 289 of the AND gate 601 and the decoder 25.
7 output 261 is input. The request selection success signal SS and the output 261 of the decoder 257 are input to the AND gate 602. Similarly, the request selection success signal SS and the output 262 of the decoder 257 are input to the AND gate 603.

The counter 265 outputs a request selection success signal SS of 1 and an output 261 of the decoder 257.
Is reset when becomes 1, and AND gate 263
The output 264 of 1 is counted. Similarly, the counter 272 is reset when the request selection success signal SS becomes 1 and the output 262 of the decoder 257 becomes 1, and the output 2 of the AND gate 270 is reset.
The number of times 71 becomes 1 is counted.

The output of the NOT gate 287 is the RA of the request held in the request register 249 of FIG.
If the match bit RM is "0", that is, the RA of the preceding request and the RA of the subsequent request in the register 249 do not match, the AND gate 60
Enter “1” in 0. The output of the AND gate 600 is
It is input to the AND gate 263. Similarly, when the RA match bit RM of the request held in the request register 250 of FIG. 11 is “0”, that is, the NOT gate 288 outputs the RA of the preceding request and the register 2
If the RA of the subsequent request in 50 does not match, “1” is input to the AND gate 601. AND
The output of the gate 601 is input to the AND gate 270. The decoder 257 decodes the memory access pipeline number PL # of the preceding request selected by the switch 253 of FIG. 11 and outputs the result to the paths 261 and 26.
AND gates 602, 270, 263, 60
Enter 3 The output of the AND gate 263 is set in the counter 265, and the AND gate 60 is set.
The output of 2 is input to the reset of the counter 265. The output of the AND gate 270 is input to the set (set) of the counter 272, and the output of the AND gate 603 is input to the reset (reset) of the counter 272.

For example, Req on the path 293 is "1",
When Req on the path 292 is “1” and SS on the path 255 is “1”, RM on the path 258 is “1”, path 2
RM on 59 is “0”, RI on path 259 is “1”,
It is assumed that the RI on the path 258 is “0” and the PL # input to the decoder 257 is “0”.

The fact that PL # is "0" means that switch 2
It indicates that the preceding request selected in 53 is issued from the memory access pipeline 3. In this case, the output 261 of the decoder 257 is 1
Becomes When the RI on the path 259 is "1", it means that any row address of the memory bank in the request register 250 requested by the request from the memory access line 4 is locked. Further, the fact that the RM on the path 259 is “0” indicates that the row address of the request from the memory access pipeline 4 and the locked row address do not match.

The fact that a certain memory bank has a locked row address, as is clear from the definition of the lock in this embodiment, is as follows: (1) A series of memory access from the access pipeline 3. There are multiple memory access requests in the request, (2) Furthermore, the first one of the multiple memory access requests has already been executed,
(3) However, it indicates that the last of those memory access requests has not yet been executed. That is, this memory bank operates in the row address fixed mode in this embodiment. Therefore, when a request from the access pipeline 4 in the request register 250 is allowed to access this memory bank, this memory bank is accessed for this request with a row address different from the row address that has been accessed so far. Will be done.

In other words, this memory bank must newly access another row address after completing the operation in the row address fixed mode. In this example of the embodiment, a request that reduces the number of operations in the row address fixed mode is not selected. From this request, the access from another request, in this example, the memory access request that locks the memory bank, and in this example, 3 is prioritized. In this embodiment, after the predetermined number n of requests from the memory access pipeline 3 are selected, the above-mentioned requests from the memory access request 4 are selected. The selection operation for this will be described later. The output of the AND gate 601 becomes 1 when the request from the memory access pipeline 4 is a non-executed request satisfying the special condition described above. The same applies to the AND gate 600.

The above value n is preferably selected by appropriately measuring the performance so as to increase the overall performance of the processor system. The higher the value, the more chances to operate in fixed row address mode and the performance of the processor system increase, but the period from which the request from one memory access pipeline is not selected increases and the performance decreases relatively. there's a possibility that. However, it is desirable to make it smaller than the total number (16 in the example of FIG. 2) of different column addresses belonging to one row address.

The counter 272 is for counting the number of times the request from the memory access request 3 is continuously selected in such a state. Similarly, the counter 265 is for counting the number of times the request from the memory access pipeline 4 is selected. Under the present assumption, the output 2 of the AND gate 601
89 becomes "1". Eventually, the output 271 of the AND gate 270 becomes "1". As a result, the set input of the counter 272 becomes "1", and the value of the counter 272 is incremented by 1. On the other hand, the output of the AND gate 602 also becomes 1, so the counter 265 is reset.
As described above, in this embodiment, the counters 265 and 27 are used.
When one of the two is counted up, the other is always reset, so that the value of either one is always "0".

The comparator 268 compares the value of the counter 265 with the numerical value "n", and when the coincidence or the disagreement is detected, the comparison results of taking the values 1 and 0 respectively are given by the encoder 27.
7 and NOR gate 279. Comparator 275
Similarly, the counter 272 is compared with the value “n”. As a result, the output of the NOR gate 279 is the counter 26
1 when at least one of the values 5, 272 reaches n
become.

The encoder 277 includes comparators 268 and 27.
The coded output of No. 5 is sent to the selector 285. For example, when the outputs of the comparators 268 and 275 are "1" and "0", respectively, the output of the encoder 277 is "0". When the outputs of the comparators 268 and 275 are "0" and "1", respectively, the output of the encoder 277 is "1". The output of the NOR gate 279 is sent to the selector 285 as a select signal. Selector 28
5 is when the output of the NOR gate 279 is 1, that is, when the output of either of the comparators 268 and 275 becomes 1, that is, when the count value of either of the counters 265 and 272 becomes n. At times, the output of the encoder 277 is selected. Thus, the counter 265 or 2
When the value of 75 reaches n, the signal for selecting a request that was not selected until then is the selector 285.
Generated by

The selector 285 has counters 265 and 27.
When the count value of neither of the two is n, the path 284 is selected. The number of the memory access pipeline is generated in this path as follows.

A switch 253 is connected to the NOT gate 281.
The memory access pipeline number PL # is supplied from (FIG. 11) via paths 256 and 612, and its output is
It is sent to the input "D" of the priority register 283. The enable input “E” of the priority register 283 is connected to the path 25 from the switch 253 (FIG. 11).
The request selection success signal SS is input via 4, 255, and the output of the NOT gate 281 is input to the data input “D” of the priority register 283.
That is, the priority register 283 holds the inverted value of the memory access pipeline number PL # only when the request selection success signal SS is "1".

The AND gate 605 receives the request flag Req supplied via the path 293 and the output of the AND gate 601 inverted by the NOT gate 607. After all, the output of the AND gate 605 is a request in which the request from the memory access pipeline 4 is valid, and the above-mentioned condition (RI = 1, RM = 0) for prohibiting execution is applied to this request. It becomes 1 when it is not established. The selector 609, when the output of the AND gate 605 is “0”, that is,
The request from the access pipeline 4 is invalid (here, the invalid request includes the request invalidated by the Req inverting circuit 290 or 291. The same applies to the following.), Or the valid request When the execution prohibition condition is satisfied, the access pipeline number "0" is selected. Selector 609 is AND
When the output of the gate 605 is "1", that is, the request from the access pipeline 4 is valid,
When the execution prohibition condition is not satisfied, the access pipeline number "1" is selected.

AND gate 604, NOT gate 606
Are AND gate 605 and NOT gate 607, respectively.
Is the same as Therefore, the output of the AND gate 604 is
It becomes 0 when the request from the access pipeline 3 is invalid or valid, and when the execution prohibition condition is satisfied. The output of the AND gate 604 becomes 1 when the request from the access pipeline 3 is valid and the execution prohibition condition is not satisfied. The outputs of the AND gates 604 and 605 are input to the exclusive OR gate 608.
The selector 610 selects the output of the priority register 283 when the output of the exclusive OR gate 608 is 0, and when the output of the exclusive OR gate 608 is 1,
The output of the selector 609 is selected.

The selector 285 determines that the output of the NOR gate 279 is "0", that is, the counters 265 and 272.
If none of these are "n", the selector 6
10 outputs 284 are selected. AND gates 604 and 6
The output of 05 is 1 when both of the two requests are valid and the execution prohibition conditions are not satisfied for the two requests. At this time, the output of the exclusive OR gate 608 becomes 0, and the selector 610 selects the output of the priority register 283. The priority register 283 holds the number of the memory access pipeline which is not the memory access pipeline selected immediately before. Therefore, the inter-PL priority management unit uses the switch 253.
Each time a request is selected by (FIG. 11), the priority between the memory access pipelines is alternately switched every cycle so that the request from the unselected memory access pipeline is selected.
As a result, the opportunities for memory access by the two memory access pipelines are equalized.

One of the outputs of the AND gates 604 and 605 is 0 and the other output is 1 because one of the requests is invalid or valid and the execution prohibition condition is satisfied, and the other request is valid and This is a case where the above execution prohibition condition is not satisfied. In this case, the other request may be selected. For example, when the AND gate 605 is 1 and the AND gate 606 is 0, the request from the memory access pipeline 3 is invalid or valid and the execution prohibition condition is satisfied, and the request from the memory access pipeline 4 is valid. In addition, the above-mentioned execution prohibition condition is not satisfied. In this case, AN
The output 1 of the D gate 605 causes the selector 609 to select 1 as the memory access pipeline number. In this case, the output of the exclusive OR gate 608 is 1, and the selector 610 selects the output 1 of the selector 609. Thus, the memory access pipeline number 1 is selected, and the request from the memory access pipeline 4 is selected. The output of the AND gate 604 is 1,
When the output of the AND gate 605 is 0, the selector 6
Similarly, 10 selects the memory access pipeline number 0.

The outputs of the AND gates 604 and 605 both become 0 when one of the requests is invalid or valid and the execution prohibition condition is satisfied, and the other request is invalid. In the present exemplary embodiment, if two requests are valid and the execution prohibition condition is satisfied, A
The outputs of the ND gates 604 and 605 both become 0,
In the present embodiment, the execution prohibition condition is not satisfied for two requests at the same time as described above, and therefore such a case does not occur. Therefore, A
When the outputs of the ND gates 604 and 605 both become 0, it is not necessary to select any request. In this case, the output of the exclusive OR gate 608 is 1, so the determination circuit 620 determines whether this output is 1 and the outputs of the AND gates 604 and 605 are both 0, which is true. Sometimes switch 2 via line 298
The selection unnecessary signal is sent to 53 (FIG. 11).

Returning to FIG. 11, the switch 253 sets the path 2
According to the number of the memory access pipeline designated by the selection signal given from 86, the request register 24
Select either 9, 250 request and pass 97
To the request register 98 (FIG. 6) via the.
At this time, a circuit (not shown) is added to add a predetermined bank busy time BT indicating the time during which the selected request is occupied by the selected memory to the selected memory. ing.

The physical bank groups 33, 34,
Each time 35 or 36 receives a new request from the priority circuit 96, it looks at the RA lock bit and RA unlock bit in the request, and controls the operation mode of the memory bank requested by the request (FIG. (Not shown). That is, when the RA lock bit is 1, the circuit operates the memory in the row address fixed mode when the memory bank is not already operating in the row address fixed mode, and the request is Execute for memory banks. If the memory bank is already operating in the row address fixing mode, the memory bank is continuously operated in the row address fixing mode to execute the request to the memory bank. When the RA unlock bit of the request is 1, the request is executed to the memory bank in the row address fixed mode, and then the memory is not in the row address fixed mode. To

(4D) RA Management Section Referring to FIG. 7, the RA management section 78 includes an RA match control section 113 for generating the row address match signal RM and an RA match control section 113 for generating the row address update inhibit signal RI. The lock control unit 114.

Referring to FIG. 8, the RA coincidence control unit 113.
Then, the RA register 128 has four fields RA0 to RA3 for holding row addresses that have been recently accessed to the corresponding four memory banks. When a new request is selected by the priority circuit 96 of the priority control unit 44 (FIG. 6) and the request is set in the request register 98,
From the request register 98, the row address RA included in the selected request, the request selection success signal SS, and the bank number in the physical bank group BKa #
Are supplied to the switch 123 via the paths 100, 101, and 102, respectively. The switch 123 uses the bank number BK in the physical bank group in the RA register 128.
The transmitted row address RA is written in the field corresponding to one memory bank having a #.

Selectors 133-136 and comparator 14
9 to 152 are provided corresponding to four memory banks, respectively. For example, the selector 133 uses the path 48
RA in response to the memory bank number BKa # in the bank group designated by the subsequent request supplied via
Select the row address in the register 128 that last accessed the memory bank with this number BKa #,
It is supplied to the comparator 149. The comparator 149 compares the row address specified by the subsequent request supplied via the path 48 with the row address output from the selector 133, and if they match, the row address for the subsequent request. The match signal RM is supplied to the request register 88 (FIG. 6) via the path 80. The same applies to the other selectors 134 to 136 and the comparators 150 to 152.

Referring to FIG. 9, the RA lock controller 11
4, RA lock registers 178 and 196 are provided corresponding to the memory access pipelines 3 and 4, respectively. The RA lock register 178 has 4 bits each consisting of 1 bit and corresponding to 4 memory banks.
It has one RA lock bit RL00-03. The first subscript of the RA lock bits RL00-03 indicates the memory access pipeline number 0, and the second subscript indicates the physical bank group of the corresponding memory bank and the memory bank number in the physical bank. Each RA lock bit, eg RL
00 takes the value 1 or 0 indicating whether or not the request from the corresponding memory access pipeline 0 locks the row address of the memory bank BKa # 0. RA
The same applies to the lock register 196.

A request is newly selected by the priority circuit 96 of the priority control unit 44 (FIG. 6), and the request is registered in the request register 98 (FIG. 6).
Set to 0, the row address lock bit RL of the request contained in the selected request from the request register 98 is transferred to R via the path 103.
A lock register 178 is provided corresponding to each field, AND gates 162, 164, 166, 168 connected to each set input and RA lock register 198 are provided corresponding to each field, and a similar A
It is supplied to the ND gates 180, 182, 184, 186. Further, the row address unlock bit RUL of the request is also provided corresponding to each field of the RA lock register 178 via the path 103, and AND gates 163 and 16 connected to the respective reset inputs.
5, 167, 169 and a similar AND gate 1 provided corresponding to each field of the RA lock register 198.
81, 183, 185, 187.

Further, the memory access pipeline number PL # of the selected request is supplied to the decoder 154 via the path 103. When the number PL # is 0, the decoder 154 supplies the value 1 to the AND gates 162 to 169 connected to the RA lock register 178 corresponding to the memory access pipeline 3 via the path 159. Similarly, when the number PL # is 1,
AND connected to the RA lock register 196 corresponding to the memory access pipeline 4 via the path 160
A value of 1 is supplied to gates 180-187.

Further, the bank number in the physical bank group BKa # of the selected request is supplied to the decoder 153 via the path 102. The decoder 153 is
When the number BKa # is 0, 1, 2, 3 and RA is set via the paths 155, 156, 157 and 158, respectively.
RA lock bit RL00 in lock register 178,
A pair of ANs connected to RL01, RL02, RL03
D gates 162 and 163, 164 and 165, 166 and 1
67, 168 and 169, and RA lock register 19
RA lock bits RL10, RL11, RL1 in 8
2, a pair of AND gates 180 and 181, 182 and 183, 184 and 185, 186 and 1 connected to RL13.
Supply 87 with the value 1.

Thus, for each RA lock bit in the RA lock register 178, for example, RL00, the request from the memory access pipeline 3 is selected by the priority circuit 96, and the request has the memory bank number BKa # in the physical bank group. It is set when the request is to access the memory bank which is "0" and the RA lock bit RL of the request is "1". Also, this RA lock bit RL00
, The request from the memory access pipeline 3 is selected by the priority circuit 96, and the request is the memory bank number BKa # in the physical bank group.
Is a request to access a memory bank whose "0" is "0", and the RA unlock bit RU of the request
It is reset when L is "1".

The same applies to the other RA lock registers RL01 to RL03 in RA lock register 178 and the RA lock bit in RA lock register 198. The selector 207 or 208 is issued by the memory access pipeline 3, and the memory bank accessed by the subsequent request supplied via the path 48 or 49 is issued by another memory access pipeline 4 and already selected. It is for detecting whether or not the lock has been completed by the preceding request. Specifically, from the RA lock register 196 provided corresponding to the memory access pipeline 4, the path 48 or 49
The lock bit corresponding to the memory bank number BKa # in the physical bank group given by is read and output as the RA change prohibition bit RI to the request registers 88 and 89 (FIG. 6) via the line 80 or 81. The selector 205 or 206 is issued by the memory access pipeline 4, and the memory bank accessed by the subsequent request supplied via the path 50 or 51 is issued by the memory access pipeline 3 and is already selected. It is for detecting whether or not the request is locked by the request. The selector 207,
It operates similarly to 208.

(4E) Bank Busy Management Section Referring to FIG. 10, in the bank busy management section 79, the bank busy counter 214 holds four bank busy times for holding the bank busy times for the corresponding four memory banks.
It has two fields BC0 to BC3. When a request is newly selected by the priority circuit 96 of the priority control unit 44 (FIG. 6) and the request is set in the request register 98, the row address RA included in the selected request is read from the request register 98. , Request selection success signal SS, and bank number in physical bank group BKa # are supplied to the switch 209 via paths 100, 101, and 102, respectively. The switch 209 is a bank busy counter 21.
The transmitted bank busy time BT is written in the field in 4 corresponding to one memory bank having the bank number BKa # in the physical bank group.

Request selection success signal SS of path 101
Is input to the switch 209. The BG memory bank number (BKa #) of the path 102 is used as an output destination selection signal of the switch 209. That is, the path 102
If the in-BG memory bank number (BKa #) of the switch 209 is “0”, the switch 209 transfers the request selection success signal SS to the enable input indicated by “E” of BC0 of the bank busy counter 214. When the bank number (BKa #) is "1", "2", and "3", the request selection success signal SS is transferred to the enable inputs (E) of BC1, BC2, and BC3, respectively. Also, pass 10
The bank busy time (BT) of 4 is connected to all the data inputs indicated by “D” of BC0 to BC3 of the bank busy counter 214.

Thus, the request selection success signal SS
BG memory bank number (BK
BC in the bank busy counter 214 indicated by a #)
0 to BC3, pass 104 bank busy time (B
T) is stored. Furthermore, the bank busy counter 214
Then, the bank busy counters BC0 to B of each memory bank
C3 is decremented by 1 every cycle. If BC0-BC
When the value of 3 is "0", the subtraction is not performed. By this processing, the bank busy time in each memory bank can be stored.

The bank busy time stored in the bank busy counter 214 is passed through the paths 215 to 218.
It is sent to the OR gates (OR0 to OR3) 219 to 222. The OR gates (OR0 to OR3) 219 to 222 respectively include BC0 to BC0 in the bank busy counter 214.
All the bits of BC3 are ORed (logical sum), and the OR result is passed through paths 223 to 226 to selectors 227 to 23.
Send to 0. OR gates (OR0 to OR3) 219 to 22
By ORing all the bits of BC0 to BC3 in 2, the "0" is output to the paths 223 to 226 only when the value of BC0 to BC3 is "0".
When the value of C3 is not "0", "1" is output to the paths 223-226. As a result, the bank busy signal is sent to the selectors 227 to 230 via the paths 223 to 226.

The selectors 227 to 230 receive only the BG memory bank numbers (BKa #) of the subsequent requests via the paths 48 to 51, and use them as select signals to correspond to these BG memory bank numbers (BKa #). Selected bank busy signal. For example, if the BG memory bank number (BKa #) indicated by the path 48, which is the select signal of the selector 227, is “0”, the selector 227 ORs the BC0 of the bank busy counter 214 obtained via the path 223 with the OR gate. At 219, the bank busy signal obtained by the OR operation is selected. Similarly,
In the selector 227, the memory bank numbers (BKa #) in the BG obtained via the path 48 are “1”, “2”, “3”.
In this case, the bank busy signals 224, 225 and 226 obtained by ORing BC1, BC2 and BC3 are selected.

The same applies to the selectors 228 to 230. When the BG memory bank number (BKa #) obtained via the paths 49 to 51 is "0" to "3", BC0 to BC3 are correspondingly changed. The bank busy signals 223 to 226 obtained by the OR operation are selected. The selected bank busy signal BB is sent to the request registers 88 to 91 via the paths 84 to 87.

According to the present embodiment example, when the RA of consecutively issued requests can be left unchanged,
Since it is possible to access by changing only CA without changing RA, the row address fixed mode of the synchronous DRAM can be effectively used. Further, since the control using the RA change prohibition bit RI is performed, RA is not excessively changed.

Incidentally, the present invention is not limited to the synchronous DRAM, but similarly to this, another memory such as a cache having a row address applied once and continuously accessible by a plurality of column addresses is provided. It can also be applied to DRAM.

[0125]

According to the present invention, in a main memory device configured by using a synchronous DRAM, the row address fixed mode, which is a characteristic of the synchronous DRAM, can be effectively used, and the main memory device has a high throughput. Is obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a main part of a vector processor according to the present invention.

FIG. 2 is a diagram showing address allocation to a main memory of the vector processor of FIG.

3 is a block diagram of a requester used in the vector processor of FIG.

FIG. 4 is a block diagram of a storage control unit used in the vector processor of FIG.

5 is a block diagram of an address decoding unit used in the storage control unit of FIG.

FIG. 6 is a block diagram of a priority control unit used in the storage control unit of FIG.

7 is a block diagram of an RA management unit used in the priority control unit of FIG.

8 is a circuit diagram of an RA coincidence control unit used in the RA management unit of FIG. 7.

9 is a circuit diagram of an RA lock control unit used in the RA management unit of FIG. 7.

10 is a circuit diagram of a bank busy management unit used in the priority control unit of FIG.

11 is a circuit diagram of a priority circuit used in the priority control unit of FIG.

12 is a circuit diagram of an inter-PL priority management unit used in the priority circuit of FIG.

FIG. 13 is a timing chart of the conventional synchronous DRAM in the case where the row address fixed mode is used and the case where it is not used.

FIG. 14 is a diagram showing addresses assigned by a conventional interleaving method.

FIG. 15 is a diagram showing addresses assigned by a conventional block interleaving method.

16 is a schematic circuit diagram of the RL / RUL bit generation unit in FIG.

[Explanation of symbols]

1 ... Arithmetic unit (ALU), 2 ... Vector register unit (VR
U), 3, 4 ... Memory access pipeline (PL0,
PL1), 5 ... Storage control unit (SCU), 6 ... Main storage unit (MS), 7, 8 ... Vector data control module (V
DM0, VDC1), 9, 10 and 11, 12 ... Vector data control unit (VDC0, VDC1 and VDC2, VDC)
3).

Claims (13)

[Claims] 1. A storage device having a plurality of memory banks, each of which is divided into M (M is an integer of 2 or more) physical bank groups each of which is made up of N (N is an integer of 2 or more) memory banks. A plurality of request circuits for respectively outputting memory access requests to the storage device; and a plurality of request circuits connected to the storage device and the plurality of request circuits, each provided corresponding to one of the plurality of physical bank groups, And a plurality of priority control units for arbitrating a plurality of memory access requests output in parallel from a plurality of request circuits and transferring one of the plurality of memory access requests to a corresponding physical bank group, Each memory bank is composed of a memory having a plurality of storage locations accessed by a row address and a column address. , A group of memory locations having the same row address and different column addresses can be continuously accessed by applying the row address once and then continuously applying the column addresses of the group of memory locations. , The plurality of memory banks include N logical bank groups each having M memory banks so that M memory banks having the same memory bank number in the physical bank group belong to the same logical bank group. A plurality of address blocks each of which is composed of M × L (L is an integer of 2 or more) addresses are sequentially assigned to different logical groups and belong to each address block.
Addresses are assigned to sequentially different M memory banks belonging to the logical group to which the address block is assigned according to an interleaving method, and as a result, to each of the M memory banks belonging to the logical group. L addresses are allocated, and among the plurality of addresses allocated to each memory bank,
A processor system in which L addresses belonging to the same address block have the same row address and are allocated to a plurality of storage locations having different column addresses. 2. The integer L is smaller than the total number of a group of storage locations having the same row address and different column addresses in each memory bank, and having the same row address in each memory bank. However, the group of storage locations having different column addresses is
2. The processor system according to claim 1, further comprising: a plurality of storage locations to which addresses belonging to the address block are assigned; and a plurality of storage locations to which addresses belonging to at least one other address block are assigned. 3. The processor system according to claim 2, wherein the integer L is equal to an integer fraction of a total number of a group of memory locations having the same row address and different column addresses in each memory bank. 4. A storage device comprising a plurality (N × M) of memory banks (N and M are integers of 2 or more), a plurality of request circuits for outputting memory access requests to the storage devices, and memories. A bank is composed of a memory having a plurality of storage locations accessed by a row address and a column address, and the memory stores a group of storage locations having the same row address and different column addresses as the row addresses. It is configured to be continuously accessible by applying once and then continuously applying the column addresses of the storage locations, and the plurality of memory banks are divided into N logical bank groups each including M memory banks. A plurality of address blocks, each of which is divided into M × L (L is an integer of 2 or more) addresses, are sequentially different. N addresses assigned to each of the M logical groups belonging to each address block are sequentially assigned to different ones of the N memory banks belonging to one logical group to which the address block is assigned according to an interleaving method. L addresses are allocated to each memory bank in the logical group as a result, and the integer L has a group of storages having the same row address and different column addresses in each memory bank. A group of storage locations that are smaller than the number of locations and have the same row address and different column addresses in each memory bank are a plurality of storage locations to which addresses belonging to the first address block are allocated. Multiple addresses assigned to at least one other address block Processor system and a storage position. 5. The processor system according to claim 4, wherein the integer L is equal to an integer fraction of the total number of a group of memory locations having the same row address and different column addresses in each memory bank. 6. A storage device comprising a plurality of memory banks, a plurality of request circuits which respectively output a group of memory access requests to the storage device, and a plurality of request circuits connected to the storage device and the plurality of request circuits. And a priority control circuit for arbitrating a plurality of memory access requests output in parallel from the request circuit and transferring the requests to the plurality of memory banks, each memory bank being accessed by a row address and a column address. A memory having a plurality of memory locations, the memory applies a row address once to a group of memory locations having the same row address and different column addresses, and continuously applies the column addresses of the memory locations. It is configured to be continuously accessible by applying the The control circuit selects, from among the plurality of memory access requests output in parallel from the plurality of request circuits, at least one memory access request to which access should be permitted, and a circuit for selecting one of the plurality of memory banks. A plurality of row address storage devices provided correspondingly, each row address storage device being accessed by a preceding memory access request recently permitted by the selection circuit to access the corresponding memory bank. One for storing a row address of a storage location in a corresponding memory bank, and a row assigned to a storage location in the memory bank accessed by each of the plurality of memory access requests output in parallel by the plurality of request circuits. Address and its memo among the above-mentioned row address storage devices A detection circuit for detecting a match between row addresses stored in one row address storage device corresponding to a bank, and a detection circuit for selecting a plurality of memory access requests depending on a detection result by the detection circuit. A processor system having a circuit for controlling selection. 7. The control circuit preferentially selects another memory access request for which a match is detected by the detection circuit, over one memory access request for which a match is not detected by the detection circuit. 7. The processor system according to claim 6, further comprising a circuit that controls the selection circuit. 8. A storage device comprising a plurality of memory banks, a plurality of request circuits which respectively output a group of memory access requests to the storage device, and a plurality of request circuits connected to the storage device and the plurality of request circuits. And a priority control circuit for arbitrating a plurality of memory access requests output in parallel from the request circuit and transferring the requests to the plurality of memory banks, each memory bank being accessed by a row address and a column address. A memory having a plurality of memory locations, the memory applies a row address once to a group of memory locations having the same row address and different column addresses, and continuously applies the column addresses of the memory locations. It is configured so that it can be accessed continuously by applying each request circuit. A circuit for sequentially outputting a series of memory access requests, and a lock request for requesting to lock one row address in one of the plurality of memory banks, and after the one memory bank is locked And a lock / unlock request circuit that outputs an unlock request for unlocking the row address of the one memory bank, the priority control circuit being output in parallel from the plurality of request circuits. A circuit for selecting at least one memory access request to be permitted access among the plurality of memory access requests, and the lock / lock included in one of the plurality of request circuits.
In response to the lock request output from the unlock request circuit, information indicating that the row address specified by the lock request in the memory bank specified by the lock request is stored by the request circuit is stored. A lock information storage device that stores information indicating that the row address in the memory bank has been unlocked in response to an unlock request that is subsequently output from the lock / unlock request circuit, and the plurality of request circuits. Each of the plurality of memory access requests output in parallel by means of a row address locked by a request circuit other than the request circuit that outputs the memory access request is assigned to a memory bank accessed by the memory access request. First to match the memory bank that has Whether or not the condition is satisfied, and when one of the memory access requests satisfies the first condition, the row address specified by the memory access request becomes the row address locked by the other request circuit. A circuit for detecting whether or not the second condition of coincidence is detected by the information stored in the lock information storage device, and the selection depending on the detection result of the detection circuit for the plurality of memory access requests. And a circuit for controlling selection by the circuit. 9. The control circuit outputs one memory access request output from any one of the request circuits, and if the first condition is satisfied and the second condition is not satisfied, one memory access request is detected. Also selects the memory access request output from the other request circuit and preferentially selecting the other memory access request detected by the detection circuit unless at least one of the first and second conditions is satisfied. 9. The processor system according to claim 8, further comprising a circuit that controls the circuit. 10. The control circuit outputs from any one of the request circuits, satisfies the first condition, and outputs the second signal.
If one of the memory access requests detected by the detection circuit is not satisfied, the other output circuit outputs the request, and if at least one of the first and second conditions is not detected, the detection circuit detects the request. The operation of preferentially selecting the other memory access request is output by the other request circuit, and is detected by the detection circuit unless at least one of the first and second conditions is satisfied. Repeat until a predetermined number of memory access requests are selected, then
10. The processor system according to claim 9, further comprising a circuit that controls the selection circuit so as to select the one memory access request. 11. The lock / unlock request circuit in each request circuit outputs a lock request in addition to one preceding memory access request output from the request circuit, and outputs another lock request from the request circuit. It has a circuit that outputs an unlock request in addition to a subsequent memory access request, and the lock request is of a row address specified by the preceding memory access request in the memory bank specified by the preceding memory access request. The lock request and the unlock request are
9. The processor system according to claim 8, wherein unlocking of a row address specified by the subsequent memory access request in the memory bank specified by the subsequent memory access request is requested. 12. A circuit for sequentially outputting the series of memory access requests in each request circuit includes a series having a series of addresses in response to access information designated by an instruction requesting access to the series of addresses. Has a circuit for sequentially outputting a series of memory access requests for accessing the memory locations, and the lock / unlock request circuit in each request circuit selects the same memory bank from the series of memory access requests. A lock request is added to at least the first memory access request of the plurality of memory access requests to be accessed, and a lock request is added to the last memory access request of the plurality of memory access requests to access the same memory bank. Command to output an unlock request by 11. The processor system according to claim 10, further comprising a circuit that determines whether to add a lock request and an unlock request to each of the series of memory access requests based on the information. 13. The processor system according to claim 12, wherein the series of addresses are addresses separated by a constant address interval.