JPH0916466A - Memory control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory control system capable of supporting different DRAMs between a main memory and an extension memory by setting timing parameters different in an RAS(row address strobe) between that to which the main memory is assigned and that to which the extension memory is assigned. SOLUTION: The main memory 7 and the extension memory 21 are provided, first RAS signals to be outputted to the main memory 7 are generated and second RAS signals to be outputted to the extension memory 21 generate the timing parameters different in RAS signals between the first RAS signals and the second RAS signals. Then, the access timing control of a high-speed page mode memory is performed when a memory is constituted of the high-speed page mode memory and the control of the access timing of an EDO(extended data out) memory is performed when the memory is constituted of the EDO memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control system, and more particularly to a high speed page mode memory and an EDO (Ext).
The present invention relates to a control system for an end data out memory (hyperpage mode memory).

[0002]

2. Description of the Related Art In recent years, a notebook-type or laptop-type portable personal computer which is easy to carry and can be operated by a battery has been developed. On the other hand, CPU (Central Processing)
Unit) is getting faster year by year. For example, Intel Corp. 80286-80386, 80486, Pe
.. continues to be speeded up, and the CPU internal clock has been speeded up and the CPU bus width has been expanded.

IBM P announced by IBM in 1984
The CAT has 80286 (6 MHz, then 8
MHz), the main memory capacity is 256K / 512K bytes, the main memory DRAM is a 64K bit product, and it is connected to the CPU through the ISA bus (6MHz). The DRAM access time was 100 ns or more, but the CPU access time was about 167 ns, so data could be transferred without waiting.

The CPU registered on the personal computer becomes faster,
With the demand for high-speed data transfer, a bus for memory was created and it became possible to access in page mode and high-speed page mode. At present, the external operating frequency of the CPU has increased about 10 times (performance is about 200 times in MIPS). On the other hand, the improvement in the performance of DRAM is only about 1/2 of the access time, which cannot be said to catch up with the CPU. Therefore, attempts have been made to make the CPU catch up by increasing the cycle time by various means.

As such a DRAM, for example, a high-speed D
RAM and EDO DRAM (Hyper page mode D
It is also known as RAM). In the high speed page mode, as shown in FIG. 14D, C in FIG.
When AS # (# means active low) rises, the data output becomes invalid, but the EDO DRAM holds the data until the next CAS # falls, as shown in FIG. 14 (e). If the CAS # cycle is shortened as shown in FIG. 14 (f) to perform high-speed data transfer, in the high-speed page, CAS # rises before data output as shown in FIG. I can't take it out. On the other hand, the EDODRAM has a feature that the CAS # cycle can be shortened because the data is held until the next CAS # falls, as shown in FIG.

In a notebook type personal computer where space is important, a CPU is used instead of the 80486 with a cache.
There is a product that uses Pentium as the above and uses EDO DRAM without using cache.

However, due to problems such as delivery of EDO DRAM, EDO DRAM and high speed page mode D
It is desirable to support both RAM. Further, in the case of a portable computer using 80486 as a conventional CPU, a 32-bit DRAM has been used as an expansion RAM. On the other hand, when the Pentium is used as the CPU, the data bus width is 64 bits. Therefore, a 64-bit DRAM is desirable as the expansion memory.
It is desirable to be compatible with bit extended DRAM.

[0008] In addition, some of these computers have 1
Book RAS (Row Address Strobe)
There is one corresponding to one memory bank.
In such a computer, for example, a high-speed memory may be used as the internal memory and a low-speed but inexpensive memory may be used as the external memory. In this case, if only one kind of timing can be set, there is no choice but to match the low-speed memory timing, and the performance of the high-speed memory cannot be utilized. Therefore, it is necessary to control the memory with different timing parameters for each RAS.

Further, according to the Pentium specifications, as shown in FIG. 15, the NA # signal (a signal indicating that the pipeline cycle is in the ready state, that is, a new bus cycle in a state where the current cycle is not completed) The pending cycle is driven within 2 clocks after the signal indicating that the external memory is in the accepting state) is asserted. On the other hand, as shown in FIG. 16, if the NA # signal is not asserted, an idle cycle (Ti) is inserted every cycle. Therefore, there is a problem that the processing speed becomes slower by that amount.

[0010]

As described above, when memories having different access times are used for the main memory and the extended memory, the memory speed must be adjusted to a low speed, and the performance of the high speed memory cannot be utilized. There are drawbacks. Moreover, it was not possible to switch and use two types of memories as main memories depending on the design. Further, conventionally, in the EDO memory, the read / write control could not be performed without using the OE # signal.
When the CPU is Pentium and the pipeline mode is not specified, the idle cycle (T
Since i) is inserted in the cycle, there is a problem that the high speed processing of the CPU cannot be utilized.

The present invention has been made in view of the above situation, and the purpose thereof is different between the main memory and the extended memory.
It is to provide a memory control method capable of supporting RAM.

Another object of the present invention is to provide a memory control system capable of switching a main memory to a high speed page mode memory or an EDO memory. Still another object of the present invention is to provide a memory control system in which memories having different access times can be mixed and used by having a timing parameter for each RAS.

Still another object of the present invention is to control the read / write cycle of the memory with a small number of pins by changing the control of the WE # signal between the high speed page mode and the EDO memory. Is to provide.

Still another object of the present invention is that it is possible to individually switch whether or not to use the pipeline mode (NA # assert) according to the type of cycle (DRAM access, VL access), and the DRAM is also available.
It is an object of the present invention to provide a memory control method capable of speeding up the memory access time in response to the speeding up of the processing speed of the CPU by switching the assertion position of NA # during the cycle.

To achieve the above object, the memory control method of the present invention is a high speed page mode memory or EDO.
In a system having a memory having a first bit width composed of an (Extended Data Out) memory, when the memory is configured by a high speed page mode memory, access timing control of the high speed page mode memory is performed, and the memory performs EDO. When it is configured by a memory, it is provided with a memory control circuit for controlling the access timing of the EDO memory.

Further, the memory control system of the present invention includes: a main memory; an expansion memory; a first RAS (Row Address Strobe) for outputting to the main memory.
e) The second RAS signal for generating the signal and outputting it to the expansion memory generates different timing parameters for the first rAS signal and the second RAS signal.

Further, the memory control system of the present invention uses a high speed page mode memory or an EDO (Extended).
Data out) memory; and a CPU that outputs a read / write signal (W / R #) signal to the memory, in a system having read / write control of the high-speed page mode memory and the EDO memory Read / write control is performed without using the output enable signal (OE #).
A write enable (WE #) signal control means for performing yri to control #).

Further, the memory control system of the present invention, in a system having a CPU having a pipeline mode, has cycle control means for discriminating the type of cycle; and enabling / disabling the pipeline mode according to the cycle.
It has means for specifying disable.

According to the present invention, different memories can be used for the main memory and the extension memory such that the main memory is 64 bits and the extension memory is 32 bits. In addition, the extended memory can switch between 32/64 bits. Further, the main memory can selectively use the fast page mode and the EDO memory. Also, different timing parameters can be set for each RAS. Therefore, a flexible memory control system can be constructed.

By controlling the read / write of the EDO memory and the high speed page mode memory only by the WE # signal without using the OE # signal, the number of pins can be reduced and a compact DRAM controller can be constructed.

Further, it is possible to individually switch whether or not to use the pipeline mode (NA # assert) depending on the type of cycle (DRAM access, VL access). Therefore, the access time can be further shortened by outputting NA # and eliminating the idle cycle (Ti). Moreover, since the assertion position of NA # can be switched, an additional circuit such as an address latch circuit is not required.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an example of a computer system to which the memory control system of the present invention is applied. As shown in the figure, for example, a Pentium (P54C) manufactured by Intel Corporation of the United States is applied to the CPU 1. The CPU 1 is connected to the CPU control gate array 5 via the 64-bit data bus 3.
A 64-bit main DRAM 7 is connected to the data bus 3. Further, the CPU 1 and the CPU control gate array 5 are connected via the control bus 9.
The control bus 9 is the ADS # output from the CPU 1.
The signal and the BE7-0 signal are supplied to the CPU control gate array 5. The ADS # signal is a signal indicating the start of the bus cycle. At the start of the bus cycle, the CPU 1 outputs the address to the common bus 11 described later during the "address time (T1)" to control the bus cycle definition information. Output to bus 9. Furthermore, C
PU1 indicates the correct address and bus cycle definition information on the bus by ADS (Address S).
status) # signal active. Note that # indicates that the above signal is active low. The data bus 3 and the control bus 9 form a CPU bus.

The CPU control gate array 5 has a data bus drive clock, a CPU controller 25 and a D controller.
It is composed of a RAM mapper, a DRAM controller 27, and a CPU cycle controller 29. In addition, a selector for register data from each of the above blocks, ADS #
, A clock output delay control circuit to the CPU, a clock / reset / suspend control circuit, an additional circuit for testing, and the like.
In FIG. 1, only the CPU controller 25, the DRAM controller 27, and the CPU cycle controller 29 are shown to simplify the drawing. The CPU control gate array 5 is connected via the VL bus 13 to the I (not shown).
It is connected to the ISA controller 15 that controls the SA bus. The VL bus 13 is composed of a 32-bit data bus 17, a control bus 19 and the like. A 32-bit extended DRAM 21 is connected to the 32-bit data bus 17. The control bus 19 uses the VADS # signal (A on the VL bus
DS # signal), VBE3-0, A02 signal, etc. are transferred. The VADS # signal is the ADS # output from the CPU 1.
The signal is VL by the CPU control gate array 15.
It is a signal converted so as to match the bus 13. further,
From the BE7-0 # signal output from the CPU 1, the VBE3-0 # signal and the A02 signal for the VL bus 13 are generated.

The common bus 11 is a CPU bus and a VL bus 13.
And address data A31-03,
The MIO # signal, DC # signal, and WR # signal are sent to the CPU
It is common to the bus and the VL bus. As described above, when the CPU is a Pentium, the data bus width is 64 bits. Therefore, addressing is performed in 64-bit units (8-byte units). Therefore, since the lower 3 bits of bits 0-2 are not necessary, the address data A31-03 is output to the common bus 11.
The MIO # signal is a signal indicating a memory address or an I / O address. When MIO # is at a high level, the memory address is output by the CPU 1, and when MIO # is at a low level, the I / O address is output. The DC # signal is a signal indicating data and control data. When DC # is high level, it means data, and when DC # is low level, it means control data. Further, when the WR # signal is at high level, it means "write", and when it is at low level, it means "read".

The VGA controller 23 is a VGA specification display controller, and is connected to the common bus 11 and the control bus 19. The common bus 11 is used for exchanging the address A31-03 and various signals MIO #, DC #, WR # with the CPU 11, the ISA controller 15 and the VGA controller 23.

FIG. 2 shows the DRAM controller 2 shown in FIG.
7 is a detailed block diagram of FIG. As shown in the figure, DRA
The M controller 27 includes an address control block 31, a timing control block 33, a backup refresh circuit 35, a control signal merge circuit 37 for HLDA, a test circuit 39, and a user macro 41. Further, the timing control block 33 includes a RAS generation circuit 43, a CAS generation circuit 45, an RCH generation circuit (a circuit for designating a timing for switching a column address) 47, a CBRST (C
AS before RAS timing) generation circuit 4
9, RDY generation circuit 51, BRDY generation circuit 53, cache control circuit 55, data bus control circuit 57, hold cycle control circuit 59, DRAM busy & NA control circuit 61, CPU cycle state transition control circuit 63, cycle latch circuit 65, shadow refresh request Control circuit 67, RAS timeout request control 69, and WE
It comprises a generation circuit 71.

FIG. 3 shows a one-chip gate array.
These are various input / output signals of the DRAM controller 27. This
The signals and their functions are shown below. I / F classification Signal name I / O function CPU LAD26-03 I CPU / VLAdress(latch) BE7Z-0Z I CPUBig enable(latch) ADSZ I CPUAddress Strobe MIOJ I CPUmemory/ IO (latch) WR I CPULight/ Lead PCD IPage Cash Dave Sable WBWT OLight back/Write through LOCKZ ILock CACHEZ Icache AHOLD OAdress Hold EADSZ O ExternalAddress Strobe KENZ OCash enable INV OINVALID BRDYZ O CPUReady HLDA IHold Acknowledge DCNAZ ONext address  VL-BUS VBE3IZ-0IZ I VLBusite Enable VRDYOOZ O VLBath Lady(Output) VRDYIZ I VLBath Lady(return) A02I I CPU / VLAdress(latch) VHOLDA O VLBus Hold Acknowledge D64HIT O DRAM control DRAMCYC I DRAM indicating that internal 64-bit memory has been hitcycle DRAMWP I DRAMLight Protect DRAMKNZ I DRAMCash enable DRAMWB ILight back/Write through ARADEF IArea fine(Light/ReadMA26-14 I logicMemory address RAS5Z-0Z O Internal: RAS1,0 Expansion: RAS5ー2 CAS7Z-0Z O Internal CAS MWEZ O Internal WE MADR11-00 O Memory address ECAS3Z-0Z O Expansion CAS EMWEZ O Expansion WE DRAMRF IShadow Refresh TimingSignal EXM32SL I Expansionmemory64/32BitSwitch 1 = 32Hi Git MEMWZ I ISAMemory read MEMRZ I ISAMemory light IOWTZ I ISAIOLight IORDZ I ISAIORead SA01-00 I ISAAdress01,00 MSTRZ IMaster SD07I-00I I InternalRegister light data REGD07-00 O InsideRegistered data REGSL O insideRegister Select clock CPCLKI I CPUclock(return) CPCLKO I CPUclock(Output) MCPCLK IMaster modeCPU used inclock VCLKI I VLBus clock CLK16M I 16MHzclock RFCLK I 32KHzclock Database Control DSELO OData(D63-32 / D31-0)Select VDLATO O VLDataLower DWORDlatch VDLAT1 O VLDataUpper DWORDlatch Others CLRZ I PCLR # + RCLR # DRAMTSZ ITest modeSignal PCLRZ I P-0Nclear As shown in FIGS. 2 and 3, DRAM controller 27
RA for DRAM 7 when CPU 1 is the master
S #, CAS #, WE #, row address (RAS #),
Column address (CAS #) timing control, cap
Burst address during shing fill and write back
Generation, BRDY for DRAM cycle of CPU1
#, KEN #, CACHE #, AHOLD, EADS
#, INV, NA # generation, DRAM logical address
Decoding RAS # based on CPU address
Page hit judgment, load from DRAM logical address
Response, column address generation, HLDA assertion, RA
S timeout request Shadow refresh request and CPU
Arbitration with DRAM access request, DRAM shadow
-Refresh cycle timing control and RA
Performs timing control of the S timeout cycle.

When the DMA / external master is the master, decoding of RAS # based on the DRAM logical address, generation of row address and column address from the DRAM logical address, RAS # and CAS for DRAM
#, WE #, row address / column address timing control, and VRDYIN # output to the VL bus.

Further, in the case of backup, a DRAM refresh cycle is generated. FIG. 4 is a control logic diagram when the timing parameter is set for each RAS.

The control logic shown in FIG. 4 is, for example, as shown in FIG.
As shown in (c), "-P" (value set at the rising edge of the clock CLK shown in (a) of the figure) is set to "0", "1", "1", "0" in order from the LSB. In this case, the circuit outputs the waveform shown in FIG.

The circuits shown in FIG. 4 are, for example,
It is provided corresponding to each signal such as for the RAS generation circuit and the CAS generation circuit. The timing register groups 73a to 73n are timing parameter setting registers provided corresponding to RAS0, for example. Similar timing register groups are provided in other RASes, respectively. For example, as shown in FIG. 6, in this embodiment, for example, RAS0 #
And RAS1 # are assigned to the 64-bit main memory, and RAS2 # to RAS # 5 are assigned to the extended memory. That is, one bank of memory is configured for one RAS. Further, the memory banks assigned to RAS # 2 to RAS # 5 are configured to be compatible with either 64-bit memory or 32-bit memory.

Further, the timing is set for each RAS. Therefore, for example, the main memory may be a memory with a fast access time, and the extended memory may be a memory with a slow access time but a low price. In this embodiment, for example, various timing parameters for controlling the memory bank assigned to RAS0 are prepared with a certain width. Therefore, as shown in FIG. 7, there is a plurality of register groups for loading the above timing parameters to one memory bank, but since the I / O map is limited, I / O as shown in FIG. The window system is adopted. As shown in FIG. 7, which RAS timing register is used is selected by the value loaded in the RAS select register.

The bit assignments of the various timing registers are as follows. bit 7 6 5 4 3 2 1 0 POWER ON RESET LLLLLLLL bit [7: 0] Specifies the timing of various control signals. Set the waveform image as it is. In terms of time, LSB is used first.

For example, if it is desired to output the waveform as shown in FIG. 9A, "55" is set in the timing register. The cycle decode circuit 75 is, for example,
A page hit read cycle or a bank miss write cycle is decoded. Then, the selector 77 outputs a selection signal for selecting a register in which the timing parameter corresponding to the detected cycle is set. The selector 77 selects the corresponding register based on the selection signal output from the cycle decode circuit. The shift register 79 shifts the bits output from the register by 1 bit in order from the LSB. In this case, since "55" is set in the register, L
"1", "0", "1""0","in order from SB
1 "," 0 "," 1 ", and" 0 "are shifted. The output from the shift register 79 is synchronized with the clock using the flip-flop 81 and output.
A waveform as shown in (a) is output.

For example, the write cycle is now shown in FIG.
It is assumed that it is defined as shown in (a). This write cycle timing register is used for each signal (in this case, FIG.
0 (a) to BUSY #, R as shown in FIG. 10 (d)
AS #, CAS #, BRDY #). In this BUSY # timing register, "1", "1", "
1 is loaded in parallel, "1", "0", "0" are loaded in parallel in the RAS # timing register, and "1", "in the CAS # timing register.
1 ”and“ 0 ”are loaded in parallel, and“ 1 ”,“ 1 ”, and“ 0 ”are loaded in parallel to the timing register for BRDY #.
When the write cycle shown in (1) is detected, by supplying the selection signal of the corresponding register to the selector, the LSB side of the register is output bit by bit and supplied to the shift register 79.

Further, the designation of which RAS timing register to access and the bit assignment of the RAS timing select register for switching the bit width of the extended memory between 64 bits and 32 bits are as follows. bit 7 6 5 4 3 2 1 0 POWER ON RESET LLLLLLLL bit [7: 4] RSTSL [3: 0] 4 bits specify which RAS timing register to access. You can specify 0-Fh (RAS0-
RAS15) 0000 ... RAS0 timing register 0001 ... RAS1 timing register ... 1111 ... RAS15 timing register [When the extension memory is 64 bits] Since common parameters are used, 5-0 The same timing register is selected no matter which value of (RAS5-0) is set. [When the extension memory is 32 bits] Different timing registers are used for internal and extension. In fact, RAS1,
Only two types, 0 (internal memory) and RAS5-2 (extended memory) can be specified. Therefore, a value of 0 or 1 is set when the parameter is set to the internal memory, and a value of 5-2 is set when the parameter is set to the extended memory. bit3 EXM32SL Status indicating the bit width of extended memory (read only) When 1, it indicates that the bit width of extended memory is 32 bits.

When 0, it indicates that the bit width of the expansion memory is 64 bits. bit [1: 0] TMGSL [1: 0] Specifies register group for parameter expansion when timing parameters are insufficient. 2-bit group 0
-3 can be specified and parameters are group 0 → 1 → 2 →
Used as 3. Actually, there are only groups 0-2.

00 ... Group 0 ↓ ... ↓ 11 ... Group 3 Next, the high-speed page mode memory and the EDO memory are used for WE.
A case where the # signal is switched and controlled will be described.

In this embodiment, special fea
By setting a parameter in the true register, switching control of the WE # signal is performed. special
The bit assignments of the feature register are as follows. Special Feature Reg (Por
t: 088D, KEY: 088C, INDEX: F4) bit [7: 5] fixed to 0 bit4 FSTMWE Valid only in hyper page mode. Lead-off cycle at page hit read cycle by speeding up rising edge of WE # signal at read. Shorten. When 1, the WE # rise at the time of reading is made one clock earlier than the conventional one. When 0, the same timing as before. WE # is started up when the cycle is determined (page hit FIX). bit3 Omitted since it is not directly related to the invention of the present application bit2 Same as above bit1 HYPEN Hyper page mode DRAM compatible mode is designated.
Switch the output method of WE. When 0, W of CPU
WE # is output based on / R #. When 1, WE # is deasserted only during the DRAM cycle of the CPU.
In either case, WE # is deasserted during HLDA, shadow refresh, etc. bit0: Omitted since it is not related to the present invention. FIG. 13 shows a waveform diagram when bit 1 of the above-mentioned special feature register is set to 0.

As shown in FIG. 3D, in the high speed page mode, when the CPU-W / R # signal becomes active low in the read cycle, the DRAM-WE # (high speed page mode) becomes high level and the read operation is performed. Holds high for a while.

On the other hand, in the hyper page mode, the DRAM-WE signal is deasserted in each read cycle as shown in FIG. By doing so, the data can be cut even if the CAS # signal does not fall, and as a result, the data can be read correctly.

Further, the write enable signal (WE #) in the fast page mode has its default value set to low level (read), whereas it has been set to high level (write) in EDO. Now, assuming that the data B shown in FIG. 12E is the last access, FIG.
The CAS # signal shown in (d) does not fall and continues to be output at the high level as shown by the broken line. As a result, as described above, the data output of FIG. 7E continues to be output without being cut off. Therefore, the data output from the CPU may collide. For this reason,
The WE # signal is normally set to a low level and is set to a high level during a read cycle. Then, at the end of the access, WE # is lowered to a low level as shown in FIG. 12 (f) instead of lowering CAS #. In the case of the EDO memory, the specifications of the memory are defined so that the data may be cut even at the falling edge of the WE # signal. Next, switching control of NA # timing will be described.

The bit assignments of the NA timing control register are as follows. bit 7 6 5 4 3 2 1 0 POWER ON RESET LLLLLLLL bit7 NAEN When set to 1, enable pipeline mode (N
Output A #).

When 0, the pipeline mode is disabled (NA # is not output). bit2-0 NATIM2-0 Switches where to assert NA #.

NATIM2 NATIM1 NATIM0 0 0 0 ・ ・ ・ Invalid 0 0 1 ・ ・ ・ 1 clock before BRDY # (To be exact, 1 clock before BUSY is cut off: same as below) 0 1 0 ・ ・ ・ BRDY # 2 clocks before 0 1 1 ・ ・ ・ 3 clocks before BRDY # 1 0 1 ・ ・ ・ 101 Settings above are invalid ~ 1 1 1 As mentioned above, where NA # is asserted to bit 2-0 of NA timing control register By setting the information for switching whether to
1 (f), one clock before BRDY #, B
It is possible to switch two clocks before RDY # or three clocks before BRDY #. FIG. 15 and FIG.
As described in 6, the idle cycle Ti is inserted every cycle in the non-pipeline mode.
By inserting this NA #, the idle cycle Ti can be eliminated, and the higher speed processing can be performed.

Further, it is possible to test how far the circuit normally operates when the address is switched without the address latch circuit. A BUSY # parameter is provided to determine where the data in the shift register 79 ends. For example, it is configured so that where to end can be set during a write cycle. For example, in the case of the waveform shown in FIG. 10, the BUS of FIG.
When Y # becomes "0", the shift operation corresponding to the parameter of each signal is completed. Therefore, the end of the cycle can be detected by monitoring the BUSY # signal. For this BUSY # signal, N clocks before the number of clocks specified by the register.
The position of NA # can be switched by providing a circuit for outputting A #. In this embodiment, the DRAM busy & NA control circuit 61 shown in FIG. 2 performs this function. For example, when NA # is output one clock before BRDY # shown in FIG. 10D, NA # may be output one clock before the write cycle in FIG. 10A ends.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a computer to which a memory control system of the present invention is applied.

FIG. 2 is a detailed block diagram of the DRAM controller shown in FIG.

FIG. 3 is a diagram showing various input / output signals of a DRAM controller configured by a one-chip gate array.

FIG. 4 is a control logic diagram when a timing parameter is set for each RAS.

5 is a waveform chart showing an example of a waveform output by the control logic of FIG.

FIG. 6 is a conceptual diagram showing a relationship between a plurality of RAS signals and a main memory and an extended memory assigned to these RAS signals.

FIG. 7 is a conceptual diagram showing a plurality of timing registers that store timing parameters for each RAS and registers for selecting RAS (timing register).

FIG. 8 is an I / O circuit for a plurality of timing registers shown in FIG.
I / O mapped to a specified I / O window on the map
The conceptual diagram which shows a window system.

FIG. 9 is a waveform chart showing an example of timing parameters set in a timing register.

FIG. 10 is a waveform chart showing an example of a write cycle and timing parameters set in a write cycle timing register.

FIG. 11: NA # showing where to assert NA #
The timing chart for demonstrating switching timing.

FIG. 12 is a timing chart showing timings of various signals in a high-speed page mode read cycle.

FIG. 13: W in high speed page memory and EDO memory
6 is a timing chart for explaining control of switching E #.

FIG. 14 is a timing chart for explaining each characteristic of the high speed page memory and the EDO memory.

FIG. 15 is a waveform diagram of a pipeline bus cycle in the Pentium CPU.

FIG. 16 is a waveform diagram of non-pipeline bus cycles in the Pentium CPU.

[Explanation of symbols]

1 ... CPU, 3 ... Data bus, 5 ... CPU
Control gate array, 7 ... main DRAM,
9 ... Control bus, 11 ... Common bus, 13
... VL bus, 15 ... ISA controller, 17
... Data bus, 19 ... Control bus, 21
... Extended DRAM, 23 ... VGA controller,
25 ... CPU controller, 27 ... DRAM controller, 29 ... CPU cycle controller,
31 ... Address control block, 33 ... Timing control block, 35 ... Backup refresh circuit, 37 ... HLDA control signal merge circuit, 3
9 ... Test circuit, 41 ... User macro, 43 ...
..RAS generation circuits, 45 ... CAS generation circuits, 47
... RCH generation circuit, 49 ... CBRST generation circuit, 51 ... RDY generation circuit, 53 ... BRDY generation circuit, 55 ... Cache control circuit, 57 ... Data bus control circuit, 59 ... ..Hold cycle control circuit, 61 ... DRAM busy & NA control circuit, 6
3 ... CPU cycle state transition control circuit, 65 ...
Cycle latch circuit, 67 ... Shadow refresh request control circuit, 69 ... RAS timeout request control circuit, 71 ... WE generation circuit, 73 ... Timing register group, 75 ... Cycle decode circuit, 77.
..Selectors, 79 ... Shift registers, 81 ...
Flip-flop circuit.

Claims (5)

[Claims] 1. A fast page mode memory or EDO (E
In a system having a memory having a first bit width consisting of an xended Data Out) memory,
A memory control circuit for controlling access timing of the high speed page mode memory when the memory is composed of a high speed page mode memory, and for controlling access timing of the EDO memory when the memory is composed of an EDO memory; An expanded memory having the first bit width or a second bit width smaller than the first bit width; and a memory for controlling switching of the first bit width or the second bit width. control method. 2. A main memory; an expansion memory; a first RAS (Row Address) for outputting to the main memory.
S Strobe) signal, and the second RAS signal output to the expansion memory includes a RAS signal generation circuit that generates different timing parameters between the first RAS signal and the second RAS signal, and the RAS signal generation circuit includes the RAS signal generation circuit. A memory control system having a plurality of registers for reading parameters, wherein the plurality of registers are mapped as an I / O window in an address space of the CPU. 3. A fast page mode memory or EDO (E
a memory composed of an Xtended Data Out memory; and a read / write signal (W /
In a system having a CPU for outputting an R #) signal, read / write control of the high speed page mode memory and read / write control of the EDO memory are performed without using an output enable signal (OE #). A memory control method comprising a write enable (WE #) signal control means which is controlled by (WE #). 4. The WE # signal control means sets the WE # signal to a low level as a default value for the EDO memory, and sets it to a high level only during a read cycle, and sets it to the high speed page mode memory. 4. The memory control method according to claim 3, wherein the WE # signal is output based on the W / R # signal output from the CPU. 5. A system having a CPU having a pipeline mode, comprising cycle control means for determining a cycle type; means for designating enable / disable of the pipeline mode according to the cycle, The CPU is a Pentium, and the enable / disable of the pipeline mode is NA #.
A memory control method characterized by further comprising means for switching the assert position of the NA # signal, which is performed by asserting or deasserting a (Next Address) signal.