JPH09162791A - Diversity receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a diversity receiver which can be provided by simple configuration and simple operating processing by weighting a base band signal through bit shift. SOLUTION: Respective bas band signals outputted from reception parts 3 and 4 are defined as b1 and b2 and respective received field intensity signal (RSSI) are defined as a1 and a2 . A subtractor 21 subtracts the value of RSSI a1 from the value of RSSI a2 and outputs a subtracted signal c1 . In the case of C1 <=0, a bit shifter 23 outputs the base band signal b1 as it is. In the case of C1 >0, each time the value of C1 is increased for 3dB, the base band signal b1 is shifted to right for one bit. A subtractor 22 and a bit shifter 24 are also operated similarly to the operation as mentioned above. Then, weighted base band signals d1 and d2 from the bit shifters 23 and 24 are added by an adder 10 and a base band output signal S is outputted.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a diversity receiver used for wireless communication and the like.

[0002]

2. Description of the Related Art In recent years, a diversity receiver has been used as an effective means for removing the influence of fading from a received signal of an antenna.

As the diversity system, there are a maximum ratio combining diversity system after detection and a selection diversity system after detection. The post-detection maximum-ratio combining diversity method is a method in which baseband signals from a plurality of receiving units are weighted by the square of the received electric field strength value at each receiving unit, combined, and decoded to perform decoding. Is
A signal having the highest received electric field strength is selected from a plurality of received signals and is decoded. At present, it is known that the maximum ratio combining diversity scheme after detection is superior to the selection diversity scheme after detection.

Conventionally, as the maximum ratio combining diversity receiver after detection, the one shown in FIG. 3 is known. FIG. 3 is a block diagram showing a conventional diversity receiver. In FIG. 3, 1 and 2 are antennas that receive radio waves and output reception signals, and 3 and 4 are input reception signals of the antennas 1 and 2, and reception field strength (RSSI) signals a1 and a2
And a receiving unit that outputs the baseband signals b1 and b2.
Is A / that converts the RSSI signals a1 and a2 and the baseband signals b1 and b2 from the receivers 3 and 4 into digital signals.
D converters, 6 and 7 are exponential converters for exponentially converting the value of the digitized RSSI signal, 8 and 9 are weighting multipliers, and 10 is a signal obtained by adding the signals from the multipliers 8 and 9 and outputting them. It is an adder. In the exponential converters 6 and 7, the value (RSSI value) of the input digitized RSSI signal is d.
Since the value is proportional to the B value, those values are exponentially converted to the true numbers. In the multipliers 8 and 9, the baseband signals b1 and b2 obtained from the A / D converter 5 are weighted by the magnitude of the RSSI signal obtained from the exponential converters 6 and 7 (RSSI value obtained by exponential conversion). Do.

The operation of the post-detection maximum ratio combining diversity receiver having the above configuration will be described. In FIG. 3, assuming that the values of the received electric field strengths of the antennas 1 and 2 are s1 and s2, the RSSI values output from the A / D converter 5 are 20 log (s1) and 20, respectively.
log (s2). Therefore, the exponential converters 6 and 7 output exponentially converted RSSI values s1 and s2, respectively. Next, in the multipliers 8 and 9, the baseband signal b
1 and b2 are weighted to the square of the received electric field strength values s1 and s2, and the weighted baseband signals of s1 ² b1 and s2 ² b2 are output. Finally, the respective weighted baseband signals are added by the adder 10, and the baseband output signal having a value of s1 ² b1 + s2 ² b2 is output as the demodulation output signal s. In this way, it is possible to obtain the combined output signal (demodulation output signal) s in which the baseband signals b1 and b2 are weighted by the square of the received electric field strength values s1 and s2.

[0006]

However, since the above-mentioned conventional diversity receiver includes the processes of exponential conversion and multiplication, it has a complicated logic circuit or a high-speed digital signal processor (DSP, Digital Signal Processor).
However, the circuit configuration is complicated and the manufacturing cost is high.

This diversity receiver is required to have a simple circuit structure and a low manufacturing cost.

An object of the present invention is to provide a diversity receiver which can be realized with a simple structure and simple arithmetic processing.

[0009]

In order to solve this problem, the present invention provides a receiving section for receiving a reception signal of an antenna and outputting a reception field strength signal and a baseband signal, and a reception field strength signal level. It is configured to have a weighting circuit that performs a corresponding weighting on the baseband signal by bit shifting, and an adding circuit that adds the weighted baseband signals and outputs a baseband output signal.

As a result, a diversity receiver that can be realized with a simple structure and simple arithmetic processing can be obtained.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is based on a receiving section for receiving a reception signal of an antenna and outputting a reception electric field strength signal and a baseband signal, and a reception section according to the level of the reception electric field strength signal. And a weighting circuit for performing a weighting on the baseband signal by bit shifting, and an addition circuit for adding the weighted baseband signals and outputting a baseband output signal. This has the effect that weighting is performed by bit shifting.

According to a second aspect of the invention, in the first aspect of the invention, the weighting circuit and the adding circuit are realized by a microprocessor, and the weighting of the baseband signal by bit shift is performed. It has the effect of being performed by a microprocessor.

According to a third aspect of the invention, in the first aspect of the invention, the receiving section has an attenuator on the input side, and the attenuation amount of the attenuator is added to the value of the received electric field strength signal. This has the effect that similar arithmetic processing is performed regardless of the presence or absence of an attenuator.

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. (Embodiment 1) FIG. 1 is a block diagram showing a diversity receiver according to an embodiment of the present invention. In FIG. 1, 1 and 2 are antennas, 3 and 4 are receivers, and 5 is A / D.
The converters 10 are adders, which are similar to those in FIG. 21, 2
Reference numeral 2 is a subtracter that outputs a difference signal between the two A / D converted RSSI signals, and 23 and 24 are weighting circuits that perform right bit shift according to the values of the difference signals output from the subtracters 21 and 22. It is a bit shifter.

The operation of the diversity receiver configured as described above will be described below. As in the case of FIG. 3, the RSSI values at the antennas 1 and 2 are s1 and s2, the baseband signals output from the receiving units 3 and 4 are b1 and b2, and the reception signals output from the receiving units 3 and 4 are receiving signals. The electric field strength signals are a1 and a2. When the baseband signals are combined at the maximum ratio, that is, when the weighting of the square of s1 and s2 is performed, the value of the combined output signal s from the adder 10 is (s1 / s) when s1 <s2.
2) ² b1 + b2, b1 + (s2 / s when s1> s2
1) It is only necessary to obtain a value of ² b2 (any value may be used when s1 = s2).

On the other hand, the RSS output from the receivers 3 and 4
Since the values of the I signals a1 and a2 are values proportional to the dB value, the subtracter 21 that subtracts the value of the RSSI signal a1 from the value of the RSSI signal a2 is 20log (s2) −20lo.
The subtraction signal c1 having a value of g (s1) is output. When the value of the subtraction signal c1 is "negative" or "0", the bit shifter 23 outputs the baseband signal b1 as it is.
When the value of the subtraction signal c1 is “positive”, the value of c1 is 3
Every time the dB increases, the baseband signal b1 is multiplied by 1/2,
That is, the baseband signal b1 is shifted to the right by 1 bit. The subtractor 22 and the bit shifter 24 are also the subtractor 2
1, the same operation as the bit shifter 23 is performed.

Finally, the weighted baseband signals d1 and d2 from the bit shifters 23 and 24 are added to the adder 10
Add with and output.

For example, 20log (s1) = 20 [d
B], 20log (s2) = 5 [dB], the subtraction signal c1 output from the subtractor 21 becomes "negative", and therefore the bit shifter 23 outputs the baseband signal b1 as it is. Since the subtraction signal c2 becomes 15 dB, the bit shifter 24 changes the baseband signal b2 to 5 dB.
Shift right bit and output. At this time, "0" is put in MSB. By adding the weighted baseband signals d1 and d2 output from the bit shifters 23 and 24 by the adder 10, the baseband signal b1 and
It is possible to obtain the combined output signal s in which b2 is weighted. In this way, it is possible to obtain the baseband output signal (combined output signal) s, which is composed by adding the squared weight, with a simple configuration of the adder 10 and the bit shifters (weighting circuits) 23 and 24.

When a variable attenuator is provided on the input side of the receivers 3 and 4, the receivers 3 and 4 calculate the amount of attenuation by RSS.
Add to I value.

As described above, according to the present embodiment, the weighting of the baseband signals b1 and b2 can be performed by a simple operation called bit shift.
Weighting can be realized by a simple configuration of 0 and the bit shifters 23 and 24 and a simple arithmetic process of bit shift.

(Second Embodiment) FIG. 2 is a block diagram showing a diversity receiver according to a second embodiment of the present invention. In FIG. 2, reference numerals 1 and 2 are antennas, 3 and 4 are receivers, and 5 is an A / D converter. These are the same as those in FIG. Reference numeral 31 is a microprocessor that performs the above-described weighting and addition by software.

The operation of the diversity receiver configured as above will be described.

The operation of the microprocessor 31 is performed by the subtracters 21 and 22 and the bit shifter 2 in the first embodiment.
The operations performed by 3, 24 and the adder 10 are performed by the operation defined by software. Since there is no multiplication operation in such an operation of the microprocessor 31, the above operation can be sufficiently realized by an inexpensive general-purpose microcomputer.

Although the microprocessor 31 operated by software is described in the present embodiment, a dedicated processor may be used instead of the processor 31. In this case, the program is unnecessary.

As described above, according to this embodiment, the weighting and addition operations of the baseband signals b1 and b2 are performed by the microprocessor 31, so that the microprocessor 31 has a simple structure and bit shift. Weighting can be realized by arithmetic processing with simple software.

[0026]

As described above, according to the diversity receiver of the present invention, the weighting of the baseband signal can be performed by a simple operation called bit shift.
An advantageous effect that a diversity receiver capable of realizing weighting with a simple configuration and simple arithmetic processing can be realized can be obtained. Further, by realizing the weighting circuit and the adding circuit by the microprocessor, there is an advantageous effect that it is possible to realize a diversity receiver in which arithmetic processing such as weighting and addition can be easily changed. Furthermore, since the receiving unit has an attenuator on the input side and the attenuation amount of the attenuator is added to the value of the received electric field strength signal, regardless of the presence or absence of the attenuator,
An advantageous effect that a diversity receiver capable of performing similar arithmetic processing can be realized is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a diversity receiver according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a diversity receiver according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional diversity receiver.

[Explanation of symbols]

 1, 2 antennas 3, 4 receiver 5 A / D converter 10 adder 21, 22 subtractor 23, 24 bit shifter (weighting circuit) 31 microprocessor

Claims (3)

[Claims] 1. A receiver for receiving a received signal of an antenna and outputting a received electric field strength signal and a baseband signal, and weighting according to the level of the received electric field strength signal by bit-shifting the baseband signal. A diversity receiver having a weighting circuit for performing the addition and an adder circuit for adding the weighted baseband signals and outputting a baseband output signal. 2. The diversity receiver according to claim 1, wherein the weighting circuit and the adding circuit are realized by a microprocessor. 3. The diversity receiver according to claim 1, wherein the receiving section has an attenuator on the input side, and adds the attenuation amount of the attenuator to the value of the received electric field strength signal.