JPH09162003A - Positive temperature coefficient thyristor device - Google Patents

Positive temperature coefficient thyristor device

Info

Publication number
JPH09162003A
JPH09162003A JP34732095A JP34732095A JPH09162003A JP H09162003 A JPH09162003 A JP H09162003A JP 34732095 A JP34732095 A JP 34732095A JP 34732095 A JP34732095 A JP 34732095A JP H09162003 A JPH09162003 A JP H09162003A
Authority
JP
Japan
Prior art keywords
temperature
semiconductor ceramic
curie point
ptc element
positive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP34732095A
Other languages
Japanese (ja)
Inventor
Atsushi Hirano
篤 平野
Shigeyuki Kuroda
茂之 黒田
Kenji Tanaka
謙次 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP34732095A priority Critical patent/JPH09162003A/en
Publication of JPH09162003A publication Critical patent/JPH09162003A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To prevent the generation of a thermal-stress breaking due to a temperature difference between the temperature of the interior of a semiconductor ceramic element having positive temperature characteristics and the temperature of the surface part of the element at the time when an abrupt voltage is applied to the element by a method wherein the temperature of the element is held at a temperature higher than room temperatures by heating the element. SOLUTION: A positive temperature coefficient thyristor device 11 is constituted into a structure wherein a semiconductor ceramic element (PTC element) 3 for overcurrent protection use, which shows positive temperature characteristics, and a heater (a heating element) 12 are housed in a case 14. The heater 12 is applied by a current through lead terminals 13 and the temperature in the case 14 is made higher than room temperatures and is held at a temperature lower than a Curie point temperature. As this result, the element 3 is also held at the same temperature as that in the case 14. The nearer the temperature of the element 3 is the Curie point temperature, the better this temperature is and specially, if the temperature in the case 14 or the temperature which is held by the element 3, and the Curie point temperature are respectively assumed T and Tc, the temperature is adjusted by the heater 12 so as to satisfy the condition of Tc-60 deg.C<T<Tc.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、正の温度特性を示
す半導体セラミック素子を有する正特性サーミスタ(P
TC)装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a positive temperature coefficient thermistor (P) having a semiconductor ceramic element exhibiting positive temperature characteristics.
TC) device.

【0002】[0002]

【従来の技術】正の温度特性を示す半導体セラミック素
子(以下、PTC素子という)を用いた従来の正特性サ
ーミスタ装置としては、たとえば図2に示すような構造
のものが知られている。この正特性サーミスタ装置1に
あっては、半導体セラミックからなる素子本体3aの相
対向する両面に電極2を設け、当該各電極2にリード線
4をそれぞれ半田付け等によって電気的に接続してPT
C素子3が形成されており、PTC素子3は外装樹脂5
で被覆されている。
2. Description of the Related Art As a conventional positive temperature coefficient thermistor device using a semiconductor ceramic element exhibiting a positive temperature characteristic (hereinafter referred to as a PTC element), for example, one having a structure shown in FIG. 2 is known. In this positive temperature coefficient thermistor device 1, electrodes 2 are provided on opposite sides of an element body 3a made of a semiconductor ceramic, and lead wires 4 are electrically connected to each electrode 2 by soldering or the like to obtain a PT.
The C element 3 is formed, and the PTC element 3 has the exterior resin 5
It is covered with.

【0003】このようなPTC素子は、素子抵抗と温度
との関係を示す図1に示されているように、キューリー
点温度以上で抵抗値が急激に増加するため、回路の過電
流保護など種々の用途に用いられている。すなわち、P
TC素子に過電流が流れるとPTC素子の抵抗によりP
TC素子の温度が急上昇してその抵抗値が非常に大きく
なるので、PTC素子を挿入されている回路の電流が遮
断され、回路が過電流から保護される。
In such a PTC element, as shown in FIG. 1, which shows the relationship between the element resistance and the temperature, the resistance value sharply increases above the Curie point temperature, so that various kinds of protection such as circuit overcurrent protection are possible. Is used for. That is, P
When an overcurrent flows through the TC element, the resistance of the PTC element causes P
Since the temperature of the TC element suddenly rises and its resistance value becomes very large, the current of the circuit in which the PTC element is inserted is cut off and the circuit is protected from overcurrent.

【0004】[0004]

【発明が解決しようとする課題】上記のような正特性サ
ーミスタ装置のリード線を通してPTC素子に急激に電
圧を印加すると、PTC素子が発熱し、PTC素子が破
壊する事故がしばしば起きていた。
When a voltage is suddenly applied to the PTC element through the lead wire of the positive temperature coefficient thermistor device as described above, the PTC element heats up and the PTC element often breaks down.

【0005】そこで、本発明の発明者らは、通電時にお
けるPTC素子の発熱の様子を調べるため、赤外線温度
解析装置を用いてPTC素子内部の温度分布を測定し
た。図3はPTC素子3の内部の温度分布を等温線6を
用いて示した図である。図3に示されているように、P
TC素子の内部では温度が高く、PTC素子の表面では
温度が低くなっており、素子破壊は、このような素子内
部と表面部との温度差による熱応力破壊によって起きる
ものであると考えられる。
Therefore, the inventors of the present invention measured the temperature distribution inside the PTC element by using an infrared temperature analysis device in order to investigate the heat generation state of the PTC element during energization. FIG. 3 is a diagram showing the temperature distribution inside the PTC element 3 using the isotherms 6. As shown in FIG.
Since the temperature is high inside the TC element and the temperature is low on the surface of the PTC element, it is considered that the element destruction is caused by the thermal stress destruction due to the temperature difference between the inside of the element and the surface portion.

【0006】そこで、詳細に検討すると、素子破壊のメ
カニズムは次のように考えることができた。PTC素子
に急激に電圧を印加すると、PTC素子に流れる電流に
よってPTC素子が発熱するが、素子内部と表面部の間
における熱放散性の違いによって素子内部の温度が表面
部の温度よりも高くなる。素子内部の温度が高くなる
と、素子内部の抵抗率は表面部よりも高くなるので、ま
すます素子内部における発熱量が大きくなり、熱放散性
と素子内部の抵抗率の増大によって素子内部と表面部と
の間の温度差が拡大し、素子内部と表面部との間の熱膨
張寸法の差によってPTC素子が破壊に至る。
[0006] Then, when examined in detail, the mechanism of device destruction could be considered as follows. When a voltage is suddenly applied to the PTC element, the PTC element generates heat due to a current flowing through the PTC element, but the temperature inside the element becomes higher than the temperature at the surface due to a difference in heat dissipation between the inside and the surface. . When the temperature inside the element increases, the resistivity inside the element becomes higher than that at the surface, so the amount of heat generated inside the element further increases, and the heat dissipation and the increase in the resistivity inside the element increase the temperature inside the element and the surface. The temperature difference between the PTC element and the PTC element is broken due to the difference in thermal expansion between the inside and the surface of the element.

【0007】本発明は、本発明の発明者らが得た上記知
見に基づいてなされたものであり、その目的とするとこ
ろは、正の温度特性を示す半導体セラミック素子の素子
内部と表面部の温度差による熱応力破壊を回避し、耐熱
破壊特性に優れた正特性サーミスタ装置を提供すること
にある。
The present invention was made on the basis of the above findings obtained by the inventors of the present invention. The purpose of the present invention is to detect the inside and the surface of the semiconductor ceramic element showing a positive temperature characteristic. An object of the present invention is to provide a positive temperature coefficient thermistor device which is excellent in heat resistance fracture characteristics while avoiding thermal stress fracture due to temperature difference.

【0008】[0008]

【課題を解決するための手段】請求項1に記載の正特性
サーミスタ装置は、正の温度特性を示す半導体セラミッ
ク素子と、当該半導体セラミック素子を室温よりも高く
キュリー点以下の温度に保つための加熱素子と、を備え
たことを特徴としている。
A positive temperature coefficient thermistor device according to a first aspect of the present invention includes a semiconductor ceramic element exhibiting a positive temperature characteristic, and a semiconductor ceramic element for maintaining the temperature higher than room temperature and lower than the Curie point. And a heating element.

【0009】請求項2に記載の正特性サーミスタ装置
は、正の温度特性を示す半導体セラミック素子と、当該
半導体セラミック素子の温度を、 Tc−60℃<T<Tc ただし、Tc:前記半導体セラミック素子のキュリー点
温度 T:前記半導体セラミック素子の温度 に保つための加熱素子と、を備えたことを特徴としてい
る。
In the positive temperature coefficient thermistor device according to a second aspect of the present invention, the temperature of the semiconductor ceramic element exhibiting a positive temperature characteristic is Tc-60 ° C <T <Tc, where Tc is the semiconductor ceramic element. Curie point temperature T: a heating element for maintaining the temperature of the semiconductor ceramic element.

【0010】請求項3に記載の正特性サーミスタ装置
は、90℃以上のキュリー点温度を有し、正の温度特性
を示す半導体セラミック素子と、当該半導体セラミック
素子の温度を、 Tc−40℃<T<Tc ただし、Tc:前記半導体セラミック素子のキュリー点
温度 T:前記半導体セラミック素子の温度 に保つための加熱素子と、を備えたことを特徴としてい
る。
A positive temperature coefficient thermistor device according to a third aspect of the present invention has a Curie point temperature of 90 ° C. or higher and shows a positive temperature characteristic of a semiconductor ceramic element, and the temperature of the semiconductor ceramic element is Tc-40 ° C. < T <Tc, where Tc: Curie point temperature of the semiconductor ceramic element, T: heating element for maintaining the temperature of the semiconductor ceramic element.

【0011】[0011]

【作用】本発明の正特性サーミスタ装置によれば、加熱
素子で正の温度特性を有する半導体セラミック素子を加
熱することによって当該半導体セラミック素子の温度を
室温よりも高い温度に保持しているので、素子内部と表
面部との間の温度差を小さくすることができる。従っ
て、急激に電圧が加わった場合でも、当該半導体セラミ
ック素子の内部と表面部との間の熱膨張寸法の差に起因
する熱応力破壊を回避することができ、耐熱破壊特性に
優れた正特性サーミスタ装置を得ることができる。特
に、良好なフラッシュ耐圧試験結果を得ることができ
る。
According to the positive temperature coefficient thermistor device of the present invention, the temperature of the semiconductor ceramic element having a positive temperature characteristic is kept higher than room temperature by heating the semiconductor ceramic element having the positive temperature characteristic. The temperature difference between the inside of the element and the surface portion can be reduced. Therefore, even when a voltage is suddenly applied, it is possible to avoid the thermal stress fracture due to the difference in thermal expansion dimension between the inside and the surface of the semiconductor ceramic element, and the positive characteristic excellent in the thermal breakdown resistance is obtained. A thermistor device can be obtained. Particularly, good flash withstand voltage test results can be obtained.

【0012】また、半導体セラミック素子の温度はキュ
リー点温度以下となっているから、半導体セラミック素
子の抵抗値が高抵抗となるのを避けることができ、温度
変化によっても抵抗値が不安定になることがない。
Further, since the temperature of the semiconductor ceramic element is lower than the Curie point temperature, it is possible to avoid the resistance value of the semiconductor ceramic element from becoming high resistance, and the resistance value becomes unstable due to the temperature change. Never.

【0013】また、半導体セラミック素子の温度Tを、
Tc−60℃<T<Tcの範囲に保持すれば、キュリー
点に近い温度領域に半導体セラミック素子を保持するこ
とができ、正特性サーミスタ装置のフラッシュ耐圧値を
高くすることができる。
The temperature T of the semiconductor ceramic element is
If the temperature is maintained in the range of Tc-60 ° C. <T <Tc, the semiconductor ceramic element can be held in a temperature region close to the Curie point, and the flash withstand voltage value of the positive temperature coefficient thermistor device can be increased.

【0014】さらには、通常の過電流保護用の素子はキ
ュリー点温度Tcが90℃以上であるので、半導体セラ
ミック素子の温度Tを、Tc−40℃<T<Tcの範囲
に保持すれば、通常では得ることができないような大き
なフラッシュ耐圧値を得ることができる。
Further, since the Curie point temperature Tc of an ordinary overcurrent protection element is 90 ° C. or higher, if the temperature T of the semiconductor ceramic element is kept within the range of Tc-40 ° C. <T <Tc. It is possible to obtain a large flash withstand voltage value that cannot be obtained normally.

【0015】[0015]

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

(本発明の一実施形態)図4は本発明の一実施形態によ
る正特性サーミスタ装置11を示す概略図である。この
正特性サーミスタ装置11は、過電流保護用の正の温度
特性を示す半導体セラミック素子(PTC素子)3とヒ
ーター(加熱素子)12とをケース14内に納めたもの
である。PTC素子3は回路(図示せず)に直列に接続
され、過電流が流れたときに電流を遮断するように使用
される。また、ヒーター12は、リード端子13から通
電され、ケース14内の温度を室温よりも高く、キュリ
ー点温度よりも低い温度に保持し、この結果PTC素子
3の温度も同じ温度に保持する。この温度TはPTC素
子3のキュリー点温度Tcに近いほど良く、特に、ケー
ス14内の温度もしくはPTC素子3の保持される温度
をT、キュリー点温度をTcとすれば、 Tc−60℃<T<Tc となるようにヒーター12で温度調整することが好まし
い。
(One Embodiment of the Present Invention) FIG. 4 is a schematic view showing a positive temperature coefficient thermistor device 11 according to one embodiment of the present invention. The positive temperature coefficient thermistor device 11 has a case 14 in which a semiconductor ceramic element (PTC element) 3 and a heater (heating element) 12 that exhibit positive temperature characteristics for overcurrent protection are housed. The PTC element 3 is connected in series to a circuit (not shown) and is used to cut off the current when an overcurrent flows. Further, the heater 12 is energized from the lead terminal 13, and keeps the temperature inside the case 14 higher than room temperature and lower than the Curie temperature, and as a result, keeps the temperature of the PTC element 3 at the same temperature. This temperature T is better as it is closer to the Curie point temperature Tc of the PTC element 3, and in particular, if the temperature inside the case 14 or the temperature held by the PTC element 3 is T and the Curie point temperature is Tc, then Tc-60 ° C < It is preferable to adjust the temperature with the heater 12 so that T <Tc.

【0016】なお、PTC素子3を加熱して温度保持す
るためのヒーター12も、正特性サーミスタ素子を用い
ることが好ましいが、SiCヒーターやその他のヒータ
ーを用いても良い。
As the heater 12 for heating the PTC element 3 to maintain the temperature, it is preferable to use a positive temperature coefficient thermistor element, but a SiC heater or another heater may be used.

【0017】(PTC素子のフラッシュ耐圧試験)次
に、PTC素子を恒温槽に入れてPTC素子の温度をさ
まざまな温度に保持し、各温度ににおけるPTC素子の
フラッシュ耐圧値(V)を求めた。この結果を図5に示
す。ここで、フラッシュ耐圧試験とは、瞬時にパルス状
の過電圧を印加してPTC素子が破壊するか否かを調べ
るものであって、フラッシュ耐圧値とは、PTC素子が
破壊に至る手前の耐電圧をさす。また、図1に示したも
のも、本発明の発明者らによって測定されたものであっ
て、恒温槽内でPTC素子の温度を様々な温度に保持し
て、各温度における抵抗値を測定したものである。
(PTC element flash withstand voltage test) Next, the PTC element was placed in a constant temperature bath to keep the temperature of the PTC element at various temperatures, and the flash withstand voltage value (V) of the PTC element at each temperature was obtained. . The result is shown in FIG. Here, the flash withstand voltage test is to examine whether or not the PTC element is destroyed by applying a pulsed overvoltage instantaneously. The flash withstand voltage value is the withstand voltage before the PTC element is destroyed. Point out. Further, the one shown in FIG. 1 was also measured by the inventors of the present invention, in which the temperature of the PTC element was kept at various temperatures in a constant temperature bath, and the resistance value at each temperature was measured. It is a thing.

【0018】図5から分かるように、PTC素子の温度
は、より高温に保持した方がフラッシュ耐圧値が大きく
なることが分かる。これは、PTC素子を室温よりも高
温に保持したことにより、急激に電圧を印加された際の
素子内部と表面部の温度差が縮小し、その熱膨張による
寸法変化が小さくなり、発生する熱応力が小さくなるた
めであると考えられる。
As can be seen from FIG. 5, the flash withstand voltage value increases as the temperature of the PTC element is kept higher. This is because by holding the PTC element at a temperature higher than room temperature, the temperature difference between the inside of the element and the surface portion when a voltage is suddenly applied is reduced, the dimensional change due to thermal expansion is reduced, and the heat generated is reduced. It is considered that this is because the stress becomes small.

【0019】従って、上記正特性サーミスタ装置11の
ように、ヒーター12で加熱することによりPTC素子
3の温度Tを室温以上、キュリー点温度Tc以下に保持
した場合にも、PTC素子3のフラッシュ耐圧値を大き
くし、PTC素子3に熱応力破壊が起こりにくいように
できると考えられる。しかしながら、PTC素子3をキ
ューリー点温度Tc以上に保持した場合には、図1から
分かるように、PTC素子3が高抵抗となるうえ、抵抗
値の温度変化率が大きいために抵抗値の安定性が損われ
る。よって、PTC素子3はキュリー点温度Tc以下で
できるだけキュリー点温度Tcに近い温度に保持するこ
とが好ましいといえる。
Therefore, even when the temperature T of the PTC element 3 is maintained at room temperature or higher and Curie point temperature Tc or lower by heating with the heater 12 as in the positive temperature coefficient thermistor device 11, the flash withstand voltage of the PTC element 3 is maintained. It is considered that the value can be increased to prevent thermal stress destruction of the PTC element 3. However, when the PTC element 3 is kept at the Curie point temperature Tc or higher, as shown in FIG. 1, the PTC element 3 has a high resistance and the resistance value is stable because the temperature change rate of the resistance value is large. Is damaged. Therefore, it can be said that it is preferable that the PTC element 3 be maintained at a temperature as close to the Curie point temperature Tc as possible, below the Curie point temperature Tc.

【0020】(実施例と比較例におけるフラッシュ耐圧
値の比較)そこで、恒温槽でなく、実際の正特性サーミ
スタ装置によりフラッシュ耐圧値試験を行なって効果を
確認した。実施例の正特性サーミスタ装置11は、図4
に示したような構造のものであって、PTC素子3とし
ては、キュリー点温度Tcが約120℃のものを用い
た。また、ケース14内はヒーター12により100℃
に保持した。この条件のもとで、PTC素子3の抵抗値
とフラッシュ耐圧値を測定した。この測定結果では、表
1に示すように、PTC素子3の抵抗値は6Ω、フラッ
シュ耐圧値は490Vであった。
(Comparison of Flash Withstand Voltage Values in Example and Comparative Example) Therefore, the flash withstand voltage value test was conducted using an actual positive temperature coefficient thermistor device instead of the constant temperature bath to confirm the effect. The positive temperature coefficient thermistor device 11 of the embodiment is shown in FIG.
The PTC element 3 having the structure as shown in FIG. 3 and having a Curie point temperature Tc of about 120 ° C. was used. The inside of the case 14 is heated to 100 ° C by the heater 12.
Held. Under these conditions, the resistance value and flash withstand voltage value of the PTC element 3 were measured. In this measurement result, as shown in Table 1, the resistance value of the PTC element 3 was 6Ω and the flash withstand voltage value was 490V.

【0021】[0021]

【表1】 [Table 1]

【0022】同様にして、ヒーターを有しない正特性サ
ーミスタ装置を用い、キュリー点温度Tcが約120℃
のPTC素子を室温(25℃)に保持し、PTC素子の
抵抗値とフラッシュ耐圧値を測定した。この測定結果で
は、表1に示すように、PTC素子の抵抗値は6Ω、フ
ラッシュ耐圧値は280Vであった。
Similarly, a Curie point temperature Tc of about 120 ° C. is obtained by using a positive temperature coefficient thermistor device having no heater.
While maintaining the PTC element at room temperature (25 ° C.), the resistance value and flash withstand voltage value of the PTC element were measured. In this measurement result, as shown in Table 1, the resistance value of the PTC element was 6Ω and the flash withstand voltage value was 280V.

【0023】従って、表1から分かるように、PTC素
子をキュリー点温度Tcに近い温度に保持することによ
りフラッシュ耐圧値を向上させることができる。これ
は、急激に電圧を印加された際の素子内部と表面部の温
度差が縮小されることにより、耐熱破壊特性に優れたも
のが得られると理解される。PTC素子の保持温度Tと
しては、この実施例の場合にも当てはまるが、そのキュ
リー点温度Tcが90℃以上であるとすると、Tc−4
0℃<T<Tcとするのが、フラッシュ耐圧値の向上に
特に望ましい。
Therefore, as can be seen from Table 1, the flash withstand voltage value can be improved by holding the PTC element at a temperature close to the Curie temperature Tc. It is understood that the difference in temperature between the inside of the element and the surface portion when a voltage is suddenly applied is reduced, so that a material having excellent thermal breakdown resistance can be obtained. The holding temperature T of the PTC element also applies to this embodiment, but if the Curie point temperature Tc is 90 ° C. or higher, Tc-4
Setting 0 ° C. <T <Tc is particularly desirable for improving the flash withstand voltage value.

【0024】[0024]

【発明の効果】本発明によれば、加熱素子で正の温度特
性を有する半導体セラミック素子を加熱して当該半導体
セラミック素子の温度を室温よりも高くキュリー点より
も低い温度に保持しているので、素子内部と表面部との
間の温度差を小さくすることができ、素子内部と表面部
の間の熱膨張寸法の差に基因する熱応力破壊を回避する
ことができる。特に、良好なフラッシュ耐圧試験結果を
得ることができ、正特性サーミスタ装置の信頼性を向上
させることができる。また、(PTC素子が作動してい
ない時の外気)温度変化による抵抗値の変動がなくな
る。
According to the present invention, the semiconductor ceramic element having a positive temperature characteristic is heated by the heating element to keep the temperature of the semiconductor ceramic element at a temperature higher than room temperature and lower than the Curie point. The temperature difference between the inside of the element and the surface portion can be reduced, and thermal stress fracture due to the difference in the thermal expansion dimension between the inside of the element and the surface portion can be avoided. In particular, a good flash withstand voltage test result can be obtained, and the reliability of the positive temperature coefficient thermistor device can be improved. Further, the fluctuation of the resistance value due to the temperature change (outside air when the PTC element is not operating) is eliminated.

【図面の簡単な説明】[Brief description of the drawings]

【図1】PTC素子における温度と抵抗値との関係を示
す図である。
FIG. 1 is a diagram showing a relationship between a temperature and a resistance value in a PTC element.

【図2】従来の正特性サーミスタ装置を示す概略断面図
である。
FIG. 2 is a schematic sectional view showing a conventional positive temperature coefficient thermistor device.

【図3】PTC素子の内部における通電時の温度分布を
等温線により示す図である。
FIG. 3 is a diagram showing the temperature distribution in the PTC element during energization by isothermal lines.

【図4】本発明の一実施形態による正特性サーミスタ装
置を示す概略図である。
FIG. 4 is a schematic diagram showing a positive temperature coefficient thermistor device according to an embodiment of the present invention.

【図5】PTC素子の温度とフラッシュ耐圧値との関係
を示す図である。
FIG. 5 is a diagram showing the relationship between the temperature of the PTC element and the flash withstand voltage value.

【符号の説明】[Explanation of symbols]

3 PTC素子(正の温度特性を示す半導体セラミッ
ク素子) 12 ヒーター 14 ケース
3 PTC element (semiconductor ceramic element showing positive temperature characteristics) 12 heater 14 case

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 正の温度特性を示す半導体セラミック素
子と、 当該半導体セラミック素子を室温よりも高くキュリー点
以下の温度に保つための加熱素子と、を備えた正特性サ
ーミスタ装置。
1. A positive temperature coefficient thermistor device comprising: a semiconductor ceramic element exhibiting a positive temperature characteristic; and a heating element for keeping the semiconductor ceramic element at a temperature higher than room temperature and lower than the Curie point.
【請求項2】 正の温度特性を示す半導体セラミック素
子と、 当該半導体セラミック素子の温度を、 Tc−60℃<T<Tc ただし、Tc:前記半導体セラミック素子のキュリー点
温度 T:前記半導体セラミック素子の温度 に保つための加熱素子と、を備えた正特性サーミスタ装
置。
2. A semiconductor ceramic element exhibiting a positive temperature characteristic, and a temperature of the semiconductor ceramic element is Tc−60 ° C. <T <Tc, where Tc: Curie point temperature of the semiconductor ceramic element T: the semiconductor ceramic element A positive temperature coefficient thermistor device equipped with a heating element for maintaining the temperature of.
【請求項3】 90℃以上のキュリー点温度を有し、正
の温度特性を示す半導体セラミック素子と、 当該半導体セラミック素子の温度を、 Tc−40℃<T<Tc ただし、Tc:前記半導体セラミック素子のキュリー点
温度 T:前記半導体セラミック素子の温度 に保つための加熱素子と、を備えた正特性サーミスタ装
置。
3. A semiconductor ceramic element having a Curie point temperature of 90 ° C. or higher and exhibiting positive temperature characteristics, and the temperature of the semiconductor ceramic element is Tc−40 ° C. <T <Tc, where Tc: the semiconductor ceramic Curie point temperature of element T: Positive temperature coefficient thermistor device provided with a heating element for maintaining the temperature of the semiconductor ceramic element.
JP34732095A 1995-12-13 1995-12-13 Positive temperature coefficient thyristor device Pending JPH09162003A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34732095A JPH09162003A (en) 1995-12-13 1995-12-13 Positive temperature coefficient thyristor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34732095A JPH09162003A (en) 1995-12-13 1995-12-13 Positive temperature coefficient thyristor device

Publications (1)

Publication Number Publication Date
JPH09162003A true JPH09162003A (en) 1997-06-20

Family

ID=18389431

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34732095A Pending JPH09162003A (en) 1995-12-13 1995-12-13 Positive temperature coefficient thyristor device

Country Status (1)

Country Link
JP (1) JPH09162003A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009258430A (en) * 2008-04-17 2009-11-05 Sony Corp Discharge apparatus, method of controlling discharge apparatus, and imaging apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009258430A (en) * 2008-04-17 2009-11-05 Sony Corp Discharge apparatus, method of controlling discharge apparatus, and imaging apparatus
US8289003B2 (en) 2008-04-17 2012-10-16 Sony Corporation Discharge apparatus, method of controlling discharge apparatus, and imaging apparatus

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