JPH09161470A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate a terminal exclusively used for resetting by providing a memory cell a clock detection circuit and a reset signal generation circuit to output a signal for resetting FF based on outputs of, a clock detection circuit. SOLUTION: A reset signal generation circuit 14 receives a reset signal outputted from a clock detection circuit 13 to supply the reset signal to FFs 6-8. While a clock CLK is supplied from outside, the reset signal is turned to an L level. Then, when the CLK fails to be supplied beyond a preset time T, the entry of standby state is judged and the reset signal goes to an H level. When the CLK is inputted again after the reset signal shifts to the H level, the reset signal is turned to the L level. Thus, the reset signal is generated within a semiconductor memory by detecting the presence of a clock input thereby eliminating a terminal exclusively used for resetting while making complicated control of input signals unnecessary.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a flip-flop built-in type semiconductor memory device.

[0002]

2. Description of the Related Art FIG. 4 shows a configuration of a conventional semiconductor memory device in which flip-flops are respectively connected to a plurality of input / output terminals and a clock is externally supplied to each flip-flop (for example, Japanese Patent Laid-Open No. 3-100994). (See FIG. 3 of the publication).

Referring to FIG. 4, a conventional semiconductor memory device includes a memory cell array 12 and a memory cell array 12 which receives an address signal and decodes a row address to form a word line.
A row decoder 9 for outputting to the cell array 12, a column decoder 11 for inputting an address signal, decoding a column address and outputting as a column selection signal to the memory cell array 12, and a digit line of the memory cell array 12. The sense amplifier 10 connected to the
Flip-flops 6 to 6 connected to these terminals 2 to 5
8 and a terminal 1 for inputting the clock signal CLK supplied to each of the flip-flops 6 to 8 from the outside. The address ADR is input to the terminal 2, and the input (write) data is input to the terminal 3. Further, read (output) data is output from the terminal 5, and a reset signal is input to the terminal 4.

That is, flip-flops (FF) 6 and 7 are respectively connected to terminals 2 and 3 which are input terminals (address and input data terminals) for access, and the flip-flops 6 and 7 are connected via the terminal 1. External clock is supplied.

The address signal ADR supplied to the terminal 2 is passed through the flip-flop 6 to the row decoder 9,
It is supplied to the column decoder 11, and the address of the memory cell is designated by both decoders.

Further, the write data supplied to the terminal 3 is supplied to the sense amplifier 10 via the flip-flop 7.

The data read from the memory cell is detected (amplified) by the sense amplifier 10, and the output of the sense amplifier 10 is flip-flop synchronized with the external clock CLK input through the terminal 1. It is output from 8.

In the conventional semiconductor memory device shown in FIG. 4, since the memory cell is accessed through the flip-flop, memory access (data writing and reading) is performed in synchronization with the external clock CLK.

The flip-flops 6, 7, 8
Is reset by being supplied with a reset signal from the outside through the terminal 4. Therefore, the reset-dedicated terminal 4 is required.

The above-mentioned Japanese Patent Laid-Open No. 3-100994 discloses that
For the purpose of providing a memory element with built-in flip-flop capable of omitting the reset-dedicated terminal of the flip-flop, when the input terminal for chip select becomes a level indicating non-selection and the memory cell is in the standby state Further, there has been proposed a configuration of a flip-flop built-in type memory element having a reset signal generating circuit that resets all flip-flops when a predetermined access input terminal (write enable terminal WE) changes to a predetermined level. By generating a reset signal inside the element from an external clock and a write enable signal, the dedicated reset terminal can be omitted.

[0011]

As described above, in the conventional flip-flop built-in type memory shown in FIG.
A dedicated terminal is required to reset each flip-flop, which causes a problem that the manufacturing process becomes complicated and the system becomes large.

In addition, in the memory element with built-in flip-flop (see FIG. 4) described in the above-mentioned Japanese Patent Laid-Open No. 3-100994, which does not require a dedicated reset terminal, a reset signal is generated internally, so that an external clock is used. It is necessary to apply a complicated control to the write enable signal, which is different from the normal operation.

Therefore, the present invention solves the above-mentioned problems of the prior art, facilitates the operation of the control signal with a simple structure, and realizes the deletion of the reset-dedicated terminal of each flip-flop. The purpose is to provide a device.

[0014]

In order to achieve the above object, the present invention provides a plurality of flip-flops which are respectively connected to a plurality of access input / output terminals and are supplied with a clock, and respective access input / output terminals. A memory cell that is accessed through the flip-flop, a clock detection circuit that inputs the clock and detects the presence or absence of the clock, and a reset that outputs a signal that resets the flip-flop based on the output of the clock detection circuit Provided is a semiconductor memory device having a built-in flip-flop, which includes a signal generating circuit.

According to the present invention, in a semiconductor memory device having a built-in flip-flop, all the flip-flops inside the chip are reset when the external clock is not input for a preset time. Therefore, the dedicated reset terminal is not required, special operation of the control signal for generating the reset signal is not required, and the device is downsized by the simple configuration.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a semiconductor memory device according to the first embodiment of the present invention. In FIG. 1, elements having the same or equivalent functions as those in FIG. 4 referred to for describing the conventional semiconductor memory device with built-in flip-flop are designated by the same reference numerals, and the description thereof will be omitted. Only the differences between the conventional semiconductor memory device with built-in flip-flop and this embodiment will be described.

Referring to FIG. 1, in the semiconductor memory device with built-in flip-flop according to the present embodiment, the reset dedicated terminal 4 of FIG. 4 is not provided, and the clock detection circuit 13 and the reset signal generation are provided inside the element. And a circuit 14 are provided.

In the standby mode, the reset signal RESET generated by the reset signal generation circuit 14 is supplied to the flip-flops 6, 7 and 8 so that the plurality of flip-flops 6 can be supplied.
Reset ~ 8 together.

FIG. 2 shows an example of the circuit configuration of the clock detection circuit 13 in this embodiment.

FIG. 3 is an operation waveform diagram for explaining the operation of the semiconductor memory device with built-in flip-flop according to this embodiment.

As shown in FIG. 2, the clock detection circuit 13
Is a non-inversion signal of the clock signal CLK via a two-stage inverter, and this inversion signal is further divided into delay gates (NA
The output signal of the NAND circuit via the ND circuit and the inverter circuit is input to the first RS flip-flop, the inversion signal of the clock signal CLK via the one-stage inverter, and the inversion signal of a plurality of stages. Delay gate (NAND
A second RS flip-flop that receives the output signal of the NAND circuit via the circuit and the inverter circuit),
The output of each RS flip-flop is taken out as a reset signal RESET from the NAND circuit via the inverter circuit. The two-system delay gate circuits are provided to detect the presence or absence of a clock based on the transition of the clock CLK from the High level to the Low level and the transition from the Low level to the High level.

Upon receiving the reset signal RESET output from the clock detection circuit 13, the reset signal generation circuit 14
Supplies a reset signal to the reset terminal of each flip-flop 6-8. In this case, the reset signal generation circuit 1
4 is composed of a buffer circuit as the simplest configuration.

In this embodiment, as shown in the operation waveform diagram of FIG. 3, the reset signal RESET is set to the Low level while the clock CLK is supplied from the outside.

Next, when the clock CLK is not supplied for a preset time T or more, it is determined that the standby state is established,
The reset signal RESET becomes High level (active). The reset signal RESET is High
When the clock CLK is input again after being set to the level, the reset signal RESET is set to the Low level.

The set time T is set to a predetermined time depending on the number of delay gate stages in the clock detection circuit 13.

As described above, according to the embodiment of the present invention, the presence or absence of the clock input is detected, and the reset signal is generated inside the semiconductor memory device. Therefore, the dedicated reset terminal can be omitted and the reset signal can be omitted. Since the signal generation is controlled only by the presence or absence of the clock signal, complicated control of the input signal is unnecessary. The semiconductor memory device according to the embodiment of the present invention is a flip-flop built-in DRAM (dynamic random access memory).
Of course, the present invention can be applied to other semiconductor memory devices having a built-in flip-flop.

[0028]

As described above, according to the semiconductor memory device of the present invention, since the built-in flip-flop is reset inside the element at the time of memory standby, the reset-dedicated terminal is omitted. be able to.

Therefore, according to the present invention, the number of signal lines for controlling the memory element is reduced, and as a result, the manufacturing process of the semiconductor memory device is further simplified and the device is further downsized (chip size). It has the advantage that it can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a circuit configuration of a clock detection circuit according to an embodiment of the present invention.

FIG. 3 is a waveform diagram for explaining the operation of the embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a conventional semiconductor memory device having a built-in flip-flop.

[Explanation of symbols]

 1 clock input terminal 2 address input terminal 3 data input terminal 5 data output terminal 6 to 8 flip-flop 9 row decoder 10 sense amplifier 11 column decoder 12 memory cell array 13 clock detection circuit 14 reset signal generation circuit

Claims (2)

[Claims] 1. A plurality of flip-flops connected to a plurality of access input / output terminals and supplied with a clock, respective access input / output terminals, a memory cell accessed through the flip-flops, A built-in flip-flop, comprising: a clock detection circuit that inputs a clock and detects the presence or absence of the clock; and a reset signal generation circuit that outputs a signal that resets the flip-flop based on the output of the clock detection circuit. Type semiconductor memory device. 2. The clock detection circuit comprises a circuit in which a plurality of delay gates each having the clock as an input are connected in cascade, and when the clock input does not come in for a predetermined time determined by the number of stages of the delay gate. 2. The flip-flop built-in type semiconductor memory device according to claim 1, wherein the reset signal is controlled to be active.