JPH09160597A - Analog post filter for voice decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the amount of operations to reduce the power consumed by providing a post filter using an analog circuit. SOLUTION: Decoded aural signals of a decoder CPU 11 are converted into analog form by a D/A converter 12. The decoded aural signals converted into analog form are delayed by an analog delay circuit 13 for output to a plurality of taps as delayed signals. These plural outputs are weighted and synthesized by a weighting synthesizing circuit 14 by means of an auditory weighting factor for an LPO analytical filter, the factor being set by a decoder CPU 11. This weighted synthesized signal is added to the analog decoded aural signal by an adder 15, and from this total output, a post-filter output is subtracted by a subtractor 16, this subtracted output is delayed by a delay circuit 17, delayed signals are output to the plurality of taps, and weighting synthesis is carried out by a weighting synthesizing circuit 18 by means of an auditory weighting factor for an LPC synthesizing filter. This synthesized output serves as a post- filter output signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a post filter used in a speech codec.

[0002]

2. Description of the Related Art A post filter used in a voice codec has a function of enhancing formant information of an output voice signal and improving clarity. In general, a post filter is realized by serially connecting an FIR filter, which is an LPC analysis filter, and a IIR filter, which is an LPC synthesis filter, using coefficients obtained by weighting linear prediction coefficients (hereinafter, LPC coefficients). The means for specifically emphasizing the voice formant using the post filter is realized by the following processing.

FIG. 10 shows the configuration of a conventional post filter. When the encoded audio signal is input, the audio decoder CPU1 causes the decoding unit 2 to perform frame-by-frame (for example, 2
(0 ms) to perform a decoding process to output a decoded voice (ta), and for the LPC analysis filter used for the post filter and LPC synthesis by the following process from the LPC coefficient received as a part of the encoded voice signal information. The perceptual weighting coefficient (f) (yes) for the filter is calculated.

If the speech coding / decoding method in this case is a method in which the LPC coefficient is not transmitted, the LPC coefficient is derived from the decoded speech (ta) by using the known Levinson-Durbin method. It is possible.

The relationship between the LPC coefficient and the perceptual weighting coefficient for the post filter is expressed by the following equations 1 and 2 when the LPC coefficient is nth order.

[0006]

[Equation 1]

[0007]

(Equation 2)

The perceptual weighting coefficients (f) and (f) for the LPC analysis filter and the synthesis filter used for the post filter derived by the above equation are input to the LPC analysis filter 3 and the LPC synthesis filter 4, which form the post filter, respectively. To be done.

The decoded voice (ta) is sent to the LPC analysis filter 3
To the LPC residual signal (L) by the analysis processing and output.

Transfer function H (Z) of LPC analysis filter 3
Is expressed by the following equation 3.

[0011]

(Equation 3)

The internal block of the LPC analysis filter 3 is shown in FIG. As is clear from the figure, the LPC analysis filter 3 has the input as decoded speech (ta) and the coefficient as Wbi.
It is an FIR filter of (i = 1-10) (f).

The LPC residual signal (L) is input to the LPC synthesizing filter 4 and is output as a post filter output (SO) by the synthesizing process.

The transfer function H of this LPC synthesis filter 4
(Z) is expressed by the following equation 4.

[0015]

(Equation 4)

Here, the internal block of the LPC synthesis filter 4 is shown in FIG. As is apparent from the figure, the LPC synthesis filter 4 is an IIR filter whose input is the LPC residual signal (re) and whose coefficient is Wgi (i = 1 to 10) (yes).

As described above, the post filter is a FIR filter and an LPC which are LPC analysis filters using coefficients obtained by weighting linear prediction coefficients (hereinafter referred to as LPC coefficients).
It is a series connection of IIR filters that are synthesis filters.
Therefore, the transfer function H (Z) of the post-filter processing is
It becomes as follows.

[0018]

(Equation 5)

By the processing up to this point, a post-filter output (SO) is obtained. If the transmission signal is a telephone band signal, this output (SO) is, for example, a sampling frequency of 8k.
Digital / analog conversion is performed by the Hz D / A converter 5, and a final synthesized sound output (T) is obtained.

By repeating the above-described processing for each frame, it is possible to continuously obtain a synthesized sound with improved perceptual quality.

[0021]

However, in the conventional configuration, in the filtering process of this series of post filters, the filter coefficient changes for each frame,
It is difficult to realize with an analog circuit, and all have been realized by arithmetic processing by software in the CPU.

For example, the post-filter calculation amount is 1 using the LPC coefficient of the tenth order as described in the above examples.
Considering a system with a frame of 20 ms and a sampling frequency of 8 kHz, the number of operations to be processed in 1 second can be calculated as follows.

Accumulation: 160000 times Addition / subtraction: 176000 times In addition to the above calculation amount of 160,000 times or more per second, in addition to actual processing, data read / write is required, and a considerable load on the CPU. Therefore, there is a problem that power consumption increases.

Further, an inexpensive CPU having a relatively low computing capacity
Then, it may be difficult to incorporate the post filter, and even if the post filter can be incorporated, there are many cases where other processing is restricted due to the post filter calculation.

An object of the present invention is to realize the post filter by an analog circuit to reduce the amount of calculation,
It is to facilitate hardware implementation of a voice decoder that consumes less power.

[0026]

SUMMARY OF THE INVENTION The above-described object is to provide a decoder CPU which receives an encoded voice signal as an input, outputs a decoded voice signal and calculates perceptual weighting coefficients for an LPC analysis filter and an LPC synthesis filter. And D for digital-analog converting the decoded audio signal output from the CPU
/ A converter, a delay circuit that receives the decoded voice signal analog-converted by the D / A converter as an input, delays the signal, and outputs a plurality of tap outputs, and the tap outputs of the delay circuits. A weighting synthesis circuit for performing weighted synthesis using the perceptual weighting coefficients for LPC analysis filters set by the CPU and outputting the result, a decoded speech signal analog-converted by the D / A converter, and the output of the weighting synthesis circuit are added. An analog FIR filter composed of an adder, a delay circuit that receives the output of the following subtractor, delays the signal, and outputs a plurality of tap outputs, and each tap output of the delay circuit is set by the CPU. Each LPC
An analog IIR filter configured by a weighting synthesis circuit that performs weighted synthesis using a perceptual weighting coefficient for a synthesis filter to output a post filter output signal, and a subtractor that subtracts the post filter output signal from the FIR filter output signal It is achieved by

According to the above means, the decoded voice signal is converted into an analog signal, the analog decoded voice signal is delayed by the analog delay circuit, and the delay signal is output to the plurality of taps. The plurality of outputs are L by a weighting synthesis circuit.
The signals weighted by the perceptual weighting coefficient for the PC analysis filter and the weighted signals are all combined. The weighted and synthesized signal is added to the analog-converted decoded speech signal by an adder, and the output of the LPC analysis filter is obtained.

Next, the output of the adder is subtracted from the post filter output by the subtractor, the subtracted output is input to the delay circuit, and the delay signal is output to each of the plurality of taps by the delay of the delay circuit. The plurality of outputs are weighted by the perceptual weighting coefficient for the LPC synthesis filter by the weighting synthesis circuit, and all the weighted signals are synthesized. The output of this weighting synthesis circuit becomes the post-filter output signal.

When the post-filter process for one frame is completed, the perceptual weighting coefficients for the LPC analysis filter and the LPC synthesis filter calculated for each frame for the next continuous frame are set in each weighting synthesis circuit. To be executed.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the configuration of an embodiment of the post filter of the present invention. The encoded signal (a) is the decoder C
It can be realized by a known method until it is input to the PU 11 and the decoded speech (b) and the perceptual weighting coefficient (e) (nu) are derived. The perceptual weighting coefficient calculated for each frame is input to the weighting synthesis circuits 14 and 18 for both the LPC analysis filter (e) and the LPC synthesis filter (n). The respective filter coefficients (e) and (e) are weighted synthesis circuits 14 and 1.
After being set to 8, the decoded voice (b) is delayed by the delay circuit 1 through the D / A converter 12 having a sampling frequency of 8 kHz.
3 is input.

Here, the analog delay circuit 13 will be briefly described. The delay circuit 13 is realized by an analog shift register. FIG. 2 shows an example of the configuration of the analog shift register, which includes buffers 101 and 105.
And sample and hold circuits 102 to 104, and TP _{1 to} TP _n are output terminals for shifted signals. The input signal V _in is input to the sample-hold circuit 102 of the first stage via the buffer 101. The sample-hold circuit 102 of the first stage holds the input signal as a sample in synchronization with the rising edge of the clock CK and outputs it to TP ₁ . Similarly, the second-stage sample-hold circuit 103 samples the output of the previous-stage sample-hold circuit 102 and delays it by 1 clock to the next stage and outputs it to TP ₂ . 3 and subsequent stages likewise for one stage operates as an analog shift register having n stages by shifting the signal by one clock, and outputs the TP ₃ to TP _n.

FIG. 3 shows an example of the configuration of the sample hold circuit.
4 and 5 show examples of buffer configurations. FIG. 3 shows buffers 201, 204, 207 and a switch 202 that is turned on when CK is L and turned off when H and CK is H.
Switch 205 that turns on when L and turns off when L
And capacitors 203 and 206.

The operation of the sample hold circuit of FIG. 3 is shown in FIG.
This will be described with reference to FIG. The input signal S _in passes through the buffer 201, the signal is transmitted to the capacitor 203 when the clock CK is L and the switch 202 is ON, and the clock CK is H.
When the switch 202 is turned off, the signal input to the capacitor 203 is held. Input signal S _{in at} this time
The output of the capacitor 203 via the buffer 204 is set to point A. Similarly, clock CK is H
When the switch 205 is ON, the signal is transmitted to the capacitor 206, the clock CK is L, and the switch 205 is OF.
When it becomes F, the signal input to the capacitor 206 is held and becomes the output signal S _out via the buffer 207.

FIGS. 4 and 5 show an example of the structure of the buffer. FIG. 4 shows a voltage follower circuit using an operational amplifier 301.
Are impedance elements 401 and 402 and the operational amplifier 40
3 is an inversion buffer composed of 3.

Both of these buffers and sample hold circuits are known in the art. The analog shift circuit can be easily configured by combining these known techniques.

Like the D / A converter 12, the delay circuit 13 shifts in synchronization with the operation of sending data from the CPU 11 to the D / A converter 12 if an operation clock (ck) of 8 kHz is applied. It is easy to understand that the operation is performed.

The signal (d) delayed by the delay circuit 13 and output as a plurality of tap outputs is weighted and synthesized by the weighting and synthesis circuit 14 by the preset perceptual weighting coefficient (e) for the LPC analysis filter and output. To be done.

Here, the weighting synthesis circuit 14 will be briefly described. As shown in FIG. 7, the weighting synthesis circuit 14 includes weighting synthesis circuits 501, 502, ... 510 and a synthesis circuit 511, and outputs the tap output of each delay circuit 13 by the preset weighting coefficient (e) as described above. (D) is a weighting circuit 501, 50
2, ..., 510, and the weighted signals (wo) are all added by the synthesis circuit 511 and become the output (f) of the weighted synthesis circuit 14.

This output (f) is added by the adder 15 to the D / A converter output (c) that does not pass through the delay circuit.

Here, FIG. 8 shows a configuration example of the weighting synthesis circuits 501, 502, ... 510 in the weighting synthesis circuit 14. (D) is a weighted input and corresponds to that in FIG. Zi (i = 1, ..., N) is an impedance on the input side, and is composed of a capacitor as shown in Equation 6.

[0041]

(Equation 6)

Here, n corresponds to the accuracy of the perceptual weighting coefficient (e), which is a digital weighting control signal, in the CPU, and n = 16, for example. Each capacitor Ci (ii =
The capacity of 1, ..., N) has a larger value as it approaches the MSB of the perceptual weighting coefficient. The switch Swi (i = 1 to n) is turned on according to the value of each bit corresponding to the weighting coefficient (e).
N / OFF. By this, Zi (i = 1, ..., N)
Alternatively, the value of the sum of Ci (i = 1, ..., N) is controlled.
An AMP 601 in the figure indicates an amplifier, and a feedback impedance Zf for this output (wo) is composed of a capacitor and is expressed by Equation 7.

[0043]

(Equation 7)

The gain G of this weighting circuit is given by Eq.

[0045]

(Equation 8)

The weighted output (wo) corresponds to that in FIG.

Here, FIG. 9 shows a configuration example of the combining circuit 511 in the weighting combining circuit 14. (O) is an input to be combined and corresponds to that in FIG. 7. Zg is an input and feedback impedance, and is composed of a capacitor as shown in equation 9.

[0048]

(Equation 9)

The capacities of the capacitors Cg are all the same value in the combining circuit. The AMP 701 in the figure indicates an amplifier, and the gain G of this combining circuit 511 is given by the expression 10.

[0050]

(Equation 10)

Therefore, the respective inputs (wo) are added and multiplied by the gain of -1, and become the output (f) of the synthesizing circuit 511. This output (f) corresponds to that of FIG. 7.

Since the sign of the weighting circuit is also inverted, the sign inversion of the synthesizing circuit does not cause any sign inversion.

The delay circuit 13, the weighting / synthesizing circuit 14, and the adder 15 described above constitute an FIR filter which is an LPC analysis filter which is a part of the post filter.

The output (g) of the adder 15 is subtracted from the output (g) of the weighting synthesis circuit 18 by the subtractor 16, and the subtracted output (h) is input to the delay circuit 17. The signals (i) delayed by the delay circuit 17 and output as a plurality of tap outputs are combined and output by the weighting combining circuit 18 by the preset perceptual weighting coefficient (L) for the LPC combining filter. The weighted synthesis circuit output (R) serves as the subtractor input and the post-filter output signal.

Here, the subtractor 16, the delay circuit 17, and the weighting / synthesizing circuit 18 form a part of the post filter LP.
It constitutes an IIR filter which is a C synthesis filter.
The detailed configurations of the delay circuit 17 and the weighting / combining circuit 18 are shown in FIG. 2, FIG. 3, FIG. 4, FIG.
It is the same as FIG.

In the above description, the CPU 11 finishes sending the decoded sound (b) for one frame to the D / A converter 12, and the post-filter process for one frame is completed. For the processing of the frames to be continued, the CPU 11 newly causes the weighting synthesis circuits 14 and 18 to calculate the L calculated for each frame.
It starts by setting the perceptual weighting factors (e) and (e) for the PC analysis filter and the synthesis filter.

The circuits 13, 14 and 17, 18 composed of the delay circuit and the weighting / synthesizing circuit are called analog neuro circuits and have already been put to practical use as a one-chip IC.

As a result, the amount of processing required by the CPU for the post filter is set in the weighting synthesis circuits 14 and 18 for the perceptual weighting coefficients (e) and (e) for the LPC analysis filter and the LPC synthesis filter calculated for each frame. The calculation process of the LPC analysis FIR filter of the post filter and the LPC synthesis IIR filter (336000 times / sec even with conventional integration and addition / subtraction) is not required at all.

As described above, the post filter, which has been difficult in the prior art, can be realized by using the analog circuit, and C
The calculation load on the PU can be greatly reduced.

As a post filter IC, packaging of the delay circuit, the weighting synthesis circuit, the subtractor, the adder, the delay circuit, and the weighting synthesis circuit into one chip can be realized by the present technology. Needless to say, it is effective as a general-purpose post filter IC.

[0061]

As described in detail above, according to the present invention, the processing required for the speech decoder post filter can be realized by an external analog circuit, thereby significantly reducing the calculation load of the CPU. Power consumption can be reduced. Further, there is an effect that a new control process can be performed on the CPU, and a post filter for improving the clarity of the decoded voice can be easily configured even if an inexpensive CPU having a relatively small calculation ability is used.

[Brief description of the drawings]

FIG. 1 is a block diagram of an analog post filter for a speech decoder according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of an analog shift register used in the delay circuit of FIG.

FIG. 3 is a block diagram of the sample hold circuit of FIG.

FIG. 4 is a buffer configuration diagram of FIG. 2.

5 is a buffer configuration diagram of FIG. 2;

FIG. 6 is an operation explanatory diagram of the sample hold circuit of FIG. 3;

FIG. 7 is a block diagram of the weighting synthesis circuit of FIG.

8 is a configuration diagram of the weighting synthesis circuit of FIG. 7.

9 is a configuration diagram of the synthesis circuit of FIG. 7.

FIG. 10 is a configuration diagram of a conventional post filter.

11 is a configuration diagram of the LPC analysis filter of FIG.

12 is a configuration diagram of the LPC synthesis filter of FIG.

[Explanation of symbols]

11 ... Decoder CPU, 12 ... D / A converter, 13 ... Delay circuit, 14 ... Weighting synthesis circuit, 15 ... Adder, 16 ...
Subtractor, 17 ... Delay circuit, 18 ... Weighting synthesis circuit.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H03H 17/02 615 9274-5J H03H 17/02 615B H03M 1/66 H03M 1/66 C

Claims (2)

[Claims] 1. A decoder C which receives an encoded voice signal as an input, outputs a decoded voice signal, and calculates perceptual weighting coefficients for an LPC analysis filter and an LPC synthesis filter.
A PU, a D / A converter for digital-analog converting the decoded audio signal output from the CPU, and a decoded audio signal analog-converted by the D / A converter as inputs, and delays the signal to form a plurality of taps. A delay circuit for outputting as an output, a weighting / synthesizing circuit for weighting / combining the tap outputs of the delay circuit with the respective perceptual weighting coefficients for LPC analysis filters set by the CPU, and outputting the D / A converter. The analog FIR filter constituted by the decoded speech signal analog-converted by the above and the adder for adding the output of the weighting synthesis circuit, and the following subtractor output are input, and the signal is delayed and output as a plurality of tap outputs. A delay circuit and each tap output of the delay circuit set by the CPU. And an analog IIR filter configured by a weighting synthesis circuit that performs weighted synthesis using the perceptual weighting coefficient for LPC synthesis filter and outputs a post-filter output signal, and a subtractor that subtracts the post-filter output signal from the FIR filter output signal. An analog post filter for a speech decoder, comprising: 2. A delay circuit which receives an analog-converted decoded speech signal as an input, delays the signal, and outputs the delayed signal as a plurality of tap outputs, and each tap output of the delay circuit is provided in each LPC.
An analog FIR filter configured by a weighting synthesis circuit that performs weighted synthesis using the perceptual weighting coefficient for the analysis filter and outputs, and an adder that adds the analog-converted decoded speech signal and the output of the weighting synthesis circuit, and the following subtraction Circuit which receives the output of the delay circuit as an input, delays the signal and outputs as a plurality of tap outputs, and each tap output of the delay circuit
An analog IIR filter configured by a weighting synthesis circuit that performs weighted synthesis using a perceptual weighting coefficient for a synthesis filter to output a post filter output signal, and a subtractor that subtracts the post filter output signal from the FIR filter output signal An analog post filter for a voice decoder, characterized by being packaged in a chip IC.