JPH09154065A - Image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption of an image pickup device. SOLUTION: An image signal Y1 (t) is generated by a signal processing circuit 17 for performing various kinds of signal processing to an image signal Y0 (t) provided from a CCD 11. The supply of power to a reference circuit 19, with which a reference voltage is supplied to an A/D converting circuit 18 for converting this image signal Y1 (t) to image data D(n), is stopped during the blanking period of horizontal scanning of CCD 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup apparatus which obtains image data for each screen by using a CCD solid-state image pickup device.

[0002]

2. Description of the Related Art In computer equipment such as personal computers and word processors, it is well known to use an image scanner which scans and reads an object document when capturing image data.
It has been considered to use an image pickup device using a CCD solid-state image pickup element that can deal with a three-dimensional object. In that case, the operation of the imaging device is controlled by the computer device, and the image data is taken out in units of one screen in response to a request from the computer device.

FIG. 6 is a block diagram showing the structure of an image pickup device in which image data is taken out on a screen-by-screen basis using a CCD solid-state image pickup device, and FIG. 7 is a timing chart for explaining its operation. The CCD solid-state imaging device 1 has a plurality of light receiving pixels arranged in rows and columns, and accumulates information charges generated in accordance with an image of an illuminated object in each light receiving pixel. The CCD 1 is, for example, of a frame transfer type, and as shown in FIG. 8, a plurality of vertical shift registers 1v continuous from the image pickup unit to the storage unit, and a horizontal shift register 1 arranged on the output side of each vertical shift register 1v.
h and an output section 1d arranged on the output side of the horizontal shift register 1h. In the imaging unit, the vertical shift register 1v is electrically separated to form a plurality of light receiving pixels, and information charges generated by photoelectric conversion are accumulated in each light receiving pixel. The information charge accumulated in each light receiving pixel of the image pickup unit is applied to each vertical shift register 1 by the frame transfer clock φf and the corresponding vertical transfer clock φv.
The inside of v is transferred from the imaging unit to the storage unit and temporarily stored. The information charges accumulated in the accumulation section are transferred from each vertical shift register 1v to each bit of the horizontal shift register 1h in units of one row by the vertical transfer clock φv, and at the same time, from the horizontal shift register 1h to the output section by the horizontal transfer clock φh. Each row is serially transferred to 1d.
The information charges transferred to the output unit 1d are stored in the capacitors bit by bit, so that the charge amount is converted into a voltage value and output as a video signal Y0 (t). At this time, in the output section 1d, the information charge accumulated in the capacitor is transferred to the horizontal transfer clock φh.
Is discharged to the drain in response to the reset clock φr synchronized with. Further, the CCD 1 has a so-called vertical overflow drain structure in which an excessive information charge generated in the image pickup section is absorbed in the substrate side, and the information charge accumulated in the image pickup section is transferred to the substrate side by the substrate clock φb. Can be discharged.

The driver circuit 2 includes a timing control circuit 3
The multi-phase frame transfer clock φf and the vertical transfer clock φv generated by are boosted and supplied to the image pickup unit and the storage unit of the CCD 1. At the same time, the substrate clock φb generated by the timing control circuit 3 is boosted and supplied to the substrate of the CCD 1. The timing control circuit 3 is activated by an activation signal TG provided from an external computer device, and based on a reference clock having a constant cycle, a frame transfer clock φf, a vertical transfer clock φv, and a horizontal transfer clock φ.
h and reset clock φr, and board clock φb
Generate The substrate clock φb is for discharging the information charges of the image pickup portion of the CCD 1 and is raised in response to the activation signal TG. The frame transfer clock φf is C
The information charges of the image pickup section of the CD 1 are transferred at high speed to the storage section in units of one screen, and are activated with a delay of a fixed period L from the fall of the substrate clock φb. This period L
Is a period during which information charges are accumulated in each light receiving pixel of the image pickup section of the CCD 1, and the exposure state of the CCD 1 is determined by the computer device side and set to an optimum state. Further, the frame transfer clock φf is clocked without a transfer operation during the period when the substrate clock φb is raised, so that the information charges of the image pickup section are easily discharged to the substrate side. The vertical transfer clock φv is for taking in the information charges transferred from the image pickup unit by the frame transfer clock φf to the storage unit and transferring the information charges from the storage unit to the horizontal transfer unit row by row. This vertical transfer clock φv is
The frame transfer clock φf is activated with a delay of a fixed period L from the fall of the substrate clock φb, and then a line feed pulse is generated at a constant cycle. The horizontal transfer clock φh is for sequentially transferring the information charges transferred from the storage section to the horizontal transfer section in units of one row to the output section side.
It is activated in response to the line transfer pulse of the vertical transfer clock φv. The reset clock φr is the CCD 1
The information charges accumulated in the output part of the above are discharged, and the phases are shifted at the same cycle as the horizontal transfer clock φh. As a result, the information charges accumulated in each light receiving pixel of the image pickup unit during the period L are transferred from the image pickup unit to the storage unit on a screen-by-screen basis, and then from the storage unit via the horizontal transfer unit on a row-by-row basis. Sequential transfer output.

The signal processing circuit 4 takes in the image signal Y0 (t) output from the CCD 1 and, after processing such as sample hold and automatic gain control (AGC), in the case of a color image, performs color separation, Processing such as color difference matrix and balanced modulation is performed. Further, a synchronizing signal for determining the timing of vertical scanning and horizontal scanning is added, and an image signal Y1 (t) including a luminance component, a color component and a synchronizing signal is generated. For example, in the sample hold process, only the difference between the levels is extracted from the image signal Y0 (t) in which the reference level and the signal level are alternately repeated at a constant cycle, and in the AGC process,
The gain for the image signal Y0 (t) is adjusted so that the average level of the image signal Y1 (t) falls within an appropriate range. The A / D conversion circuit 5 processes the image signal Y1 (t) output from the analog signal processing circuit 4 by the analog signal processing circuit 4 (C
Image data D1 (n) corresponding to each light-receiving pixel of CCD1 by analog / digital conversion in synchronization with the output operation of CD1)
Generate The image data D (n) thus generated is sequentially transferred to the computer device on a line-by-line basis.

[0006]

When the CCD 1 is driven, a high voltage is required for controlling the substrate potential, frame transfer operation, and vertical transfer drive. For example, the timing control circuit 3 and the signal processing circuit 4 operate in the range of 0V to 5V, while the frame transfer operation of the CCD 1 and the vertical transfer drive use a clock that changes in the range of -7V to 5V.
In addition, the output of CCD 1 has a voltage of 15V with respect to the ground potential.
The electric potential of is supplied. In the case of the image pickup apparatus including the driver circuit 2 that operates at such a high voltage, the power consumption in each circuit block is large, and therefore a large capacity battery is required when the image pickup apparatus is driven by a battery.

Therefore, it is an object of the present invention to reduce the power consumption of an image pickup device and to reduce the size and weight of the device.

[0008]

According to the present invention, a plurality of light receiving pixels are arranged in rows and columns, and a solid-state image sensor for accumulating information charges corresponding to an image of a subject on a screen-by-screen basis, and each light-receiving pixel of the solid-state image sensor. A drive circuit that transfers the accumulated information charges in the vertical direction row by row, then transfers it in the horizontal direction and sequentially outputs it, and determines the respective timings of vertical scanning and horizontal scanning of the solid-state imaging device in accordance with a reference clock of a constant cycle. And a signal processing circuit that receives the output of the solid-state image sensor to generate a predetermined video signal, and sets the signal processing circuit in a standby state during a horizontal scanning blanking period of the solid-state image sensor. To do.

As a result, during the horizontal scanning blanking period in which the image signal is not output from the solid-state image pickup device, the signal processing circuit and the A / D conversion circuit consume no power, so that the entire device consumes power. Will be reduced.

[0010]

1 is a block diagram showing the structure of an image pickup apparatus according to the present invention. The CCD solid-state image sensor 11 is
A plurality of light receiving pixels are arranged in rows and columns, and information charges corresponding to a subject image are accumulated in each light receiving pixel. This CCD 1 is, for example, of a frame transfer system similar to that of FIG. 6, and after transferring the information charges accumulated in the image pickup unit to the storage unit in units of one screen,
The image signal Y0 (t) is output by transferring and outputting in units of one row via the horizontal transfer unit. For CCD1,
From the power supply circuit 12 built in the device to the second power supply potential Vd2
Is supplied to the first ground potential V from a power source external to the device.
g1 is supplied.

The power supply circuit 12 includes two diodes 12
a and 12b and two capacitors 12c and 12d. First and second diodes 12a, 12b
Are connected in series, the first power supply potential Vd1 is applied to the anode side of the first diode 12a, and the first ground potential Vg1 is applied to the cathode side of the second diode 12b via the first capacitor 12c. To be done. First diode 1
The first driving clock φd1 is applied to the connection point between 2a and the second diode 12b via the second capacitor 12d, and the second diode 12b and the first capacitor 12c are connected.
The second power supply potential Vd2 is taken out from the connection point with
It is supplied to D1. The driver circuit 13 uses the frame transfer clock φ generated by the timing control circuit 13.
f, the vertical transfer clock φv, and the substrate clock φb are boosted and supplied to each part of the CCD 1. At the same time, the first drive clock φd1 generated by the timing control circuit 14 is boosted and supplied to the power supply circuit 12. This driver circuit 1
The first power supply potential Vd1 is supplied to 3 from the power eye outside the device, and the second ground potential Vg2 is supplied from the booster circuit 14 incorporated in the device. As a result, the driver circuit 13 operates from the second ground potential Vg2 to the first power supply potential Vd1.
To work between. The booster circuit 14 includes three diodes 1
4a, 14b, 14c and three capacitors 14d, 1
It is composed of 4e and 14f. The first to third diodes 14a, 14b, 14c are connected in series, and the first capacitor 14 is provided on the anode side of the first diode 14a.
The first ground potential Vg1 is applied via d, and the first ground potential Vg1 is applied to the cathode side of the third diode 14c. Second diode 14b and third diode 1
2c via the second capacitor 14e at the connection point with 4c
Drive clock φd2 is applied to the first diode 14
An inverted clock of the second drive clock φd2 is applied to the connection point between a and the second diode 14b via the third capacitor 14f. Then, the second ground potential Vg2 is taken out from the connection point between the first diode 14a and the first capacitor 14d and supplied to the driver circuit 13.

The timing control circuit 15 is activated by an activation signal TG supplied from a computer device, and the frame transfer clock φ is activated based on a reference clock having a constant cycle.
f, vertical transfer clock φv, horizontal transfer clock φh reset clock φr, and substrate clock φb are generated. At the same time, the first and second drive clocks φd1 and φd2 synchronized with the vertical transfer clock φv and the blanking clock φbk synchronized with the horizontal transfer clock φh are generated. Here, the substrate clock φb, the frame transfer clock φf, the vertical transfer clock φv, the horizontal transfer clock φh, and the reset clock φr are the same as those generated by the timing control circuit 3 shown in FIG. 6, as shown in FIG. Yes, the information charges accumulated in each light receiving pixel of the image pickup unit during the period L are transferred from the image pickup unit to the storage unit in one screen unit, and then sequentially from the storage unit in one row unit via the horizontal transfer unit. It is configured to be transferred and output. The first drive clock φd1 is the power supply circuit 1
2 is driven to generate the second power supply potential Vd2 for the CCD 11, which is activated in synchronization with the line feed pulse of the vertical transfer clock φv. The period from the rise to the fall of the first drive clock φd1 is CC
It is set so as to be within the blanking period of the horizontal scanning of D11. The second drive clock φd1 is supplied to the booster circuit 14
To generate the second ground potential Vg2 for the driver circuit 13, and repeats rising and falling in synchronization with the horizontal scanning timing of the CCD 11. Then, while the frame transfer clock φf is clocked, the frequency is switched to a high frequency and the driver circuit 13
We are trying to prevent power shortages in the area. The pair of buffer circuits 16a and 16b drive the booster circuit 14 by receiving the second drive clock φd1 generated by the timing control circuit 15 and its inverted clock. That is, since the timing control circuit 15 has a small output clock driving capability, the buffer circuit 1 is provided separately from the timing control circuit 15.
6a and 16b are provided so that the booster circuit 14 can be driven reliably. Blanking clock φbk is C
It designates a period during which the information charges are transferred and output from the CD 1, and is raised while the horizontal transfer clock φh is clocked. And the blanking clock φ
Power is supplied to the signal processing circuit 17 and the reference circuit 19, which will be described later, only during the period when bk is raised.

The signal processing circuit 17 takes in the image signal Y0 (t) output from the CCD 1, performs various processes such as sample hold and gamma correction, and outputs it as an image signal Y1 (t) according to a predetermined format. The signal processing itself in this signal processing circuit 17 is the same as that of the signal processing circuit 4 shown in FIG. Then, the A / D conversion circuit 18 takes in the image signal Y1 (t) output from the signal processing circuit 17, and performs analog / digital conversion of the image signal Y1 (t) in synchronization with the signal processing operation of the signal processing circuit 17. By doing C
Image data D (t) corresponding to each light receiving pixel of the CD 11 is generated. The reference circuit 19 is the A / D conversion circuit 18
On the other hand, two types of reference potentials corresponding to the dynamic range of the image signal Y1 (t) are supplied.

Timing control circuit 15 and buffer circuit 1
6, the signal processing circuit 17, the A / D conversion circuit 18, and the reference circuit 19 are integrated on the same semiconductor substrate to be formed as an integrated circuit element 20 for image pickup control. The integrated circuit element 20 is set to operate by receiving the first power supply potential Vd1 and the first ground potential Vg1. As a result, all the circuit blocks including the CCD 11 can be operated by the single power supply of the first power supply potential Vd1 and the first ground potential Vg1.
The integrated circuit element 20 controls a first gate circuit 20a that controls the input of the reference clock CLK to the timing control circuit 15 and an input of the first drive clock φd1 from the timing control circuit 15 to the driver circuit 13. Second
And a gate circuit of. Then, the signal processing circuit 1
7 and the third and fourth gate circuits 20 for controlling the input of the blanking clock φbk to the reference circuit 19.
c, 20d are provided. The first gate circuit 20a is
The rising of the first activation control signal PS1 permits the input of the reference clock CLK, and the second gate circuit 20b
Permits the input of the first drive clock φd1 by the rising of the fourth activation control signal PS4. The third gate circuit 20c permits the input of the blanking clock φbk at the rising edge of the third activation control signal PS3, and the fourth gate circuit 20d causes the blanking clock φbk at the rising edge of the second activation control signal PS2. Allow input. These first to fourth activation control signals PS1 to PS1
PS4 is supplied from the computer device side together with the activation signal TG, and as shown in FIG. 3, is started stepwise at regular time intervals. As a result, when the image pickup is started, the timing control circuit 15,
Since the A / D conversion circuit 18, the signal processing circuit 17, and the driver circuit 13 are activated in sequence, the current consumed by the device also increases stepwise. Therefore, as shown by the broken line in FIG. 3, the peak value of the inrush current can be made smaller than when all the circuits are started up at the same time. The activation control signals PS1 to PS4 described above can be generated inside the image pickup apparatus or inside the integrated circuit element 20 by using a well-known delay circuit.

FIG. 4 is a waveform diagram for explaining the operation of the booster circuit 14. Here, a case where the first power supply potential Vd1 is 5V and the first ground potential Vg1 is 0V will be described. Since the timing control circuit 15 operates between 0V and 5V, the second
The crest value of the drive clock φd2 is 5V. Therefore, the second diode 1 to which the second drive clock φd2 is applied
The potential at the connection point A between 4b and the third diode 14c is
Since the maximum potential is clamped to 0V by the third diode 14c, it changes between −5V and 0V in the same phase as the second drive clock φd2. Furthermore, the potential at the connection point B between the first diode 14a and the second diode 14b to which the inverted clock of the second drive clock φd2 is applied is the potential change at the connection point A and the second diode 14b.
Since the maximum potential is clamped to −5V by the clamping operation by, the voltage changes between −10V and −5V in the opposite phase to the second drive clock φd2. Then, the second ground potential Vg2 taken out from the connection point of the first diode 14a and the first capacitor 14d becomes about -10V due to the smoothing action of the first capacitor 14d. In normal operation, a voltage drop corresponding to the threshold value of the diode and a loss due to the driving load of the driver circuit 13 occur.
V or so. In the case of a circuit that is actually operated, the threshold value of the diode, the driving capability, the capacitance of the capacitor, etc. may be set so that the second ground potential Vg2 has a target value.

FIG. 5 is a waveform diagram for explaining the operation of the power supply circuit 12. Here, the first power supply potential Vd1 is 5 V and the second ground potential Vg2 supplied from the booster circuit 14 is −10.
The case of V will be described. Since the driver circuit 13 operates between −10 V and 5 V, the first drive clock φd1 is
The peak value is boosted to 15V and supplied to the power supply circuit 12. The potential of the connection point C between the first diode 12a and the second diode 12b to which the boosted first drive clock φd1 is applied is clamped at 5V by the first diode 14c. It changes between 5V and 20V in the same phase as the driving clock φd1 of 1. Then, the second diode 12b and the first capacitor 12
The second power supply potential Vd2 extracted from the connection point with c is
Approximately 20V due to the smoothing action of the first capacitor 12c
Becomes In a normal operation, like the booster circuit 14, the voltage drops to about 15V because a voltage drop corresponding to the threshold value of the diode and a loss due to the driving load of the CCD 11 occur. Also in this booster circuit 12, in the case of a circuit which is actually operated, the threshold value of the diode, the driving capability, the capacitance of the capacitor, etc. may be set by setting the second power supply potential Vd2 to a target value.

[0017]

According to the present invention, since the power supply to the signal processing circuit and the reference circuit is temporarily stopped during the horizontal scanning blanking period of the solid-state image pickup device, the power consumption is reduced. . In addition, by shifting the rising timing of each image block of the image pickup device composed of various circuits, it is possible to lower the peak value of the inrush current at startup and reduce power consumption at startup. can do. Therefore, when the imaging device is driven by a battery, simplification of the power source can be expected, and the cost of the device can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an image pickup apparatus of the present invention.

FIG. 2 is a timing diagram illustrating the operation of the image pickup apparatus of the present invention.

FIG. 3 is a waveform diagram of a start control signal for starting the image pickup apparatus of the present invention.

FIG. 4 is a waveform diagram illustrating the operation of the booster circuit.

FIG. 5 is a waveform diagram illustrating the operation of the power supply circuit.

FIG. 6 is a block diagram illustrating a configuration of a conventional imaging device.

FIG. 7 is a timing diagram illustrating the operation of the conventional imaging device.

FIG. 8 is a schematic diagram showing a configuration of a frame transfer type CCD solid-state imaging device.

[Explanation of symbols]

 1, 11 CCD solid-state imaging device 2, 13 Driver circuit 3, 15 Timing control circuit 4, 17 Signal processing circuit 5, 18 A / D conversion circuit 12 Power supply circuit 12a, 12b Diode 12c, 12d Capacitor 14 Booster circuit 14a-14c Diode 14d-14f Capacitors 16a, 16b Buffer circuit 19 Reference circuit 20 Integrated circuit element

Claims (2)

[Claims] 1. A solid-state image sensor in which a plurality of light-receiving pixels are arranged in rows and columns and information charges corresponding to an image of a subject are accumulated on a screen-by-screen basis, and one row of information charges accumulated in each light-receiving pixel of the solid-state image sensor. Each of which is transferred in the vertical direction, and then transferred in the horizontal direction and sequentially output, a timing control circuit which determines each timing of vertical scanning and horizontal scanning of the solid-state image sensor according to a reference clock having a constant cycle, and the solid-state An image pickup apparatus comprising: a signal processing circuit that receives an output of the image pickup device to generate a predetermined video signal; and the signal processing circuit is put in a standby state during a horizontal scanning blanking period of the solid-state image pickup device. . 2. An A / D conversion circuit for analog / digital converting the image signal generated by the signal processing circuit in synchronism with the output operation of the solid-state image pickup device to generate image data. The image pickup apparatus according to claim 1, wherein the D conversion circuit, together with the signal processing circuit, is placed in a standby state during blanking of horizontal scanning of the solid-state image pickup element.