JPH09153559A - Semiconductor integrated circuit device, its operating method, and electronic circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the phenomenon of hot electron in a given memory cell when a charge accumulated in source and drain regions is reset after write and erase operation at a memory cell in a non-volatile memory. SOLUTION: A memory cell in a memory block MB is turned off just after write or erase operation is carried out in the given memory block of a flash memory. Then, potential of a main bit line BL is reduced to a grounding level, and switching MOSFET's Q1S and Q2s are turned on. As a result, a charge accumulated in a sub-source line SS and a sub-bit line BLS is each discharged to a grounding potential VSS or the main bit line BL.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, an operating method thereof, and an electronic circuit device technology, and more particularly to a flash memory (EEPROM; Electric).
The present invention relates to a technology effectively applied to a semiconductor integrated circuit device having an ally erasable programmable read only memory) and a write / erase operation method thereof.

[0002]

2. Description of the Related Art A non-volatile memory that is electrically writable and erasable allows rewriting of information even when it is built in a wiring board and is easy to use, so various electronic circuit products that require a memory, For example, it can be widely used for IC cards and mobile phones.

In particular, 1 bit / 1 MOS.FET (Meta
l Oxide Semiconductor) structure flash memory (EE
The PROM) can have a higher degree of integration as compared with a flash memory (EEPROM) having a 1-bit / 2MOS.FET structure, and contributes comparatively greatly to downsizing and high functionality of electronic devices.

In recent years, from the viewpoint of reducing the occupied area of the memory cell region, etc., the memory cell region is divided into a plurality of memory blocks, and each memory block is constructed by connecting a plurality of memory cells in parallel. There is a structure in which the source region and the drain region of each memory cell are configured by a source line and a sub-bit line made of a common semiconductor region to reduce the number of connection holes and reduce the occupied area of the memory cell region.

A flash memory having such a structure (EE
In PROM), when writing information,
For example:

First, a write voltage is applied to the drain region of the memory block, and then a voltage of a predetermined value is applied to the word line of the selected memory cell in the memory block. Then
A tunnel phenomenon occurs between the floating gate electrode and the drain region of the memory cell, and thereby electrons are extracted from the floating gate electrode to the drain region (writing of information).

By the way, in this writing operation,
The control gate electrode (word line) of the non-selected memory cell is also applied with a voltage having the same potential as the above-mentioned write voltage.

This is because in the operation of writing information,
The above-mentioned write voltage is applied to the drain region of the non-selected memory cell, but at this time, a predetermined value or more is applied between the potential of the drain region of the non-selected memory cell and the potential of the control gate electrode of the non-selected memory cell. This is to prevent the electrons in the non-selected memory cells from being extracted by the potential difference (when the potential of the drain region is high) due to the potential difference.

A flash memory (EEPROM)
This is described in, for example, Japanese Patent Laid-Open No. 3-250495.

[0010]

The inventor of the present invention has found that a flash memory (EEP) having a plurality of memory blocks as described above.
As a result of examining the ROM), it was found that the following problems occur.

That is, when the voltage of the source region and the drain region of the memory cell is reset before resetting the voltage of the word line, the charges accumulated on the sub bit line (drain region) side are on the source line (source region) side. The parasitic capacitance of the non-selected memory cells is attracted by the voltage stored in the write operation, and flows to the source line side through the memory cell having a lower threshold voltage among the non-selected memory cells, resulting in a hot electron phenomenon in the non-selected memory cells. There is a problem that electrons are injected into the floating gate electrode of the non-selected memory cell and the threshold voltage of the non-selected memory cell rises.

An object of the present invention is to reset hot charges accumulated in a source region and a drain region of a memory cell after a write / erase operation in the memory cell constituting a non-volatile memory, in a predetermined memory cell. It is to provide a technique capable of preventing a phenomenon from occurring.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0014]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

A semiconductor integrated circuit device according to the present invention comprises a plurality of memory blocks dividedly arranged in a memory cell region on a semiconductor substrate, each of the plurality of memory blocks being provided on a floating gate electrode via an insulating film. A plurality of MIS • FET type non-volatile memory cells having a two-layer gate electrode structure in which control gate electrodes are laminated are connected in parallel, and the source regions and drains of the plurality of memory cells in each memory block are connected. A semiconductor integrated circuit device in which regions are connected by a first source line and a first bit line each made of a common semiconductor region, and a writing operation and an erasing operation in a selected nonvolatile memory cell in the memory block. At the end of, all the nonvolatile memory cells in the memory block in which the selected nonvolatile memory cell exists are turned off. In After, it is provided with a path for release without the all electric charges charged in the drain region and the source region of the nonvolatile memory cell is passed through the non-volatile memory cells of the memory block.

Also, the method for operating a semiconductor integrated circuit device of the present invention comprises a plurality of memory blocks divided into memory cell regions on a semiconductor substrate, each of the plurality of memory blocks being on a floating gate electrode. MIS having a two-layer gate electrode structure in which control gate electrodes are stacked with an insulating film interposed
A plurality of FET type non-volatile memory cells connected in parallel, and a source region and a drain region of the plurality of memory cells in each of the memory blocks are a first source line and a first source line, each of which is a common semiconductor region; A method of operating a semiconductor integrated circuit device connected by a 1-bit line, comprising: selecting a nonvolatile memory cell at the end of a write operation and an erase operation in a selected nonvolatile memory cell in the memory block. After turning off all the non-volatile memory cells in the existing memory block, the electric charge stored in the drain region and the source region of all the non-volatile memory cells is released through separate paths. It is a thing.

Also, the method of operating a semiconductor integrated circuit device of the present invention comprises a plurality of memory blocks divided into memory cell regions on a semiconductor substrate, each of the plurality of memory blocks being on a floating gate electrode. MIS having a two-layer gate electrode structure in which control gate electrodes are stacked with an insulating film interposed
A plurality of FET type non-volatile memory cells connected in parallel, and a source region and a drain region of the plurality of memory cells in each of the memory blocks are a first source line and a first source line, each of which is a common semiconductor region; A method of operating a semiconductor integrated circuit device connected by a 1-bit line, comprising: a source region of the nonvolatile memory cell at the end of a write operation and an erase operation in a selected nonvolatile memory cell in the memory block. In order to allow the electric charge charged in the drain region to escape without passing through the non-volatile memory cell in the memory block, electrically between the source region and the drain region of the non-volatile memory cell in the memory block. The step of turning on the connected third switching element is included.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings (note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments. , The repeated explanation is omitted).

(Embodiment 1) FIG. 1 is a circuit block diagram of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG.
1 is a circuit diagram of main parts of a memory cell region and a peripheral circuit region of the semiconductor integrated circuit device of FIG. 1, FIG. 3 is a circuit diagram of main parts of a memory cell region of the semiconductor integrated circuit device of FIG. 1, and FIG. 4 is a semiconductor integrated circuit of FIG. FIG. 5 is a cross-sectional view of a main part of a memory cell in a circuit device.
(A), (b) is an explanatory view of an operating state in the semiconductor integrated circuit device of FIG. 1, FIGS. 6 (a) to (c) are explanatory views of an operating state in the semiconductor integrated circuit device of FIG. 1, and FIG. FIG. 3 is an explanatory diagram for explaining an example of set voltage values of each unit during a write operation and an erase operation of the semiconductor integrated circuit device of No. 1;

The semiconductor integrated circuit device according to the first embodiment shown in FIG. 1 is, for example, a flash memory 1. In FIG. 1, Vcc indicates a power supply potential and Vss indicates a ground potential.

In the memory cell region M of the flash memory 1, a plurality of non-volatile memory cells (hereinafter, simply referred to as memory cells), which will be described later, are regularly arranged. This memory cell is a minimum unit of a memory that stores either one of high (hereinafter simply referred to as “H”) signal level or low (hereinafter simply referred to as “L”) signal level binary data. is there.

The row address buffer circuit XADB takes in and holds the row address signal AX at a predetermined timing, forms an internal row address signal based on the row address signal AX, and supplies it to the row address decoder circuit XDCR. It is a circuit to do.

The row address decoder circuit XDCR is a circuit which receives an internal row address signal from the row address buffer circuit XADB and selects a predetermined one word line. Note that Vrw, Vww, Vwv, Vew, and Vev are built-in voltages supplied from the built-in power supply circuit VS.

The column address buffer circuit YADB is
The circuit is a circuit that takes in and holds the column address signal AY at a predetermined timing, forms an internal column address signal based on the column address signal AY, and supplies the internal column address signal to the column address decoder circuit YDCR.

The column address decoder circuit YDC
R receives the internal column address signal from the column address buffer circuit YADB and receives the column gate array circuit Y.
This circuit finally selects a predetermined main bit line via G.

The data latch circuit DR is a circuit for temporarily holding write data or read data.
The sense amplifier circuit SA is a circuit for detecting and amplifying a minute voltage (or current) transmitted to the main bit line, and the data output buffer circuit DOB and the data input buffer circuit DIB via the column gate array circuit YG.
Is electrically connected to Note that Vr d and Vw d are
This is the built-in voltage supplied from the built-in power supply circuit VS.

The data output buffer circuit DOB is a circuit for amplifying the signal read from the memory cell MC so that it can be transmitted to an external device without being attenuated in a wiring path on the way, and via a multiplexer circuit MP. It is electrically connected to the external input / output terminal I / O.

The data input buffer circuit DIB is a circuit for setting the input signal of the write data transmitted from the outside to a potential suitable for the internal circuit, and the external input / output terminal I / I via the multiplexer circuit MP. It is electrically connected to O.

The mode control circuit MC is a circuit for controlling the operation of modes such as writing, erasing and reading based on the control signal supplied from the control signal buffer circuit CSB, and includes the row address buffer circuit XADB and the column address buffer. Circuit YAD
B, a data input buffer circuit DIB, a data output buffer circuit DOB, a source / well potential switching circuit SVC, an external terminal R / B, and the like.

Note that Vec represents the built-in voltage supplied from the built-in power supply circuit VS. Also, / CE, / OE, /
Reference symbols WE and SC denote control signal terminals to which a chip enable signal, an output enable signal, a write enable signal, and a serial clock signal are input, respectively. This “/” is Active Low
w) means a signal.

Next, a part of the memory cell area M and the peripheral circuit area of the flash memory 1 will be described with reference to FIGS.

In the memory cell area M, a plurality of memory blocks MB are arranged. Each memory block MB is
A plurality of memory cells MC are connected in parallel and configured.

As will be described later, the memory cell MC is a MOS-FET having a two-layer gate electrode structure in which a control gate electrode (control gate electrode) is laminated on a floating gate electrode (floating gate electrode) via an insulating film. It is composed of.

The control gate electrodes of the memory cells MC are word lines WL (WL0, WL1 ... WLX; X).
Is a part of the memory cell MC of the adjacent memory block MB.

The source region of each memory cell MC in each memory block MB has a common sub-source line (first source line) SS (SS0, SS1 ... SSn;
n is the number).

The sub-source line SS is formed in the semiconductor region provided on the upper part of the semiconductor substrate as described later, and the switch MOS • FET (first switching element) Q1S (Q1S0, Q1S1 ... Q1Sn; n is electrically connected to the ground potential Vss via n).

The switch MOS • FET Q1S is turned on by a signal transmitted to the wiring SMS. This wiring SMS is for all switch MOS / FE
It is common to TQ1S.

The drain region of each memory cell MC has a common sub-bit line (first bit line) BLS (BL
S0, BLS1 ... BLS n; n is the number).

The sub-bit line BLS is formed in a semiconductor region provided on the upper part of the semiconductor substrate as will be described later, and the switch MOS • FET (second switching element) Q2S (Q2S0, Q2S1 ... Q2Sn; n). Is the number of main bit lines BL (BL0, BL1 ... BLn;
n is the number).

The switch MOS • FET Q2S is driven by the signal transmitted to the wiring SMD. This wiring SMD is used for all switch MOS / FE
It is common for TQ2S.

One end of the main bit line BL has a MOS
It is electrically connected to the ground potential VSS through the FET QD. This MOS-FET QD has a wiring DDC (DDC
0, DDC1 ... DDCn; n is the number of signals).

The other end of the main bit line BL is electrically connected to the sense amplifier SA through the selection MOS • FETQSE.

The selection MOS • FET QSE is an element for selecting a bit line, and the wiring TR (TR0, TR1 ... TR).
n; n is the number of signals transmitted.

The sense amplifier SA is a CMOS (Complime
ntary MOS) Amplifier SAC and MOS ・ FET QSAP0, Q
It has SAP1, QSAN0, and QSAN1.

Further, the precharge MOS.FET QPR connected to each main bit line BL is an element for precharging the main bit line BL at the time of reading data, and the wiring RPC (RPC0, RPC1 ... RPCn; n).
Is driven by the signal transmitted to the number.

Wiring PCs (PC0, PC1 ... PC
n; n is the number) is to transmit a drive signal for precharging only the main bit line BL in which the write data is latched in the verify operation (write verify operation) that is subsequently performed after writing.

Next, FIG. 4 shows a cross-sectional view of the main part of the memory cell MC described above. The semiconductor substrate 2 is made of, for example, p ⁻ -type silicon (Si) single crystal, and an n well 2n and a p well 2p are formed in this order from the lower layer on the upper layer portion thereof.

A field insulating film 3 for element isolation is formed on the semiconductor substrate 2. The field insulating film 3 is made of, for example, silicon dioxide (SiO ₂ ), and the above-mentioned memory cell MC is formed in the element forming region surrounded by this. A channel stopper region 4 for element isolation is formed below the field insulating film 3.

The memory cell MC includes a source region 5s and a drain region 5d formed on the p well 2p of the semiconductor substrate 2 and an insulating film 5i1 formed on the semiconductor substrate 2.
And the floating gate electrode 5 formed thereabove
f, an insulating film 5i2 formed on the upper layer thereof, and a control gate electrode 5c formed on the upper layer thereof.

The source region 5s is formed by introducing, for example, n-type impurity phosphorus or arsenic (As), and is a part of the sub-source line SS (see FIG. 2) described above. The drain region 5d is formed by introducing, for example, n-type impurity phosphorus or As, and is a part of the sub-bit line BLS (see FIG. 2).

The insulating film 5i1 is made of SiO ₂ , for example. The floating gate electrode 5f is made of, for example, low resistance polysilicon. Insulating film 5i2, for example SiO ₂ film is formed by laminating on the silicon nitride film. The control gate electrode 5c is made of, for example, low resistance polysilicon and is also a part of the above-mentioned word line WL (see FIG. 2).

Such a memory cell MC has, for example, Si
It is covered with an interlayer insulating film 6 made of O ₂ . A first layer wiring 7 is formed on the interlayer insulating film 6. The first layer wiring 7 is made of, for example, an aluminum (Al) -Si-copper (Cu) alloy, and is covered with a surface protection film 8 made of, for example, SiO ₂ .

Next, a write operation method of the flash memory 1 will be described with reference to FIGS. In addition,
Since the erase operation is the same as the write operation, its description is omitted.

FIG. 5 is a diagram in which one memory cell MC of the memory block MB is extracted and shown as a representative of all the memory cells MC. FIG. 5A shows a state during a write operation, and FIG. 5B shows a write operation. The latter state is shown. Note that C0 represents a parasitic capacitance.

In the first embodiment, in the writing operation (removing the electric charge of the floating gate electrode),
As shown in FIG. 5A, predetermined voltages Vpg, Vps and Vpd are applied to the control gate electrode, the sub source line SS and the sub bit line BLS, respectively. In addition,
Vs indicates the source voltage.

Subsequently, in the write operation, the parasitic capacitance C0
In order to release (reset) the charge accumulated in
The voltage applied to the control gate electrode is 0 (zero: VOf
f) Set to V and turn off the memory cell MC.

By doing so, it is possible to prevent the charge accumulated in the parasitic capacitance C0 from escaping through the memory cell MC. Therefore, it is possible to prevent the hot electron phenomenon caused by the escape of charges through the memory cell MC.

Such an operation will be specifically described with reference to FIG. Note that FIG. 7 shows an example of the applied voltage to each part during the write operation and the erase operation.

First, in the write operation, the charge of the floating gate electrode of the selected memory cell MC is extracted and the write operation is performed as follows.

That is, as shown in FIGS. 6A and 7, for example, -10V is applied to the selected word line WL, and the power supply potential VCC (about 3V) is applied to the other unselected word lines WL. ) Is applied. In addition, the sub source line S
A voltage of, for example, about 0 to 3 V is applied to S, and a voltage of, for example, about 3 V is applied to the sub bit line BLS and the main bit line BL. Further, a voltage of, for example, about 6V is applied to the wiring SMD, and a voltage of, for example, about 0V is applied to the wiring SMS.

Then, after the write operation is completed, the parasitic capacitance charge of the sub-source line SS or the sub-bit line BLS is extracted as follows.

First, as shown in FIG. 6B, the voltage of each word line WL in all the memory cells MC of the selected memory block MB is set to 0V, for example.

As a result, as described above, the parasitic capacitance C
It is possible to prevent the charge accumulated at 0 from escaping through the memory cell MC and prevent the hot electron phenomenon caused by this.

Subsequently, as shown in FIG. 6C, the main bit line BL is set to 0V, for example, and the power supply potential VCC is applied to the wiring SMS to drive the switch MOS • FET Q2S, The sub-source line SS and the ground potential VSS are electrically connected. In this way, the voltage applied to the sub-source line SS and the sub-bit line BLS is set to, for example, about 0V.

As a result, the charges accumulated in the parasitic capacitance C0 of the sub-source line SS and the sub-bit line BL can be escaped through separate paths without passing through the memory cell MC.

That is, as shown by arrows A and B in FIG. 6 (c), the charges accumulated in the sub-source line SS flow to the ground potential VSS through the switch MOS • FET Q2S and are accumulated in the sub-bit line BLS. The electric charge that has been used is made to flow to the main bit line BL through the switch MOS • FET Q1S.

Next, FIG. 9 shows the flash memory 1 of the present invention.
1 is a schematic view of a main part of an IC card (electronic circuit device) 10 that uses The flash memory 1 and the microcontroller (control circuit) 1 of the present invention are provided on the plastic substrate 10a.
1 is mounted. The microcontroller 11 is a control circuit for the flash memory 1 and controls the operation of the flash memory 1.

The internal wiring of the flash memory 1 and the microcontroller 11 of the present invention and the wiring on the plastic substrate 10a are connected to each other.

Further, the wiring on the plastic substrate 10a is electrically connected to the connector 10c provided at the end of the plastic substrate 10a so that it can be connected to the interface circuit in the external system through the connector 10c. It has become. As a result, the IC card 10 can be used as information of various systems.

Further, here, the microcontroller 1
Although the example in which 1 is built in the IC card 10 is shown, the microcontroller 11 may be provided independently instead of being provided in the IC card 10.

If this IC card is used as a replaceable auxiliary storage medium in a small-sized and portable computer system below a workstation like a conventional floppy disk, it is not necessary to rotate the disk and the entire system can be made smaller. In addition, it is possible to reduce the weight and the thickness, reduce the power consumption, and read / write a large amount of information at high speed, so that the processing capability of the entire system is improved.

Next, FIG. 10 shows a principal part explanatory view of a computer system 12 using the flash memory 1 of the present invention. The computer system 12 includes a central processing unit CPU as the information device, an I / O bus I / OB built in the information processing system, a bus unit BUS, and a memory control unit for accessing a high speed memory such as a main memory or an extended memory. MCU, DRAM as main memory,
It is composed of a read-only memory ROM in which a basic control program is stored, a keyboard controller KBDC having a keyboard connected to its tip, and the like. Note that CC
P indicates a processing device that performs processing equivalent to that of the central processing unit CPU.

Further, the display adapter DA is the I / O bus I.
/ OB, and the display DP is connected to the tip of the display adapter DA. The I / O bus I / OB has a parallel port PP, a serial port SP such as a mouse, a floppy disk drive FDD, and an I / O bus.
A buffer controller HB for converting data from the O bus I / OB into a hard disk drive HDD is connected. Further, the expansion RAM and the DRAM are connected to the bus from the memory control unit MCU.

The hard disk drive HDD is electrically connected to the flash memory file system FFS and its interface unit IFU. The interface unit IFU is electrically connected to the flash memory 1, the control unit CU that controls the operations of the flash memory file system FFS, and the information table IT.

Now, the operation of the computer system 12 will be described. When the power is turned on and the operation is started, the central processing unit CPU first accesses the ROM through the I / O bus I / OB to perform an initial diagnosis,
Perform initial settings. Then, the system program is loaded from the auxiliary storage device into the DRAM.

Further, the central processing unit CPU is
/ O bus I / OB operates to access the HDD controller to the hard disk drive HDD. Then, when the loading of the system program is completed, the process proceeds according to the process request from the user.

It should be noted that the user can select the above I / O bus I / OB.
Upper keyboard controller KBDC and display adapter D
Work is carried out while inputting and outputting the processing by A. Then, the input / output device connected to the parallel port PP and the serial port SP is utilized as needed.

When the main memory capacity of the main body DRAM is insufficient, the main memory is supplemented by the expansion RAM. When the user wants to read or write a file, the user requests access to the auxiliary storage device assuming that the hard disk drive HDD is the auxiliary storage device.

Then, the flash file system FFS constituted by the flash memory 1 of the present invention receives it and accesses the file data.

An application example using this computer system 12 is shown in FIG. Notebook type personal computer 12a
Is a system having an IC card slot ICS and having a built-in flash memory file FMF constituted by an IC card 10 having a built-in flash memory of the present invention, and having a keyboard KB and a display DP as input / output devices.

The disk top type personal computer 12b is
The system has a built-in flash memory file FMF formed by an IC card 10 having a floppy disk drive FDD and the flash memory of the present invention.

By using the keyboard KB and the display DP as input / output devices and inserting the floppy disk FD into the floppy disk drive FDD, the data of the floppy disk FD can be stored in the flash memory file FMF. There is.

The pen portable type personal computer 12c is
This is a system into which a flash file card FFC as an IC card incorporating the flash memory of the present invention can be inserted, and has a structure in which an input-only pen 12cp can be used as an input / output device.

Thus, the flash memory 1 of the present invention
Can be applied to the above portable computer system (notebook type personal computer 12a, desktop type personal computer 12b, pen portable type personal computer 12c).

As a result, it is not necessary to rotate the conventional disk, the overall size and weight of the system can be reduced, the power consumption can be reduced, and a large amount of information can be read and written at high speed. The processing capacity of the system 12 as a whole can be improved. Furthermore, since the conventional disk is replaced with the flash memory 1 of the present invention, impact resistance, which is a problem in a portable computer, can be improved, and reliability in a computer system can be improved.

Next, FIG. 12 shows an explanatory diagram of a microprocessor system 13 incorporating the flash memory 1 of the present invention. The microprocessor 13 is a central processing unit CP
U, flash memory 1 of the present invention, serial communication interface SCI, read only
A memory ROM, a random access memory RAM, other input / output circuit I / OC and other peripheral circuits, and a control circuit CONT and the like.

The rewrite control program to be executed by the central processing unit CPU in the microprocessor 13 is previously written in the flash memory 1 of the present invention by a general-purpose PROM writer.

Then, by the control of the mode signal MD to the mode signal input terminal MDP, the central processing unit CPU, the input / output circuit I / OC, the serial communication interface SCI, the read only memory are supplied via the data bus DBUS. Data is interfaced with the ROM, the random access memory RAM, and the flash memory 1 of the present invention.

Further, the central processing unit CPU controls the operation of the flash memory 1 of the present invention. Further, the input / output circuit I / OC and the serial communication interface SCI interface the data with the input / output device.

Further, the flash memory 1 of the present invention has an input / output circuit I / OC, a serial communication interface SCI, and a serial communication interface SCI via an address bus ABUS.
Random access memory RAM, read only
Addresses with memory ROM. This read-only memory ROM stores a non-rewritable basic system program.

In this manner, the flash memory 1 of the present invention can rewrite its stored information under the control of the central processing unit CPU in the state where the microprocessor 13 is mounted as a microprocessor system including an input / output device. To be done. The stored information can be rewritten under the control of the input / output device such as a general-purpose PROM writer.

Thus, the flash memory 1 of the present invention
Is applied to a microprocessor system, the power consumption can be reduced. Furthermore, a large amount of information can be read and written at high speed, the microprocessor 13 can be downsized, and the processing capacity of the entire microprocessor system is improved.

FIG. 13 is an explanatory view of the main parts of a cordless telephone system 14 incorporating the flash memory 1 of the present invention. The reception of voice by the cordless telephone having the flash memory 1 according to the present invention will be described below.

The radio wave input by the antenna 14a is input to the digital modulation circuit 14c1 of the baseband section 14c via the analog front end section 14b, and is subjected to waveform equalization and analog-digital conversion.

The output signal of the digital modulation circuit 14c1 is input to the channel coding circuit 14c2 to perform error correction and frame decomposition.

Further, the output signal of the channel coding circuit 14c2 is input to the voice codec circuit 14c3, subjected to digital-analog conversion and voice expansion, and transmitted to the speaker of the cordless telephone 14d.

Below, the voice transmission of the cordless telephone system 14 incorporating the flash memory 1 of the present invention will be explained. The voice input to the microphone of the cordless telephone 14d is input to the voice codec circuit 14c3 of the baseband unit 14c.

Then, voice analog-digital conversion and voice compression are performed, and error correction and frame assembly are performed via the channel coding circuit 14c2.

Further, waveform equalization and digital-analog conversion are performed through the digital modulation circuit 14c1 and through the analog front end section 14b.
It is transferred to the antenna 14a.

Such a cordless telephone system 14
The control unit 14e for controlling the microprocessor is a microprocessor MPU.
And a flash memory 1.

The microprocessor MPU and flash memory 1 are bidirectionally connected. And
The microprocessor MPU is operated by inputting a signal by the key K1 provided in the cordless telephone 14d.
The speed dial number, code and the like are written in the flash memory 1 under the control of.

Then, the speed dial number, code and the like stored in the flash memory 1 are also read. Further, by the microprocessor MPU,
Digital modulation circuit 14c1 and voice codec circuit 1
4c3 is controlled.

Thus, the cordless telephone system 14
By using the flash memory 1 for the control unit 14e, the control unit 14e can be downsized, the cordless telephone system 14 can be downsized, the weight can be reduced, the power consumption can be reduced, and a large amount of information can be read and written at high speed. The processing capacity of the entire system is improved. Further, shock resistance, which has been a problem for mobile phones, can be improved, and reliability as a cordless phone system is improved.

Next, FIG. 14 shows an explanatory view of the essential parts of a digital still camera system 15 using the IC card 10 having the flash memory 1 of the present invention built therein.

Digital still camera system 15
Is composed of an optical system 15a, a central processing unit CPU, a motor drive circuit 15b, a diaphragm 15c, a shutter 15d, an image sensor 15e, signal processing circuits 15f1 and 15f2 and an analog-digital conversion circuit A / DC.

The object is received by the optical system 15a, and the motor drive circuit 15 is controlled by the central processing unit CPU.
The diaphragm 15c and the shutter 15d are controlled by b,
The subject is imaged on the image sensor 15e via the diaphragm 15c and the shutter 15d.

Then, the signal of the image formed by the image sensor 15e is formed by the signal processing circuit 15f1. Further, the signal formed by the signal processing circuit 15f1 is the analog-digital conversion circuit A
/ DC is input, and a digital signal is formed from the input analog signal.

Then, the digital signal is input to the signal processing circuit 15f2 controlled by the central processing unit CPU and data is compressed, and the data is stored in the IC card 10 with the built-in flash memory 1.

As described above, the IC card 10 with the built-in flash memory 1 in the digital still camera system 15
By applying the above, the digital still camera system 15 can be downsized, lightened, and thinned, the power consumption can be reduced, and a large amount of information can be read and written at high speed. The processing capacity is improved.

Furthermore, the impact resistance, which is a problem for the digital still camera system 15, can be improved,
The reliability of the digital still camera system 15 as a system is improved.

Next, FIG. 15 shows an explanatory view of the main parts of an automobile system 16 manufactured by using the flash memory 1 of the present invention as a memory element. The input / output control unit I / OCONT controls the transmission TRM that transmits the power of the air conditioning unit 16a, the sensors 16b and the engine 16c to the tires, and further inputs and outputs signals to and from the instruments and the display panel A.

The engine 16c is the engine control unit 16
controlled by d. Then, the input / output control unit I /
The OCONT controls the flash memory 1 as a memory unit by the signal processing unit 16e including the microprocessor MPU of the flash memory 1 according to the present invention, and writes and reads information.

The output signal from the transmission TRM is input to the vehicle height controller 16f and the suspension controller 16g to control the vehicle body.

Further, in the first embodiment, the flash memory 1 of the present invention is incorporated in the microprocessor MPU and is also applied to the memory section. However, the present invention is not limited to this and can be applied to a desired location. it can.

As a result, the above-mentioned automobile system 1
6 can be reduced in size and weight, and can be reduced in power consumption, thereby improving fuel efficiency. Furthermore, by using the flash memory 1 according to the present invention, the shock resistance can be increased, so that the reliability of the system can be improved. Further, since a large capacity memory can be provided, there is an advantage that the control system can be provided with a high processing capacity with a small number of parts.

As described above, according to the first embodiment, the following effects can be obtained.

That is, at the end of the write and erase operations in the selected memory cell MC in the selected memory block MB forming the flash memory 1, all the memory cells MC in that memory block MB are turned off. After that, all the sub-source lines S of the memory cells MC are
Since the electric charge accumulated in S and the sub bit line BLS can be released without passing through the memory cell MC in the memory block MB, it is possible to prevent the hot electron phenomenon from occurring in the memory cell MC in the memory block MB. Is possible. Therefore, it is possible to prevent the threshold voltage of the memory cell MC from rising due to the hot electron phenomenon. Therefore, it is possible to improve the operational reliability of such a flash memory 1.

(Second Embodiment) FIGS. 8 (a) and 8 (b) are explanatory views for explaining a circuit configuration and an operating state of a main part of a semiconductor integrated circuit device according to another embodiment of the present invention. is there.

FIG. 8 shows one of the memory blocks MB.
It is the figure which extracted and recorded one memory cell MC as a representative of all the memory cells MC, (a) shows the state at the time of write-in operation, (b) has shown the state after a write-in operation.

In the second embodiment, as shown in FIG. 8, a switch MOS • FET (third switching element) Q3S is electrically connected between the sub-source line SS and the sub-bit line BLS of the memory cell MC. It is connected to the. Other than this, the structure is the same as that of the first embodiment.

This switch MOS • FET Q3S is an element that makes the sub-source line SS and the sub-bit line BLS conductive or non-conductive, and one switch is sufficient for one memory block MB. .

The write operation method of such a flash memory 1 is as follows.

First, in the second embodiment, in the writing (drawing the electric charge of the floating gate electrode) operation, as shown in FIG. 8A, the control gate electrode, the sub-source line SS and the sub-bit line BLS are Predetermined voltages Vpg, Vps, and Vpd are applied, respectively.

Then, in order to release (reset) the charges accumulated in the parasitic capacitance C0 at the time of writing, the control gate electrode, the sub-source line SS and the sub-bit line BL.
With the state of S unchanged, switch MOS / FETQ
Turn on 3S.

By doing so, the sub-source line SS
And the charge accumulated in the parasitic capacitance C0 of the sub-bit line BLS does not pass through the memory cell MC, and the switch MO
It is possible to escape to the main bit line BL or the ground potential VSS through the S-FET Q3S. Therefore, it is possible to prevent the hot electron phenomenon caused by the electric charge escaping through the memory cell MC.

As described above, in the second embodiment,
In addition to the effects obtained in the first embodiment, the following effects can be obtained.

That is, the charge accumulated in the parasitic capacitance C0 of the sub-source line SS and the sub-bit line BLS of the memory block MB is released through the switch MOS.FET Q3S to turn off the memory cell MC immediately after the write or erase operation. Since it is not necessary, it becomes possible to simplify the operation control immediately after the write operation or erase operation.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-mentioned Embodiments 1 and 2 and is within a range not departing from the gist thereof. It goes without saying that various changes can be made.

For example, in the first and second embodiments, the control gate electrode of the memory cell is made of low resistance polysilicon alone, but the present invention is not limited to this. For example, tungsten silicide or the like may be formed on the low resistance polysilicon film. A laminated structure in which such a silicide film is formed may be used.

In the above description, the case where the invention made by the present inventor is mainly applied to the flash memory (EEPROM) technology which is the field of use which is the background of the invention has been described, but the invention is not limited to this, and for example, the EEPROM is used. And other semiconductor integrated circuit device technology having a logic circuit on the same semiconductor substrate. The present invention can be applied to a semiconductor integrated circuit device having at least the memory cell region having the above configuration.

[0131]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

That is, according to the above-described present invention, after all the memory cells in the memory block are turned off at the end of the write operation and the erase operation in the selected memory cell in the memory block, Since the electric charge charged in the source region and the drain region of the memory cell can be released without passing through the memory cell in the memory block, it is possible to prevent the hot electron phenomenon from occurring in the memory cell in the memory block. Is possible. Therefore, it is possible to prevent the threshold voltage of the memory cell from rising due to the hot electron phenomenon. Therefore, it is possible to improve the operational reliability of the semiconductor integrated circuit device having such a nonvolatile memory.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a main part circuit diagram of a memory cell region and a peripheral circuit region of the semiconductor integrated circuit device of FIG.

3 is a circuit diagram of an essential part of a memory cell region of the semiconductor integrated circuit device of FIG.

FIG. 4 is a cross-sectional view of essential parts of a memory cell in the semiconductor integrated circuit device of FIG.

5A is an explanatory diagram of a write operation state of the semiconductor integrated circuit device of FIG. 1, and FIG. 5B is an explanatory diagram of an operation state of the semiconductor integrated circuit device of FIG. 1 at the end of the write operation.

6A is an explanatory diagram of a write operation state of the semiconductor integrated circuit device of FIG. 1, and FIGS. 6B and 6C are explanatory diagrams of an operation state of the semiconductor integrated circuit device of FIG. 1 at the end of the write operation. is there.

FIG. 7 is an explanatory diagram for explaining an example of set voltage values of respective portions during a write operation and an erase operation of the semiconductor integrated circuit device of FIG.

FIG. 8A is an explanatory diagram of a write operation state of a semiconductor integrated circuit device which is another embodiment of the present invention;
FIG. 7B is an explanatory diagram of an operating state at the end of the write operation of the semiconductor integrated circuit device.

FIG. 9 is an explanatory view of a main part of an IC card using the semiconductor integrated circuit device of the present invention.

FIG. 10 is an explanatory diagram of a main part of a computer system using the semiconductor integrated circuit device of the present invention.

FIG. 11 is an explanatory diagram of an application example of a computer system using the semiconductor integrated circuit device of the present invention.

FIG. 12 is an explanatory diagram of an application example of a microprocessor system incorporating the semiconductor integrated circuit device of the present invention.

FIG. 13 is an explanatory view of a main part of a cordless telephone system incorporating the semiconductor integrated circuit device of the present invention.

FIG. 14 is an explanatory view of a main part of a digital still camera system in which an IC card having a semiconductor integrated circuit device according to the present invention is built-in.

FIG. 15 is an explanatory view of a main part of an automobile system incorporating a semiconductor integrated circuit device of the present invention.

[Explanation of symbols]

1 flash memory (semiconductor integrated circuit device) 2 semiconductor substrate 2n n well 2p p well 3 field insulating film 4 channel stopper region 5s source region 5d drain region 5i1 insulating film 5i2 insulating film 5f floating gate electrode 5c control gate electrode 6 interlayer insulating film 7 First layer wiring 8 Surface protective film 10 IC card (electronic circuit device) 10a Plastic substrate 10c Connector 11 Micro controller (control circuit) 12 Computer system 12a Notebook type personal computer 12b Disk top type personal computer 12c Pen Portable type personal computer 12cp Input-only pen 13 Microprocessor system 14 Cordless telephone system 14a Antenna 14b Analog front end part 14c Baseband part 14d -Dress telephone 14e Control unit 15 Digital still camera system 15a Optical system 15b Motor drive circuit 15c Aperture 15d Shutter 15e Image sensor 15f1, 15f2 Signal processing circuit 16 Automotive system 16a Air conditioning unit 16b Sensors 16c Engine 16d Engine control unit 16e Signal Processing section 16f Vehicle height control section 16g Suspension control section M Memory cell area MB Memory block MC Memory cell WL, WL0, WL1 ・ ・ ・ WLX Word line BL0, BL1 ・ ・ ・ BLn Main bit line BL SS, SS0, SS1・ SSn sub-source line (first
Source line) BLS, BLS0, BLS1 ... BLS n Sub bit line (first bit line) Q1S, Q1S0, Q1S1 ・ ・ ・ Q1Sn switch MOS ・ F
ET (first switching element) Q2S, Q2S0, Q2S1 ・ ・ ・ Q2Sn switch MOS ・ F
ET (second switching element) Q3S switch MOS • FET (third switching element) SMS wiring SMD wiring XADB row address buffer circuit AX row address signal XDCR row address decoder circuit Vrw, Vww, Vwv, Vew, Vev, Vrd , Vwd, V
ec Built-in voltage VS Built-in power supply circuit YADB Column address buffer circuit AY Column address signal YDCR Column address decoder circuit YG Column gate array circuit DR Data latch circuit SA Sense amplifier circuit DOB Data output buffer circuit DIB data input buffer circuit MP multiplexer circuit I / O External input / output terminal MC mode control circuit CSB control signal buffer circuit SVC source / well potential switching circuit R / B external terminal / CE, / OE, / WE, SC control signal terminal QD MOS ・ FET DDC, DDC0, DDC1 ・ ・ ・DDCn wiring QSE selection MOS / FET TR, TR0, TR1 ・ ・ ・ TRn wiring SAC CMOS amplifier QSAP0, QSAP1, QSAN0, QSAN1 MOS ・ F
ET QPR Precharge MOS ・ FET RPC, RPC0, RPC1 ・ ・ ・ RPCn wiring PC, PC0, PC1 ・ ・ ・ Pcn wiring Vpg, Vps, Vpd voltage Vs source voltage RAM random access memory MPU microprocessor FMF flash memory file KB Keyboard DP Display MSLOT Memory Slot FDD Floppy Disk Drive FD Floppy Disk FFC Flash File Card CPU Central Processing Unit SCI Serial Communication Interface I / OC I / O Circuit CONT Control Circuit MDP Mode Signal Input Terminal MD Mode Signal DBUS Data Bus ABUS Address Bus ROM read only memory A / DC analog-digital conversion circuit TRM transmission KBDC keyboard controller

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshihiro Tanaka 1-280, Higashi Koigakubo, Kokubunji City, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Inventor Michitaro Kanemitsu 5-20-1, Mizumizumotocho, Kodaira-shi, Tokyo Hiritsu Super LSI Engineering Co., Ltd. (72) Inventor Masataka Kato 1-280 Higashi Koigakubo, Kokubunji City, Tokyo Metropolitan Research Laboratory, Hitachi, Ltd. (72) Inventor Tetsuo Adachi 1-Chome, Higashi Koigakubo, Kokubunji, Tokyo No. 280, Central Research Laboratory, Hitachi, Ltd.

Claims (7)

[Claims] 1. A plurality of memory blocks dividedly arranged in a memory cell region on a semiconductor substrate, wherein each of the plurality of memory blocks has a control gate electrode laminated on an insulating film on a floating gate electrode. A plurality of non-volatile memory cells of the MIS-FET type having a two-layer gate electrode structure connected in parallel, and the source region and the drain region of the plurality of memory cells in each memory block are common semiconductor regions. A semiconductor integrated circuit device connected by a first source line and a first bit line, each of which is selected at the end of a write operation and an erase operation in a selected nonvolatile memory cell in the memory block. After turning off the non-volatile memory cell in the memory block where the non-volatile memory cell exists,
A semiconductor integrated circuit device, characterized in that a path is provided so as to remove a charge stored in a source region and a drain region of the nonvolatile memory cell. 2. The semiconductor integrated circuit device according to claim 1, wherein the path is a path provided separately for the first source line and the first bit line. apparatus. 3. The semiconductor integrated circuit device according to claim 2, wherein the path on the side of the first source line has a path electrically connected to a ground potential via a first switching element, The semiconductor integrated circuit device, wherein the path on the 1-bit line side has a path electrically connected to a second bit line made of a conductor via a second switching element. 4. The semiconductor integrated circuit device according to claim 1, wherein the path electrically connects a source region and a drain region of a non-volatile memory cell in the memory block through a third switching element. A semiconductor integrated circuit device having a path formed by: 5. A plurality of memory blocks divided and arranged in a memory cell region on a semiconductor substrate, wherein each of the plurality of memory blocks has a control gate electrode laminated on an floating gate electrode via an insulating film. A plurality of non-volatile memory cells of the MIS-FET type having a two-layer gate electrode structure connected in parallel, and the source region and the drain region of the plurality of memory cells in each memory block are common semiconductor regions. A semiconductor integrated circuit device connected by a first source line and a first bit line, each of which is selected at the end of a write operation and an erase operation in a selected nonvolatile memory cell in the memory block. After turning off all the non-volatile memory cells in the memory block containing the non-volatile memory cells, A method for operating a semiconductor integrated circuit device, comprising the step of allowing charges stored in a source region and a drain region of a memory cell to escape via separate paths. 6. A plurality of memory blocks dividedly arranged in a memory cell region on a semiconductor substrate, wherein each of the plurality of memory blocks has a control gate electrode laminated on a floating gate electrode via an insulating film. A plurality of non-volatile memory cells of the MIS-FET type having a two-layer gate electrode structure connected in parallel, and the source region and the drain region of the plurality of memory cells in each memory block are common semiconductor regions. A method of operating a semiconductor integrated circuit device comprising: a first source line and a first bit line connected to each other, wherein at the end of a write operation and an erase operation in a selected nonvolatile memory cell in the memory block, The charges stored in the source region and the drain region of the non-volatile memory cell are stored in the non-volatile memory in the memory block. In order to escape without passing through the cell,
A third electrically connected between a source region and a drain region of the nonvolatile memory cell in the memory cell block,
A method of operating a semiconductor integrated circuit device, comprising the step of turning on the switching element. 7. An IC card comprising the semiconductor integrated circuit device according to claim 1 and a control circuit for controlling the operation of the semiconductor integrated circuit device on a wiring board. An electronic circuit device characterized by: