JPH09152984A - Generalized data format converting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To store and transfer program code or data with high efficiency by converting source data to a standard processor format. SOLUTION: The block diagram of a standard processor data format encoder consists of five functional blocks, i.e., a header generating circuit 11, a source data file purser 12, a dual-buffer bank 13, a pack coded word connector and byte swapper 14, and a bit stream formatter 15. The functional block 14 packs each pack data word in specific format according to an Endian flag mark. Further, the bit stream formatter compose and assembles the header and pack coded word generated by the functional block 14 in the standard processor data format. Thus, the source data is converted to the standard processor format for storing and transmitting the processor program code and data.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to the storage, retrieval and transmission of processor code or data for different processor families.

[0002]

BACKGROUND OF THE INVENTION In many computer or processor systems, program and data memory form part of the system. Different microprocessor system families have different word lengths. For example, Motorola's 56000 Digital Signal Processor (DSP) family of microcodes has a word length of 24 bits, and Matsushita Electric's MN
The 1900 (DSP) microprocessor family has a word length of 40 bits.

The object code or data that needs to be loaded into the program or data memory area must follow a predetermined program word length. To meet this requirement, these data are stored in a 16-bit word length format. A formatted 16-bit word is divided into upper and lower bytes. In this big endian format, the upper byte is stored in the even address location and the lower byte is stored in the odd address location. Using this conventional file format, there is a waste of 1 byte per word if the word length is greater than 2 bytes and has an odd number of bytes. One dummy byte is added word by word such that the first byte of the program or data word begins at an even address. If this conventional file format is used to store data in an 8-bit wide PROM, there is a waste of one byte for each word stored (see Figure 6).

The number of processors in the commercial market is increasing at a surprising rate. In some computer systems, there is a need for more than one processor to solve complex problems. Some experts think that no one all-inclusive processor has the ability to solve complex computationally intensive problems. In many multiprocessor systems, each processor requires a separate program memory space to execute its object code. The word length of the program space varies depending on the type of processor. This means
Changing the program word length of the object code makes it difficult and troublesome to download the object code into the program memory space.

Different memory bank configurations need to be specially configured for individual processors in a multiprocessor computer platform of different processor families. Executing a very large dynamic application program in a multiprocessor environment requires program loading at run time. In such a system, the loading is performed by the monitoring entity. This supervising entity loads the program to a specific processor within the processors in the computer system. To allow data loading for individual processors,
A channel for processor microword length is required between the supervisory entity and the processor. In a multiprocessor environment, there are n different types of word lengths for the processor, and n physical channels are required between the supervisory entity and the processor.

[0006]

The various conventional methods have the above-mentioned problems.

The present invention provides a technique for translating data from the original binary data format into a standard processor data format suitable for transmission and storage. This format is invented for the purpose of storing the processor's original binary data for different word lengths. Any redundant data used to pad between processor words is completely removed. Thus, it is an effective and efficient data storage format for different processor word length requirements. The device in each processor is invented to produce a standard download data operation according to the word length specified in the data format. This device, also known as processor data row, enables the real-time standard processor data format to decode the data and load it into the target processor.

[0008]

SUMMARY OF THE INVENTION Different types of data for downloading to a target processor in a multi-processor environment are eliminated to eliminate redundant data packed between programs or data words downloaded to different types of target processors. To avoid having a transmission channel, the generalized data format translator comprises means for converting the original binary data into a standard processor data format for storage and transmission of data for different types of processor word lengths, Means for removing redundant memory packed between processor word lengths having an odd number of bytes, and means for decoding standard processor data formats and downloading data to said target processor. .

The present invention allows original data to be converted into standard processor formats for storing and transmitting processor program code and data. The processor code and data can be downloaded to the target processor using standard processor data formats. Transmission of data encoded in a standard processor data format may be performed using common serial channels. Decoding and downloading of processor data or code in a standard processor data format is performed by the processor data loader. The device extracts stored program data or transport program data and header information indicating the format of the target processor. Regarding the format information, a sequence is generated to enable the appropriate buffer so that the input data bytes are sent to their respective locations according to the target data format.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

1, 2, 3, 4, and 5 show embodiments of the present invention.

Encoding of Original Data FIG. 1 shows an exemplary embodiment of the present invention used in encoding an original data file consisting of processor object code or data. A block diagram of a standard processor data format encoder is shown with five functional blocks: a header generator circuit (shown at 11), an original data file parser (shown at 12), a dual buffer bank (shown at 13), and a packed code. It consists of a digitized word concatenator / byte swapper (shown at 14) and a bitstream formatter (shown at 15).

The operation of the encoding shown in FIG. 1 is shown in steps below. [11] SW1 is at Pt1.1 position during header generation. The header is generated based on the input value indicating the format of the original file to be encoded. SW1 is switched to Pt1.2 which allows the pack encoded data to be added after the header information after generating the header. [12] The original data file containing the program code or data is analyzed according to the word length (WL) original data file. The source data file parser 1.2 retrieves two processor codes or data words from the input source data file having a word length determined by the value of WL (unit is the number of bytes). This functional block
1.2 also transfers words to dual buffer bank 1.3 based on SW2 position. After any two encoded program codes or data are stored in the dual buffer bank, SW2 returns to its initial position. [13] Even address offset processor data or codewords are stored in even buffers and odd address offset words are stored in odd buffers. Odd offset address (also known as odd address)
Is determined by the value 2n + 1 and the even offset address (also known as the even address) is determined by the value 2n. The starting address is the input parameter,
That is, it is obtained from the start address. SW2 is in position Pt2.2 to load even offset addressing words and SW2 is in position Pt2.1 to load odd offset addressing words. The value of n is incremented by one step for every two processor codes or data loaded into the buffer. [14] 2 encoded based on the endianness indicator
The processor data are concatenated to form a pack coded word. Depending on the endian flag, the bytes within each subcoded word are byte swapped.
Each coded word is 16 bytes long. The number of sub-coded words in each coded word is equal to the value of WL. This function block 14 packs each packed data word into the format shown in FIG. 1 based on the endian flag indicator. SW3 is at the Pt3.1 position for every two processor code or data words concatenated and byte swapped for each subcoded word. [15] The bitstream formatter organizes and assembles the header and pack coded words generated by the functional block shown at 14 into a standard processor data format.

Standard Processor Data Format The standard processor data format has a file header to provide information for different programs and data codes. As shown in FIG. 5, the header is a 10-byte block. Following the header is the program code. The 10 byte header block consists of the base page address of the target memory, the address offset, the program / data size, the translated program word length (in bytes) and the little or big endian format indicator. The bitstream header below is k
7 illustrates a format description for storing a number of packed coded words.

The page address makes up to 256 pages addressed by a 256 address offset. Program sizes up to 64K words can be used. The endian format indicator specifies whether 2 bytes are swapped per 16-bit coded word.

The program loader must extract the header to set up the loading process. The address page and offset allow the loader to determine a starting location within the target processor's memory space. Program size provides the total number of program codes to load. Latching a program word in processor memory is determined by the word length indicator. If the endian indicator is set, the high and low bytes must be swapped. Thus, in a multiprocessor environment, this standard file format can be sent to the processor and loaded into memory using standard equipment for header decoding and data loading.

The data from the processor data loader memory is retrieved by a microcontroller or any other type of device capable of address and header generation. In a single processor environment, the header without target processor selection includes the following fields: (I) program size, (II) start address, (III) endian indicator, and (IV) target word length (header local to translator). Can be generated at will, which is optional). The starting address indicates the location in the first target processor program memory where the translation data should be stored. The program size indicates the length of the stored (source) program data converted into the total number of data words stored in the target memory. The endian indicator indicates whether byte swapping is required from the source program data to the target program data.

Due to byte swapping of odd data words (low bytes to high bytes and vice versa), the last byte of a data word is stored after the first byte of the next word. If the spare buffer is not used, the last word of the current word is clocked out only after the first byte of the next word, so the first byte of the current word is overwritten by the next succeeding byte. . Then the rearranged or converted data is
It will be latched in the target processor memory until the target program is completely downloaded. This is shown in FIG. However, due to this storage for odd byte target data words, the odd target word clock must be delayed by one byte clock, while the even target word clock is
It must be increased by the byte clock. For even byte target words, the word clock is consistent or fixed.

In summary, a variable word clock is only needed for odd byte target data words with byte swap. The even address word clock is n + 1 bytes long, while the odd address clock is n-1 bytes. Here, n is the target word length in bytes. The equations for obtaining the required word clocks (odd and even) with different combinations of input and output formats can be found in [47]. Even addresses refer to the first and every next alternating address where data is written, while odd addresses refer to the second and every alternating address.

FIG. 3 illustrates how the processor data loader accommodates single or multi-processor systems. [31] The microprocessor extracts the program code / data and adds the headers needed for data format translation for the target processor. There is an extra field (compared to a single processor) in the header for a multiprocessor environment to indicate the desired target processor. [32] In a multiprocessor environment, extra (extr
a) The decoder needs to select one (or more) of the target processor memories. A decoder is any device or circuit that can select the desired target memory. [33] The data format translator converts the stored program code / data into the target processor format specified in the header. [34] Processor memory stores conversion codes / data retrieved by different types of processors.
The memory is FIFO, buffer array, RAM, EPR
It includes any storage device such as an OM and other capable of storing digital data.

FIG. 4 illustrates converting a standard processor data format to a desired target format.

The operation of the illustrated embodiment is illustrated in steps below. [41] Receive source data and header information from the processing element. [42] Extract header information such as target word length, endian indicator, program size and address fields. [43] Since the first byte from the secondary buffer is invalid, initialize the address pointer to point one word before the starting address of the target memory. A "write and chip enable" signal is also generated at the same time. The counter and comparator (set to zero or final address + 1 depending on ascending or descending order) loads into the target memory according to the program size. The address pointer is incremented as each word of data is written to memory. [44] The following sequence is generated depending on the endian indicator and the target word length field. Endian indicator = 1 (byte swap) Odd byte target word Even address XX01, XX00 , XX11, XX10, ... XX00 , n An underlined binary sequence indicates that a byte is sent to the spare buffer. .

Odd address XX10, XX01, ..... n, n-1 Even byte target word Even and odd address XX01, XX00, XX11, XX10, ..... n, n-1 Endian indicator = 0 ( Non-byte swap) Even and odd byte target words Odd and even addresses XX00, XX01, XX10, .... n-1, n where XX length depends on word width, n is in binary form It is word wide. The length of the sequence depends on the target word length, while the array of sequences depends on the endianness indicator. The sequence generator stops once the last program word has been stored. [45] Decode the generated sequence and send the input data continuously to the desired buffer location so that the buffer is activated and the target program format is obtained. The sequence repeats each time a data word fills the buffer. [46] The buffer stores individual data bytes until a data word is formed. [47] Latch the data word formed with the address indicated by the address generator in the target memory. The word clock is fixed or variable depending on the endian indicator and the word width. The word clock consists of pulses at word clock timing as summarized below to latch the data stored in the buffer for the target memory. Word clock = n + (c ^* e) Target word width in n-byte units c 1 for odd address word clock 1 for even address word clock 1 e (endian indicator) 0 non-byte swap 1 byte swap [48] When the data word is latched with the word clock and written to memory, the address for program memory is incremented. Data Storage Efficiency of Standard Processor Data Format The calculation for data storage efficiency is based on the following formula:

Eff% = (D × 100) / (D + H + R) (Equation 1) D: number of bits of original data to be stored H: number of bits used for header description R: bit Based on the redundant bit storage used when encoding the stream and the format used for transmission, the efficiency is eff _{(wL = 3)} = 99.99962%.

Here, word length = 3 bytes R = 0 H = 8 × 8

[0026]

The generalized data format translator according to the present invention enables processor program code or data to be stored and transmitted in a standard data format referred to as a highly efficient standard processor format.

In the present invention, an apparatus is provided for translating processor data / codewords of different endian formats of arbitrary byte length into a standard format for transmission and storage. The present invention also provides that the device
Allows header decoding and loading of standard processor formats into the memory of the target processor in a single processor or multiprocessor computing environment.

The device can be implemented with very low hardware complexity.

[Brief description of the drawings]

FIG. 1 is a standard processor data format encoder according to an embodiment of the present invention.

FIG. 2 is an example of bytes to be rearranged during format decoding and data loading.

FIG. 3 is a processor data loader used in a single or multiprocessor system.

FIG. 4 Block of processor data loader

FIG. 5: Standard processor data format

[Figure 6] Packing of redundant bytes

[Explanation of symbols]

 11 Header Generator Circuit 12 Original Data Parser 13 Dual Buffer Bank 14 Pack Coded Word Concatenation and Byte Swapper 15 Bit Stream Formatter

Claims (2)

[Claims] 1. A means for (a) parsing an original input file into a word size of an arbitrary word length indicated by bytes specified for the input file format; and (b) concatenating adjacent words. Means for forming a packed coded word consisting of one even and one odd addressed processor word, and (c) a transformation having a header indicating the content and format of the data stored in the standard processor data format. A means for storing files, characterized in that it converts a raw binary input containing data or code for a particular processor into a standard processor data format for storage and transmission. Data format converter. 2. (a) means for extracting the header from a transport file, which is created by using the generalized data format conversion device according to claim 1, and (b) each memory word (target processor data width). Means for generating addresses to the target processor program memory in ascending (descending) order for (c), and (c) for the decoder or demultiplexer so that the storage file format is returned to its original location in the target file format. Means for generating a suitable sequence, said decoder or demultiplexer being also capable of generating a clock for switching the data bytes to the desired location, where (d) the data word is formed. The data word width to the target processor memory And means for latching into the decode a standard processor data format, and real-time decoding apparatus for loading data to the target processor.