JPH09152976A - Computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the execution speed of a process by scheduling a process so that a cache memory which holds the contents of a common memory is effectively utilized. SOLUTION: Processes 190 and 191 share the common memory 110. The processes 190 and 191 are executed by one of processors 101 and 103 and data which are referred to during the execution are stored in caches 102 and 104. Even when the common memory is referred to during the execution, the contents are stored in the cache memories. For example, when the process 190 alters the contents of the common memory 110, the alteration is recorded in the cache 102. For example, the process 191 tries to refer to the contents of the common memory that are altered by the process 190 at this time. In this case, the contents of the common memory 110 stored in the cache 102 are transferred to the processor 103 through a bus 106 and used by the process 103.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a computer system.

[0002]

2. Description of the Related Art In UNIX, a shared memory mechanism is mounted as one of means for interprocess communication. The UNIX shared memory mechanism allows a process to access a common memory area in the same manner as a normal memory access by making the common memory area accessible to a plurality of processes at the same time. Exchange data with. The advantages of the shared memory mechanism are:
Compared to other means of interprocess communication such as message communication, it does not require a special programming method attached to the mechanism. For message communication, a new way of thinking such as sending and receiving messages is required.
Access to the shared memory can be performed in the same manner as normal memory access, so there is no need to change the way of thinking of programming. However, access to the shared memory usually requires exclusive control. The data required for exclusive control is also placed on the shared memory.

The shared memory mechanism of UNIX originally realizes a communication mechanism between a plurality of processes which are time-divisionally executed on a single processor computer. Also, the shared memory mechanism acts on the address space of the process and does not affect the schedule of processes that can access the shared memory. Therefore, after executing a process that uses a certain shared memory, a process that does not use the shared memory is executed, and then a process that uses the shared memory is executed again in this order. When the last process is executed, the contents of the shared memory that the first executed process refers to and are stored in the cache are more likely to be evacuated from the cache memory, which may reduce the execution speed. There is a problem.

In recent years, shared memory multiprocessor computers have come to be used in systems that require high performance. Generally, a processor has a cache memory with a high access speed, and frequently used data and instructions are stored in the cache memory to reduce the memory access time and increase the execution speed. In the shared memory type multiprocessor computer, the cache of each processor in the computer maintains the coherence of contents (cache coherence) by some means.

When a program is executed on a shared memory type multiprocessor computer, it is known that the cache miss rate and the bus traffic required for cache coherence control greatly affect the program execution speed and the performance of the computer system itself. , The process scheduling method is designed to reduce cache misses. A typical method is affinity control that controls the execution processor of a process.
Reference (ASPLOS-VI Proceedings Sixth International Co
nference on Architectural Support for Programming
Language and Operating Systems, Scheduling and Pag
e Migration for Multiprocessor Compute Server). Affinity control aims to increase the execution speed of a program by effectively using the data once stored in the cache memory by fixing the execution processor of the process as much as possible. In this paper, the priority of the running process is temporarily raised and the time slice given to the process is substantially lengthened to fix the execution processor, effectively use the cache, and improve the program execution speed. I am trying.

When executing a program using a shared memory mechanism in a shared memory type multiprocessor computer which performs cache coherence control, coherent control between processors affects the program execution speed and the execution speed of the entire computer. In other words, when multiple processes that use the same shared memory are executed on different processors, when the shared memory contents are stored in the cache memory of one processor, they are cached in the processor of another processor. When a process that needs the contents of shared memory runs, the latter processor needs to copy the cache contents of the former processor. When a plurality of processes having such a relationship run on different processors at the same time to access the shared memory, a cache ping-pong phenomenon occurs in which the contents of the cache memory move back and forth between the processors. as a result,
The traffic on the bus connecting the processors increases,
This is a problem because the execution of the program becomes slow and the performance of the computer system itself deteriorates.

The shared memory mechanism of UNIX originally realizes a communication mechanism between processes that are time-divisionally executed on a single processor, and a shared memory is simultaneously accessed by a plurality of processes in a multiprocessor type computer. The problem is that it does not take this into consideration. As a document that affects the schedule of a set of specific processes (fair share schedule (The design of UNIX ope
rating system by Maurice J. Bach, Prentice-Hall,
pp. 255-257)). This is a process scheduling method that guarantees that a certain set of processes is given a certain percentage of CPU time or more.

UNIX is a registered trademark in the United States and other countries licensed by X / Open Company Limited.

[0009]

SUMMARY OF THE INVENTION The present invention provides a plurality of processes that can access the same memory area as compared to a conventional computer system that does not perform a special schedule for a plurality of processes that can access the same memory area. Affects the schedule and improves the process execution speed.

Further, with respect to the shared memory mechanism in the shared memory type multiprocessor computer with cache coherence control, it affects the schedules of a plurality of processes that can access the same memory area and improves the execution speed.

Further, regarding execution processors of a plurality of processes that can access the same memory area, the execution processors of the respective processes are reconfigured based on the CPU usage of the respective processes, and the execution speed of the processes using the shared memory. A computer system having a mechanism for improving

[0012]

A computer system according to the present invention comprises means for allocating and scheduling processors in a time-sharing manner with execution priorities for a plurality of processes, and creation of a memory area which can be commonly accessed by the processes. And the process has means for gaining access to the memory area. Regarding the creation of the memory area that multiple processes can access in common, the schedule of the process that can access the created memory area,
It has a means for requesting execution in consideration of accessing the memory area, or a means for requesting start and end of the schedule considering having access right to the common memory area during execution of the program. ing. In addition, whether the processes have a common memory area that can be accessed, the CPU usage of the processes in that case,
It has means for comparing the execution priority of each process and the execution processor to determine the process schedule and the effective processor.

By continuously scheduling a plurality of processes having the same execution processor that can access the same common memory area on a certain processor, the cache memory of the execution processor is used more effectively and a cache miss occurs. , Resulting in faster process execution. By raising or lowering the priority of processes that can access the same memory, when the scheduler selects processes, one processor continuously schedules processes that can access the common memory area,
In another processor, by suppressing the execution of processes that can access the common memory area, traffic required for cache coherence control between processors is reduced, and as a result, the execution speed of the entire computer system is improved. Based on the CPU usage of a set of processes that can access the same memory area and the CPU usage of each process, reconfiguring the execution processors of multiple processes that can access the same shared memory area The bus traffic required for cache coherent control is reduced, and as a result, the execution speed of the entire computer system is improved.

[0014]

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a process scheduling scheme, and more particularly to process scheduling when processes use shared memory as a means of interprocess communication.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a shared memory type multiprocessor computer. 102 and 104 are cache memories dedicated to the processors 101 and 103, respectively, and are managed by the processors connected to them. Processor 10
A plurality of processes for executing an operating system and application programs are running on Nos. 1 and 103. FIG.
However, the number of processors is set to two, but this does not limit the number of processors of the present invention. The process data is stored in the main memory 105. In FIG. 1, process 190,
191 shares the shared memory 110. Process 1
90 and 191 are executed by one of the processors 101 and 103, and the data referred to during execution is cache 10
2, 104 are stored. Even if the shared memory is referenced during execution, the contents are stored in the cache memory.
For example, suppose process 190 is running on processor 101. As process 190 modifies the contents of shared memory 110, the modification is recorded in cache 102. At this time, at the same time, the process 191 causes the processor 10
Process 191 and process 191
Suppose you try to refer to the contents of the shared memory changed by. At this time, the contents of the shared memory 110 stored in the cache 102 are transferred to the processor 1 via the bus 106.
03 is used for the process 191.

A first embodiment of the present invention will be described.
The first embodiment of the present invention relates to the scheduling of multiple processes that can access the same shared memory, and schedules such processes sequentially.

FIG. 2 shows an explanatory diagram of the data structure of the first embodiment of the present invention. The data structure of the first embodiment of the present invention will be described with reference to FIG. Reference numerals 200 and 220 are data structures that describe the state of the process. 200 includes an execution priority 201 of the process 20, a recent CPU usage 202 of the process 20, an execution processor 203 of the process 20, and a pointer 204 to a data structure expressing the address space of the process 20. 220 also includes the priority 221, the CPU usage 222, the execution processor 223, and the address space 224 of the process 22. 21
Reference numerals 0 and 230 are data structures that represent the address spaces of the processes 20 and 22, respectively. The address space of a process includes the execution code portion, the data portion, the stack portion of the process, and pointers 211 and 231 to the data structure managing the shared memory when the process can access the shared memory. A data structure 240 manages the shared memory and includes a pointer 241 to the shared memory management table 250. Reference numeral 250 is a shared memory management table for managing all shared memories in the computer system.
Holds information about the created shared memory. An entry is assigned to each created shared memory, a data structure 251 expressing a set of processes using the shared memory, a total CPU usage 252 of processes using the shared memory, and a shared memory priority. The schedule flag 253 is included. A data structure 270 describes information for each processor in the computer. 270
282 holds a pointer 281 to an entry in the shared memory management table 250 of the shared memory that is the target of the priority schedule in the processor 101, and a time 282 when the priority schedule of the process accessible to the shared memory indicated by 281 is started. Is included. Processor 10
The second information is described by 291 and 292. 281,
The process using the shared memory indicated by 291 is scheduled by each CPU with priority.

CPU usage 202, 22 of each process
2. The total CPU usage 252 of processes that can access the shared memory is calculated by the interrupt processing of the clock interrupt generated at regular time intervals. For example, assume that a clock interrupt occurs while the process 20 is running. The clock interrupt handler is a process state data structure of the process 20 and has a CPU usage amount of 200.
2 is incremented, and since the process 20 can access the shared memory 240, 252 which is the total CPU usage of the shared memory 240 is incremented. The CPU usage is attenuated at regular time intervals so that the CPU usage approximates the latest CPU usage. That is, the past CPU usage amount is forgotten as time passes.

The procedure for creating the shared memory will be described on the assumption that the process 20 requests the creation of the shared memory 240 which is to be subjected to the shared memory priority schedule. When the process 20 requests the operating system to create the shared memory, the system allocates one free entry in the shared memory management table 250 and creates the shared memory management structure 240. If the shared memory priority schedule is requested at the time of creation request, the priority schedule flag 253 of the assigned entry in the shared memory management table is set. When the process 20 requests the access right to the shared memory 240, the entry 211 for the shared memory is set in the data structure 210 that represents the address space of the process 20. As a result, the shared memory 240 is incorporated in the address space of the process 20, and the process 20 can access the shared memory 240. Although only one shared memory is accessible to the process in FIG. 2, this does not limit the number of shared memories available to the process.

FIG. 3 shows a flow chart of the first embodiment of the present invention. FIG. 3 shows a process scheduling method according to the first embodiment of the present invention. The operation of the first embodiment will be described according to this flowchart. The operating system switches the running process for some reason, such as when the running process sleeps waiting for some event, or when the running process runs out of the given CPU time. In the system, there is a queue that holds the processes waiting to run, and they are managed according to the execution priority of the processes. The process that has been running until now is described as process 20, and the processor that performs process switching is described as 101. First,
In step 1001, it is checked whether or not there is a shared memory currently preferentially scheduled by the processor 101. This can be understood by referring to the priority schedule shared memory 281 of the processor structure table 270. If there is a shared memory with priority scheduling, go to step 1002,
If not, the process proceeds to step 1010. Step 1010
Then, one process with the highest priority is selected from the runnable process queue. It is assumed that the process selected here is the process 22. If the selected process 22 has the accessible shared memory (step 1011), the total CPU usage of the shared memory among the shared memories in which the priority schedule flag 253 accessible by the process 22 is set is The smallest number is selected (step 1012). Step 1012 is the shared memory CPU usage 2 of the shared memory entry accessible by the process 22 of the shared memory management table 250.
52 is inspected. In step 1013, the pointer to the entry of the shared memory management table 250 of the shared memory with the smallest CPU usage selected in step 1012 is set to the priority schedule shared memory 281 of the entry of the processor 101 of the processor structure table 270.
In the priority schedule start time 282. And the selected process 22
To run.

When the processor which performs the process switching is implementing the priority schedule, that is, the pointer to the entry of the shared memory table 250 is registered in the priority schedule shared memory 281 of the entry of the processor 101 of the processor structure table 270. If so, step 1002 is performed. Here, the processor 101
Describes that the shared memory 240 is the target of the priority schedule. First, step 100
In 2, the execution processor checks whether or not there is a runnable process whose execution priority is higher than the predetermined constant K4 in the processor 101. If there is, go to step 1015, and if not, go to step 1003. In step 1003, it is checked whether or not there is a process in which the execution processor 101 has a higher execution priority than the process that has been executed up to now, and the difference between them is larger than a predetermined constant K3.
If there is, go to step 1015, and if there is not, go to step 1004
Proceed to. In step 1015, the priority schedule shared memory 281 of the entry of the processor 101 in the processor structure table 270, the priority schedule start time 2
82 is set to invalid and the process proceeds to step 1010. In step 1004, next, the processor structure table 27
The time set in the priority schedule start time 282 of the entry of the processor 101 of 0 is checked and the elapsed time from that time to the present exceeds the predetermined constant K0, or is registered in the priority schedule shared memory 281. There is no runnable process whose execution processor 101 is 101 that is accessible to the shared memory 240 (step 1005), or there is such a process, but the priority 201 of the process 20 which has been running until now is compared. If the difference is larger than K1 (step 1006), the processor 10 in the processor structure table 270 is processed.
The priority schedule shared memory 281 and the priority schedule start time 282 of the entry 1 are set to be invalid (step 1009), and the process proceeds to step 1010. If not, step 1007 is executed. In step 1007, the process having the highest execution priority among the processes using the shared memory 240 registered in the priority schedule shared memory 281 is selected. If the selected process is process 22, then in step 1008, the execution priority 2 of the process 22 selected in step 1007 is set.
Priority 201 of process 20 that has been running 21
Set to.

In this embodiment, by scheduling the processes in which the execution processors are the same and can access the same shared memory as continuously as possible, the contents of the shared memory once stored in the cache of the processor can be used without being expelled from the cache. It is characterized by doing. For example,
The process 20 using the shared memory 240 is the processor 10
Suppose that the shared memory 240 was accessed while traveling at the scheduled time of 1. The contents of the accessed shared memory are cached in the cache 102. At some point after this, process switching occurs, but if the contents of the shared memory remain in the cache 102 at this time, the cache 102 can be effectively used when the process that may use this is next scheduled. This reduces the load on the memory system and improves the execution speed.

In this embodiment, when a process capable of accessing the shared memory for which the priority schedule is designated by a certain processor is scheduled, the shared memory and the use start time are recorded. The use start time is recorded by waiting for the process with the highest execution priority waiting to run in that processor to schedule the processes that use the same shared memory as continuously as possible. To schedule a low process, so that it will not occupy the processor, and to return to the schedule according to the normal process execution priority after a certain period of time after using shared memory Is.

A second embodiment of the present invention will be described.
The second embodiment of the present invention relates to a schedule of a plurality of processes using the same shared memory but different execution processors. Priority schedule When a process that has access to the specified shared memory starts running on a processor, the process that has access to this shared memory and is another processor is the executing processor, reduces the execution priority, and It is characterized by reducing the use of shared memory in the processor.

FIG. 4 shows the data structure of the second embodiment of the present invention. Reference numerals 400 and 420 are data structures that describe the state of the process. Reference numeral 400 denotes the execution priority 401 of the process 40, and execution priority 40 of the process 40 before reduction.
2, the execution priority lowering flag 403 indicating whether the execution priority of the process 40 is forcibly lowered, and the execution processor 405 of the process 40 are included. The state of the process 42 is described in the same manner as the process 40 by 421, 422, 423, 425 of 420. Reference numerals 404 and 424 denote data structures 410 and 430 that describe the address spaces of the processes 40 and 42, respectively. 41 if the process has shared memory accessible
0 and 430 have entries 411 and 431 that point to a data structure that manages the shared memory, and 411 and 431 indicate a data structure 440 that manages the shared memory. In this example, processes 40, 42 can access the same shared memory 440, which is described by 440. The shared memory 440 contains an index 441 to 450, which is the system's shared memory management table. The shared memory management table 450 is a table for managing information on all the shared memories in the created system, and an entry is assigned to each shared memory. For each entry, the number 451 of the processor that preferentially uses the shared memory, the set 452 of processes that can access the shared memory, and the priority schedule flag 45.
Contains three. Reference numeral 480 is a list of procedures to be called at a certain point in the future, which is a list of elements including a calling time 481, a calling procedure 482, and an argument 483 to be passed to the procedure 482. This list 480 is inspected at the time of clock interrupt processing generated at fixed time intervals, and at time 481, the system schedules to call the procedure 482 with 483 as an argument.

The method of creating the shared memory, specifying the priority schedule of the shared memory, and granting the access right to the process are the same as in the first embodiment.

FIG. 5 shows a flowchart of the second embodiment of the present invention. FIG. 5 shows a process scheduling method in the second embodiment of the present invention. Second of the present invention
The embodiment will be described with reference to this flowchart. The operating system switches the execution process with some kind of trigger. At that time, the process to be run next must be selected. In the system, there is a queue that holds processes that are waiting to run, and they are managed according to the execution priority of the processes. In the following, the processor in which process switching is performed will be described as 101. First, in step 2001, one process having the highest execution priority is selected with the processor 101, which is about to perform process switching, as the execution processor. This is process 40. In the following step 2002, if the process 40 selected in step 2001 cannot access the shared memory for which the priority schedule is designated, nothing is done and the process 40 is run. It is assumed that the selected process 40 can access the shared memory 440 for which the priority schedule is designated.
If there is a shared memory that can be accessed by the process selected in step 2001 and that has a priority schedule specified, a loop 20 is performed for each of the shared memories that are not specified as the priority use processor.
Execute 20. Whether or not the preferential use processor is designated is determined by the preferential use processor designation 45 of the entry corresponding to the shared memory in the shared memory management table 450.
You can tell by inspecting 1. It is assumed that the process 40 can access the shared memory 440 that is designated as the priority schedule but is not designated as the priority use processor.

First, in step 2003, the shared memory 4
The priority use processor designation of 40 is set to the processor 101. Then, step 2004 to step 2007 are executed for each process that can access the shared memory currently being inspected. In steps 2004 to 2007, the process can access the shared memory 440, and the execution processor is other than the processor 101.
In (Step 2004), it is not running (Step 200
5), the execution priority has not been lowered (step 20)
06) The process priority is lowered by a predetermined constant P0 to obtain a new execution priority (step 2007). For example, the process 42 can access the shared memory 440 for which the priority schedule is designated, and the processor 1
It is assumed that a processor other than 01 is an execution processor and is waiting for running. If the process 42 can access the shared memory that has already been designated as the priority processor and the process execution priority is lowered,
do nothing. This can be seen by inspecting the execution priority lowering flag 423 of the process 42. If the execution priority has not been lowered, the current execution priority 421 is saved in the pre-lowering execution priority 422, the process execution priority is lowered by a predetermined constant P0, and a new priority is set to 421. . If the process 42 is running, the priority of the process 42 is not lowered and is left as it is. if,
If there is another process that can access the shared memory 440, the execution priority of the process is lowered by the same procedure. When all the processes that can access the shared memory 440 have been checked, the process proceeds to step 2008. In step 2008, it is checked whether there is a process whose execution priority has been lowered. If not, the priority processor designation 451 of the shared memory 440 registered previously is invalidated (step 2010). If there is a process whose execution priority has been lowered, a procedure for canceling the preferential use processor designation after a certain time is registered in 480 (step 2009). Since there is a process whose execution priority has been lowered, a shared memory priority use processor deselection procedure is registered in 480 after a predetermined constant time T0 so as to schedule the argument as the shared memory 440. This procedure is called by the system after T0,
Cancels the priority use processor specification of the shared memory, and restores the execution priority of the process whose execution priority has been lowered. This procedure will be described later. Process 40 in the shared memory that is not designated as another priority processor
If they are accessible, the inspection from step 2003 is similarly performed for them.

FIG. 6 shows a flowchart of the second embodiment of the present invention. FIG. 6 shows a procedure for deselecting the preferential use processor of the shared memory. The priority processor designation cancellation procedure will be described with reference to FIG. This procedure is registered in 480 and is called with the shared memory as an argument to cancel the preferential use processor designation. here,
44 shared memory for canceling priority processor designation
0, the process 42 is a process whose execution priority is lowered by the designation of the shared memory priority use processor.
The priority processor specification cancellation procedure is called with the shared memory as an argument. This procedure is called with the shared memory 440 as an argument, and the shared memory management table 452
For all processes using this shared memory 440, refer to steps 2101 to 21.
Perform 02. In step 2101, the execution priority lowering flag of the process is checked. If the execution priority has been lowered, the process advances to step 2102 to restore the process execution priority. As for the process 42, the execution priority lowering flag 423 of the structure 420 of the process 42 is checked to see whether the execution priority has been lowered. Since the execution priority of the process 42 is lowered, the pre-lowering execution priority 422 of the structure 420 is set to the execution priority 421, and the execution priority lowering flag 42 is set.
Clear 3 This procedure is performed for all processes using the shared memory 440. Finally, in the following step 2103, the priority use processor designation 451 of the shared memory is set to be invalid.

The second embodiment of the present invention is characterized in that the traffic for cache coherence control is reduced by adjusting the priority of processes using the same shared memory. Further, the shared memory is usually used under exclusive control of a program, but when there are a plurality of processes that frequently access the same shared memory, it has an effect of reducing the time required for this exclusive control. Ordinary exclusive control attempts to acquire the resource several times, if the resource cannot be acquired, surrenders the processor, and tries to acquire the resource again after a specified time. If the resource cannot be acquired by this control continuously, process switching frequently occurs and the efficiency deteriorates. Further, since the data itself related to exclusive control is stored in the shared memory, cache misses frequently occur. In this embodiment, when a process using shared memory runs on a processor, the priority of the process waiting to run on another processor is lowered, so that a process unrelated to another can run. If so, they are run to reduce the cache misses related to shared memory and the time required for exclusive control. If there is no other process running, the process runs even if the priority is lowered, and the parallelism of the program is maintained.

A third embodiment of the present invention will be described.
The third embodiment of the present invention is characterized in that the execution processor of the process is reconfigured based on the CPU usage of the process that can access the shared memory.

FIG. 7 shows the data structure of the third embodiment of the present invention. The data structure of the third embodiment of the present invention will be described with reference to FIG. Each process has a process state structure that describes the state of the process. Reference numerals 300 and 320 in FIG. 7 denote process state structures of the processes 30 and 32, respectively. The process state structure of the process 30 will be described as an example. A process state structure 300 of the process 30 is an execution processor 30 of the process 30.
1, a recent CPU usage 302 of the process 30, a migration prohibition flag 303, and a pointer 304 to a data structure describing the address space of the process 30. Also for the process 32, the process information structure 320
Is similarly described by. The data structure 310 representing the address space indicated by 304 is a process 30.
Contains a pointer to the data that describes the shared memory, if any is accessible in the address space. The process 30 is accessible to the shared memory 340 and includes 310 in 311 with a pointer to 340. The shared memory is managed by the shared memory management table 350. Reference numeral 350 has information on all shared memories in the system, and an entry is assigned to each shared memory. The entry describing each shared memory is a migration inspection prohibition flag 351 and shared memory C.
It includes a PU usage amount 352 and a pointer 353 to a shared memory CPU usage amount per processor 360. Shared memory for each processor CPU usage 360 is shared memory 3
It expresses how much a process accessible to 40 has run on which processor. In FIG. 7, 3
Only four processors 61, 362, 363, 364 are drawn, but this does not limit the number of processors. 370 represents the idle time for each processor.

FIG. 8 shows a flow chart of the third embodiment of the present invention. A third embodiment of the present invention will be described with reference to FIG. FIG. 8 is a flowchart regarding the clock interrupt processing. The clock interrupt is generated in each processor in the computer system, and each processor processes the clock interrupt independently. First, in step 3001, when a clock interrupt occurs, it is checked whether a process is running on the processor that received the interrupt. If the process was not running, eg idle, then do nothing. Here, the interrupted processor is 1
It is assumed that the process 30 is running at 01 and 101 at that time. In the following step 3002, it is checked whether the interrupted process uses the shared memory. If used, the CPU usage amount of each processor of the shared memory accessible by the process and the CPU usage amount of the shared memory are incremented (steps 3003 and 300).
4). Since the process 30 uses the shared memory 340, the CPU shared memory usage 352 of 340, and the CPU shared memory usage 361 corresponding to 101 of 340 are incremented. If you are not using shared memory, do nothing. Each CPU usage is attenuated at regular time intervals so that the recent CPU usage is approximated. By this clock interrupt processing, it is required to determine which processor and how much the process using the shared memory has run. CPU usage of process Calculated as in the first embodiment. The idle time of the processor is obtained by incrementing the idle time corresponding to the processor in which the interrupt occurs when there is no process running at the time of the clock interrupt.

9 and 10 show a flow chart of the third embodiment of the present invention. A third embodiment of the present invention will be described with reference to FIGS. 9 and 10
The flow chart shown in is scheduled by the system to be executed at regular time intervals. First, in step 3101, the shared memory management table 350 is scanned,
Among the shared memories that are not prohibited from migration inspection, the shared memory with the highest shared memory CPU usage is found. Whether or not each shared memory is prohibited from migration inspection is checked by the migration inspection prohibition flag 351 of each entry in the management table 350. CPU
The usage amount is acquired from the entry 352 of the shared memory management table. In the following step 3102, step 310
It is checked whether the CPU usage of the shared memory found in 1 is less than a predetermined constant S0, and if so, the process is not migrated and the process ends. Otherwise, proceed to step 3103. In step 3103, the shared memory CPU usage of each processor is checked, and there is a processor having a predetermined constant S1 or more among the shared memory CPU usage of each processor, and the idle time of the processor is a predetermined constant. It is checked whether there is a processor that is S2 or higher. If there is such a processor, go to step 3105, and if not, go to step 3104. Here, the shared memory 340 has a shared memory CPU usage of S
It is assumed that the value is 0 or more. The shared memory usage table 360 for each CPU is checked from the management table entry 353 of the shared memory 340. If the usage amount corresponding to the processor 101 is 361 and it is S1 or more and the idle time 371 corresponding to the processor 101 is S2 or more, the process proceeds to step 3105. If no such processor can be found for the shared memory currently being tested, the process proceeds to step 3104. In step 3104, the migration inspection is not prohibited, the shared memory having the second largest shared memory CPU usage amount after the previously selected shared memory is selected, and the process proceeds to step 3102. In step 3105, the processor having the longest idle time is selected from the processors having a predetermined constant S1 or more in the shared memory CPU usage amount.

In step 3105, the shared memory 340,
It is assumed that the processor 101 is selected. In step 3106, the number of selected processes is set to 0.
Steps 3107 to 3113 are performed for all processes that can access the selected shared memory 340. The process 30 will be described as an example. First, the migration prohibition flag 303 of the process state structure 300 is inspected (step 3107). If it is prohibited, the process proceeds to step 3113 to check another process. Otherwise, proceed to step 3108. In step 3108,
It is checked whether the execution processor 301 of the process state structure 300 is the processor 101 selected as the migration destination. If so, the migration prohibition flag 303 of the process state structure 300 of this process 30 is set to prohibit migration (step 3115), and the process proceeds to step 3113 to check another process. If not, the CPU usage 302 of the process 30 is checked (step 3109). If the CPU usage 302 is equal to or less than the predetermined constant S3, the process proceeds to step 3110, and if not, the process proceeds to step 3113. In step 3110, the execution processor 301 of the process state structure 300 of the process is changed to the execution processor 101 selected as the migration destination, and the migration prohibition flag 30 is set.
Set 3 In step 3111, if the number of selected processes is incremented and the number of processes that changed the process execution processor is S4 (step 3
112) Finish. Otherwise, check other processes that have access to the selected shared memory. When all the processes that can access the selected shared memory have been inspected, the migration inspection prohibition flag 351 of the selected shared memory is set and the process ends (step 3114).

In the third embodiment of the present invention, processes using the same shared memory are executed by the same processor as much as possible, so that the entry of the shared memory in the cache of the processor is effectively used. As a decision policy of the execution processor, it is C to some extent that the shared memory can be accessed.
Execution of process using PU Causes a processor to execute a process that uses the same shared memory but uses less CPU. The reason why the process that uses less CPU is moved is that if the process that has been executed for a certain time or longer is changed to the executing processor, the efficiency of using the cache entry other than the shared memory deteriorates.

The three embodiments of the present invention have been described above. In these embodiments, the target of the schedule is the process, but the schedule system of the embodiments of the present invention can be applied to the schedule of a plurality of threads sharing one address space, and the same effect can be expected.

[0038]

As described above, according to the present invention, the process execution speed is improved because the process is scheduled so as to effectively use the cache memory that holds the contents of the shared memory with respect to the process schedule that uses the shared memory.
Further, the cache copy between processors is also reduced, so that the execution speed of the computer system itself is improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a shared memory type multiprocessor computer according to the present invention.

FIG. 2 is an explanatory diagram of a data structure showing the first embodiment of the present invention.

FIG. 3 is a flowchart showing a first embodiment of the present invention.

FIG. 4 is an explanatory diagram of a data structure showing a second embodiment of the present invention.

FIG. 5 is a first flowchart showing a second embodiment of the present invention.

FIG. 6 is a second flowchart showing the second embodiment of the present invention.

FIG. 7 is an explanatory diagram of a data structure showing a second embodiment of the present invention.

FIG. 8 is a first flowchart showing a third embodiment of the present invention.

FIG. 9 is a second flowchart showing the third embodiment of the present invention.

FIG. 10 is a third flowchart showing the third embodiment of the present invention.

[Explanation of symbols]

 101, 103 ... Processor, 102, 104 ... Cache memory, 105 ... Main storage device, 190, 191 ... Process address space, 110 ... Shared memory, 106 ... Bus.

 ─────────────────────────────────────────────────── --- Continuation of the front page (72) Inventor Yutaka Enmitsu 1099 Ozen, Aso-ku, Kawasaki City, Kanagawa Prefecture, Ltd. System Development Laboratory, Hitachi, Ltd. Hitachi, Ltd. Systems Development Laboratory, address 1099 (72) Inventor Shigeo Takasaki 5030 Totsuka-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture Hitachi Software Development Division, Hitachi Ltd.

Claims (8)

[Claims] 1. A method for scheduling a process according to an execution priority for a plurality of processes, creation of a memory area that can be commonly accessed by the processes, and the process acquiring an access right to the memory area. A computer system comprising means for requesting the system to change the execution priority of a process group that can access the memory area or the execution processor to schedule. 2. The schedule of a plurality of processes according to claim 1, wherein the same common memory area is accessible and the execution processors are the same processor. When selecting a process to be run, if the process that has been running in the processor has a common memory area that can be accessed, the executing processor can access another common memory area in the processor. A computer system that prioritizes processes to be selected and continuously runs processes that can access the same common memory area. 3. A means for requesting a system to schedule a process according to claim 2, regarding a schedule of a plurality of processes that can access the common memory area when the common memory area is created. Computer system having. 4. One of processes that can access a common memory area relates to a schedule of a plurality of processes that can access the common memory area during its execution,
A computer system having means for requesting the system to start and end the process schedule according to claim 2. 5. The computer system according to claim 1, wherein in a computer system having a plurality of processors, the common memory area can be accessed and the execution processors are different processors. When selecting a process to run, if the selected process has a common memory area that is accessible, the common memory area is accessible and the execution processor is set to a processor different from the processor. A computer system that lowers the process execution priority. 6. A means for requesting a system to schedule a process according to claim 5, which relates to scheduling of a plurality of processes accessible to the common memory area when the common memory area is created. Computer system having. 7. One of processes that can access a common memory area relates to a schedule of a plurality of processes that can access the common memory area during its execution,
A computer system having means for requesting the system to start and end the process schedule according to claim 5. 8. A computer system having a plurality of processors according to claim 1, wherein an execution processor of a plurality of processes that can access a common memory area, and a certain period of time of each of the processes that can access the common memory area. When creating a shared memory so as to reset the execution processor of the process that can access the common memory area at regular intervals according to the CPU usage amount in the computer and the idle time of each processor in the computer system A computer system having means for requesting the system.