JPH09148492A - Electronic component packaging device - Google Patents
Electronic component packaging deviceInfo
- Publication number
- JPH09148492A JPH09148492A JP7299917A JP29991795A JPH09148492A JP H09148492 A JPH09148492 A JP H09148492A JP 7299917 A JP7299917 A JP 7299917A JP 29991795 A JP29991795 A JP 29991795A JP H09148492 A JPH09148492 A JP H09148492A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- lead frame
- electronic component
- packaging device
- component packaging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、電子部品のチップ
を内部リードフレームに載置して樹脂モールドした電子
部品パッケージ装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component packaging device in which a chip of an electronic component is placed on an internal lead frame and resin-molded.
【０００２】[0002]
【従来の技術】従来の電子部品パッケージ装置の断面構
造を図２に示す。１１は偏平状の内部リードフレーム
で、この内部リードフレーム１１上には、低背チップ１
２と高背チップ１３がダイボンドされている。１４、１
５は外部リードフレームである。低背チップ１２は外部
リードフレーム１４とワイヤ１６ａにより接続され、高
背チップ１３は外部リードフレーム１５とワイヤ１６ｂ
により接続され、低背チップ１２と高背チップ１３とは
ワイヤ１６ｃにより接続されている。そして、これらの
構造部材は、外部リードフレーム１４、１５の外部リー
ド端子を除いて樹脂１７によりモールドされている。2. Description of the Related Art A cross-sectional structure of a conventional electronic component packaging device is shown in FIG. Reference numeral 11 denotes a flat internal lead frame, and the low-profile chip 1 is mounted on the internal lead frame 11.
2 and the high-height chip 13 are die-bonded. 14, 1
Reference numeral 5 is an external lead frame. The low-profile chip 12 is connected to the external lead frame 14 and the wire 16a, and the high-profile chip 13 is connected to the external lead frame 15 and the wire 16b.
The low-height tip 12 and the high-height tip 13 are connected by a wire 16c. Then, these structural members are molded with resin 17 except the external lead terminals of the external lead frames 14 and 15.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、従来の
電子部品パッケージ装置は、低背チップ１２と高背チッ
プ１３を内部リードフレーム１１にダイボンドする際、
チップ１２、１３が位置ずれを生ずることがあった。ま
た、低背チップ１２と外部リードフレーム１４を接続す
るワイヤ１６ａ、高背チップ１３と外部リードフレーム
１５を接続するワイヤ１６ｂ、低背チップ１２と高背チ
ップ１３間を接続するワイヤ１６ｃに、それぞれ段差が
生じて、ワイヤボンディングが困難な場合もあり、ま
た、接続ワイヤ１６ａ、１６ｂおよび１６ｃの長さが長
くなって、高周波特性が悪化していた。また、モールド
した低背チップ１２、高背チップ１３の発熱量が大きい
場合、内部リードフレーム１１の金属厚みを大きくして
放熱量を大きくする必要があった。 そこで、本発明
は、ダイボンドされるチップの位置ずれが生じることが
なく、チップと外部リードフレームとのワイヤボンディ
ングおよびチップ間のワイヤボンディングをさほど段差
なく行うことができ、かつ、高周波特性を改善し、そし
て熱放散を改善した電子部品パッケージ装置を提供する
ことを目的とする。However, in the conventional electronic component packaging apparatus, when the low-height chip 12 and the high-height chip 13 are die-bonded to the internal lead frame 11,
The chips 12 and 13 were sometimes displaced. In addition, a wire 16a connecting the low profile chip 12 and the external lead frame 14, a wire 16b connecting the high profile chip 13 and the external lead frame 15, and a wire 16c connecting the low profile chip 12 and the high profile chip 13 are respectively provided. In some cases, there is a step, which makes it difficult to perform wire bonding, and the connection wires 16a, 16b, and 16c become long, which deteriorates high-frequency characteristics. Further, when the heat generation amount of the molded low-height chip 12 and high-height chip 13 is large, it is necessary to increase the metal thickness of the internal lead frame 11 to increase the heat radiation amount. Therefore, the present invention does not cause a displacement of a die-bonded chip, can perform wire bonding between a chip and an external lead frame and wire bonding between chips without much difference, and improves high frequency characteristics. And, it is an object of the present invention to provide an electronic component packaging device with improved heat dissipation.
【０００４】[0004]
【課題を解決するための手段】本発明は、上記目的を達
成するために、下記手段を採ることを特徴とする。 １．内部リードフレームにチップを載せて電気的に接続
し、該チップと外部リードフレームとをワイヤボンディ
ングして、樹脂モールドしてなる電子部品パッケージ装
置において、前記内部リードフレームに前記チップの載
置される一個もしくは複数個の窪地が形成されてなる電
子部品パッケージ装置。The present invention is characterized by adopting the following means in order to achieve the above object. 1. In an electronic component packaging device in which a chip is placed on an internal lead frame and electrically connected, and the chip and the external lead frame are wire-bonded and resin-molded, the chip is placed on the internal lead frame. An electronic component packaging device in which one or a plurality of depressions are formed.
【０００５】２．前記複数個の窪地の深さが同一もしく
は相違してなる請求項１記載の電子部品パッケージ装
置。[0005] 2. The electronic component packaging device according to claim 1, wherein the depths of the plurality of depressions are the same or different.
【０００６】３．前記内部リードフレームに形成された
前記窪地の裏面金属が、前記樹脂モールドの外部に露出
してなる上記１または上記２記載の電子部品パッケージ
装置。[0006] 3. 3. The electronic component package device according to 1 or 2 above, wherein a back surface metal of the recess formed in the internal lead frame is exposed to the outside of the resin mold.
【０００７】以上のように、本発明は、内部リードフレ
ームに窪地を設けて、この窪地にチップを載置するの
で、チップの位置ずれがなく、また、複数個の高さの異
なるチップの場合には、高さに合わせて窪地の深さを調
整して、前記複数個のチップの高さをほぼ一定にできる
ので、ボンディングワイヤの長さも一定になり、かつ、
チップと外部リードフレーム間およびチップ同士間のワ
イヤボンディングをさほど段差なく行うことができ、ボ
ンディングワイヤも短くなるので高周波特性が向上す
る。また、発熱量の大きいチップの内部リードフレーム
の裏面金属をモールド樹脂の外部に露出させることによ
り、放熱量を大きくすることができると共に、該内部リ
ードフレームの露出した裏面金属をセット基板のグラン
ド電極にそのまま半田付けすることにより、グランドの
強化も図ることができる。As described above, according to the present invention, since the inner lead frame is provided with the depression and the chip is placed in this depression, there is no displacement of the chip, and in the case of a plurality of chips having different heights. In addition, since the depth of the depression is adjusted according to the height to make the height of the plurality of chips almost constant, the length of the bonding wire is also constant, and
Wire bonding between the chip and the external lead frame and between the chips can be performed without much steps, and the bonding wire is shortened, so that high frequency characteristics are improved. Further, by exposing the back surface metal of the internal lead frame of the chip, which generates a large amount of heat, to the outside of the mold resin, it is possible to increase the amount of heat dissipation, and at the same time, the exposed back surface metal of the internal lead frame is connected to the ground electrode of the set substrate. The ground can be strengthened by directly soldering to the ground.
【０００８】[0008]
【発明の実施の形態】以下に、本発明の電子部品パッケ
ージ装置の実施例について図１を参照して説明する。同
図は本実施例に係る電子部品パッケージ装置の断面によ
る概略の形態を示すものである。１は内部リードフレー
ムで、コバール材などの金属よりなり、厚みが２００μ
ｍである。この内部リードフレーム１には、１００μｍ
の浅い窪地１ａと５００μｍの深い窪地１ｂがプレスな
どにより形成されている。前記浅い窪地１ａには、高さ
３００μｍのＩＣの低背チップ２ａがダイボンディング
され、前記深い窪地１ｂには、高さ７００μｍのＩＣの
高背チップ２ｂがダイボンディングされている。BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of an electronic component packaging device of the present invention will be described below with reference to FIG. The figure shows a schematic form of a cross section of the electronic component packaging apparatus according to the present embodiment. Reference numeral 1 denotes an internal lead frame, which is made of metal such as Kovar and has a thickness of 200μ.
m. The inner lead frame 1 has 100 μm
The shallow depression 1a and the deep depression 1b of 500 μm are formed by pressing or the like. An IC low-profile chip 2a having a height of 300 μm is die-bonded to the shallow depression 1a, and an IC high-profile chip 2b having a height of 700 μm is die-bonded to the deep depression 1b.
【０００９】３、４はそれぞれ外部リードフレームであ
る。外部リードフレーム３は、低背チップ２ａとワイヤ
５ａによりボンディングされている。また、外部リード
フレーム４は、高背チップ２ｂとワイヤ５ｂによりボン
ディングされている。さらに、低背チップ２ａと高背チ
ップ２ｂは、ワイヤ５ｃによりボンディングされてい
る。低背チップ２ａ、高背チップ２ｂなどの前記部材
は、外部リードフレーム３、４の外部リード端子３ａ、
４ａと内部リードフレーム１に設けた窪地１ｂの裏面金
属１ｃとを露出させて、樹脂６によりモールドされる。Reference numerals 3 and 4 are external lead frames. The external lead frame 3 is bonded to the low-profile chip 2a and the wire 5a. The external lead frame 4 is bonded to the high-profile chip 2b and the wire 5b. Further, the low-height chip 2a and the high-height chip 2b are bonded by the wire 5c. The members such as the low-profile chip 2a and the high-profile chip 2b are the external lead terminals 3a of the external lead frames 3 and 4,
4a and the backside metal 1c of the recess 1b provided in the internal lead frame 1 are exposed and molded with the resin 6.
【００１０】以上のように、本実施例は、低背チップ２
ａ、高背チップ２ｂの高さに合わせて、そのダイボンド
される内部リードフレーム１の所定場所に窪地１ａ、１
ｂを設けているので、低背チップ２ａ、高背チップ２ｂ
が所定の場所に位置ずれを生じることなくダイボンドさ
れる。また、低背チップ２ａ、高背チップ２ｂの高さが
一定になるので、低背チップ２ａ、高背チップ２ｂ間の
ワイヤボンディングが容易となる。As described above, this embodiment has the low profile chip 2
a, the recesses 1a, 1 are provided at predetermined positions of the inner lead frame 1 to be die-bonded according to the height of the high-profile chip 2b.
b is provided, so low profile tip 2a and high profile tip 2b
Are die-bonded in place without displacement. Further, since the heights of the low-height chip 2a and the high-height chip 2b are constant, wire bonding between the low-height chip 2a and the high-height chip 2b becomes easy.
【００１１】また、本実施例においては、内部リードフ
レーム１に設けた窪地１ｂの裏面金属１ｃが、樹脂６か
ら露出しているので、該露出裏面金属１ｃをセット基板
（図示せず）のグランド電極に直接かつ短距離で接続で
きるので、グランドが強化され周波数特性が向上すると
共に、放熱効果も改善される。Further, in this embodiment, since the back surface metal 1c of the recess 1b provided in the internal lead frame 1 is exposed from the resin 6, the exposed back surface metal 1c is grounded on the set substrate (not shown). Since it can be directly connected to the electrodes in a short distance, the ground is strengthened, the frequency characteristics are improved, and the heat dissipation effect is also improved.
【００１２】[0012]
【発明の効果】本発明は、以上のように、内部リードフ
レームに窪地を設け、この窪地にチップを載置してダイ
ボンドするので、チップの位置ずれが生じず、チップと
外部リードフレーム間をさほど段差なくワイヤボンディ
ングすることができる。As described above, according to the present invention, since the recess is formed in the internal lead frame and the chip is placed on the recess and die-bonded, the chip is not displaced and the chip and the external lead frame are not separated from each other. Wire bonding can be performed without a step.
【００１３】また、複数個の高さの異なるチップをダイ
ボンドする場合には、その高さに合わせて前記窪地の深
さを調整するで、前記複数個のチップの高さをほぼ一定
にすることができて、チップ間のワイヤボンディングを
段差なく行うことができる。このように、段差のないワ
イヤボンディングにより接続ワイヤが短くなり、高周波
特性が改善される。When a plurality of chips having different heights are die-bonded, the height of the plurality of chips can be made substantially constant by adjusting the depth of the depression according to the height. As a result, wire bonding between chips can be performed without a step. In this way, the stepless wire bonding shortens the connecting wire and improves the high frequency characteristics.
【００１４】また、本発明は、発熱量の大きいチップが
ダイボンドされる内部リードフレームの窪地の裏面金属
をモールド樹脂の外部に露出させるので、チップの放熱
量を大きくすることができると共に、該内部リードフレ
ームの露出裏面金属をセット基板のグランド電極にその
まま半田付けすることにより、グランドの強化も図るこ
とができる。Further, according to the present invention, since the back surface metal of the recess of the internal lead frame to which a chip having a large amount of heat generation is die-bonded is exposed to the outside of the molding resin, it is possible to increase the amount of heat dissipation of the chip and It is possible to strengthen the ground by directly soldering the exposed backside metal of the lead frame to the ground electrode of the set substrate.
【図１】 本発明の電子部品パッケージ装置の一実施例
の断面形態図FIG. 1 is a sectional form view of an embodiment of an electronic component packaging device of the present invention.
【図２】 従来の電子部品パッケージ装置の断面形態図FIG. 2 is a cross-sectional view of a conventional electronic component packaging device.
１ 内部リードフレーム １ａ、１ｂ 窪地 １ｃ 裏面金属 ２ａ 低背チップ ２ｂ 高背チップ ３、４ 外部リードフレーム ５ａ、５ｂ、５ｃ ワイヤ ６ 樹脂 1 Internal lead frame 1a, 1b Recess 1c Backside metal 2a Low profile chip 2b High profile chip 3, 4 External lead frame 5a, 5b, 5c Wire 6 Resin
Claims (3)
気的に接続し、該チップと外部リードフレームとをワイ
ヤボンディングし、樹脂モールドしてなる電子部品パッ
ケージ装置において、 前記内部リードフレームに前記チップの載置される一個
もしくは複数個の窪地が形成されてなる電子部品パッケ
ージ装置。1. An electronic component package device comprising a chip mounted on an internal lead frame for electrical connection, wire bonding between the chip and an external lead frame, and resin molding, comprising: An electronic component packaging device in which one or a plurality of recesses to be placed are formed.
相違してなる請求項１記載の電子部品パッケージ装置。2. The electronic component packaging device according to claim 1, wherein the depths of the plurality of depressions are the same or different.
記窪地の裏面金属が、前記樹脂モールドの外部に露出し
てなる請求項１または請求項２記載の電子部品パッケー
ジ装置。3. The electronic component packaging device according to claim 1, wherein a back surface metal of the recess formed in the internal lead frame is exposed to the outside of the resin mold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7299917A JPH09148492A (en) | 1995-11-17 | 1995-11-17 | Electronic component packaging device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7299917A JPH09148492A (en) | 1995-11-17 | 1995-11-17 | Electronic component packaging device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09148492A true JPH09148492A (en) | 1997-06-06 |
Family
ID=17878495
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7299917A Pending JPH09148492A (en) | 1995-11-17 | 1995-11-17 | Electronic component packaging device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09148492A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003522416A (en) * | 2000-02-02 | 2003-07-22 | インフィネオン テクノロジーズ アクチエンゲゼルシャフト | Semiconductor component having contact portion provided on lower side and method of manufacturing the same |
| US6693350B2 (en) | 1999-11-24 | 2004-02-17 | Denso Corporation | Semiconductor device having radiation structure and method for manufacturing semiconductor device having radiation structure |
| US6703707B1 (en) | 1999-11-24 | 2004-03-09 | Denso Corporation | Semiconductor device having radiation structure |
| US6946730B2 (en) | 2001-04-25 | 2005-09-20 | Denso Corporation | Semiconductor device having heat conducting plate |
| JP2005300485A (en) * | 2004-04-16 | 2005-10-27 | Renesas Technology Corp | Semiconductor device |
| CN102157500A (en) * | 2011-03-04 | 2011-08-17 | 南通富士通微电子股份有限公司 | Semiconductor package |
| JP2012212863A (en) * | 2011-03-30 | 2012-11-01 | Internatl Rectifier Corp | Dual compartment semiconductor package using temperature sensor |
| JP2013232552A (en) * | 2012-04-27 | 2013-11-14 | Lapis Semiconductor Co Ltd | Semiconductor device and measurement device |
| JP2013232544A (en) * | 2012-04-27 | 2013-11-14 | Lapis Semiconductor Co Ltd | Resin sealing method and manufacturing method of semiconductor device |
| JP2016187059A (en) * | 2016-08-03 | 2016-10-27 | ラピスセミコンダクタ株式会社 | Semiconductor device and measurement instrument |
| US9787250B2 (en) | 2012-04-27 | 2017-10-10 | Lapis Semiconductor Co., Ltd. | Semiconductor device and measurement device |
-
1995
- 1995-11-17 JP JP7299917A patent/JPH09148492A/en active Pending
Cited By (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6967404B2 (en) | 1999-11-24 | 2005-11-22 | Denso Corporation | Semiconductor device having radiation structure |
| US6693350B2 (en) | 1999-11-24 | 2004-02-17 | Denso Corporation | Semiconductor device having radiation structure and method for manufacturing semiconductor device having radiation structure |
| US6703707B1 (en) | 1999-11-24 | 2004-03-09 | Denso Corporation | Semiconductor device having radiation structure |
| US6798062B2 (en) | 1999-11-24 | 2004-09-28 | Denso Corporation | Semiconductor device having radiation structure |
| US6891265B2 (en) | 1999-11-24 | 2005-05-10 | Denso Corporation | Semiconductor device having radiation structure |
| US6998707B2 (en) | 1999-11-24 | 2006-02-14 | Denso Corporation | Semiconductor device having radiation structure |
| US6960825B2 (en) | 1999-11-24 | 2005-11-01 | Denso Corporation | Semiconductor device having radiation structure |
| US6992383B2 (en) | 1999-11-24 | 2006-01-31 | Denso Corporation | Semiconductor device having radiation structure |
| JP2003522416A (en) * | 2000-02-02 | 2003-07-22 | インフィネオン テクノロジーズ アクチエンゲゼルシャフト | Semiconductor component having contact portion provided on lower side and method of manufacturing the same |
| US6946730B2 (en) | 2001-04-25 | 2005-09-20 | Denso Corporation | Semiconductor device having heat conducting plate |
| US6963133B2 (en) | 2001-04-25 | 2005-11-08 | Denso Corporation | Semiconductor device and method for manufacturing semiconductor device |
| JP2005300485A (en) * | 2004-04-16 | 2005-10-27 | Renesas Technology Corp | Semiconductor device |
| CN102157500A (en) * | 2011-03-04 | 2011-08-17 | 南通富士通微电子股份有限公司 | Semiconductor package |
| US8637981B2 (en) | 2011-03-30 | 2014-01-28 | International Rectifier Corporation | Dual compartment semiconductor package with temperature sensor |
| JP2012212863A (en) * | 2011-03-30 | 2012-11-01 | Internatl Rectifier Corp | Dual compartment semiconductor package using temperature sensor |
| US8860198B2 (en) | 2011-03-30 | 2014-10-14 | International Rectifier Corporation | Semiconductor package with temperature sensor |
| US9054119B2 (en) | 2011-03-30 | 2015-06-09 | International Rectifier Corporation | Dual compartment semiconductor package |
| JP2013232552A (en) * | 2012-04-27 | 2013-11-14 | Lapis Semiconductor Co Ltd | Semiconductor device and measurement device |
| JP2013232544A (en) * | 2012-04-27 | 2013-11-14 | Lapis Semiconductor Co Ltd | Resin sealing method and manufacturing method of semiconductor device |
| US9787250B2 (en) | 2012-04-27 | 2017-10-10 | Lapis Semiconductor Co., Ltd. | Semiconductor device and measurement device |
| US10243515B2 (en) | 2012-04-27 | 2019-03-26 | Lapis Semiconductor Co., Ltd. | Semiconductor device and measurement device |
| US10622944B2 (en) | 2012-04-27 | 2020-04-14 | Lapis Semiconductor Co., Ltd. | Semiconductor device and measurement device |
| JP2016187059A (en) * | 2016-08-03 | 2016-10-27 | ラピスセミコンダクタ株式会社 | Semiconductor device and measurement instrument |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100359681C (en) | Semiconductor device and its lead frame | |
| TWI245429B (en) | Photosensitive semiconductor device, method for fabricating the same and lead frame thereof | |
| US6847104B2 (en) | Window-type ball grid array semiconductor package with lead frame as chip carrier and method for fabricating the same | |
| WO2002009180A1 (en) | Plastic package base, air cavity type package and their manufacturing methods | |
| JP2004153220A (en) | Lead frame, its manufacturing method, plastic molding semiconductor device and its manufacturing device | |
| US5612853A (en) | Package for a power semiconductor device | |
| US20090072334A1 (en) | Semiconductor device, pre-mold package, and manufacturing method therefor | |
| JPH1167809A (en) | Semiconductor device | |
| JPH09148492A (en) | Electronic component packaging device | |
| JP2002334975A (en) | Support structure for semiconductor device, ccd semiconductor device, manufacturing method therefor and package for ccd semiconductor device | |
| US6645792B2 (en) | Lead frame and method for fabricating resin-encapsulated semiconductor device | |
| JPH11330314A (en) | Semiconductor device structure, manufacture thereof, and lead frame used therefor | |
| JP2000349222A (en) | Lead frame and semiconductor package | |
| JPH08236665A (en) | Resin sealed semiconductor device and manufacture thereof | |
| JP2001177007A (en) | Semiconductor device and manufacturing method thereof | |
| JP2000150725A (en) | Semiconductor device and its manufacture | |
| JP2713141B2 (en) | Semiconductor device | |
| KR19990086280A (en) | Semiconductor package | |
| KR20010061847A (en) | Heatsink merged semiconductor package and memory module having the package | |
| JP2000304638A (en) | Connection structure of sensor chip | |
| KR100439188B1 (en) | equipment for molding of semiconductor package | |
| JPH07221211A (en) | Semiconductor device | |
| JPH05291345A (en) | Semiconductor device | |
| JPH07193179A (en) | Lead frame | |
| JPH11195743A (en) | Semiconductor device and manufacture thereof |