JPH09146514A - Crt display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable simplifying a deflection driving section and performing easily a VCCI measure without variation of luminance of a screen, in a CRT display device of a multi-scan type. SOLUTION: A display clock generation section 1 generates a clock signal C2 of a prescribed fixed display timing. Horizontal and vertical deflection driving sections 6, 7 generate horizontal and vertical deflection current Ih, Iv in accordance with horizontal and vertical synchronizing signal Hs2, Vs2 generated by a horizontal and vertical synchronization generation section 5 based on the clock signal C2, and drives a deflection yoke 8 of a CRT 9. A video signal processing means 3 outputs an input video signal S1 as a video signal S2 being adaptable for display timing in accordance with difference of timing between a clock signal C1 indicating timing of the input video signal and the display clock signal C2. A video amplifying section 8 amplifies the video signal 2 and supplies it to the CRT 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CRT display device, and more particularly to a multi-scan CRT display device used in a computer system or the like.

[0002]

2. Description of the Related Art A conventional CRT display device of this type has a plurality of video signals with different synchronization timings, for example, 640.
X480 dots, 800x600 dots, 1024x7
In order to support a video signal of an image of 68 dots or the like, the display timing is made to follow according to the synchronization timing of the input video signal.

[0003]

As described above, in the conventional CRT display device, the display timing is adjusted with respect to various input video signals, and the CRT is driven and displayed, so that it operates in a wide frequency wave range. A drive circuit is needed,
The circuit configuration becomes complicated and the number of partial points increases. Further, since the drive frequency changes over a wide range, the frequency components of the unnecessary radiation noise generated from the device are distributed over a wide range, so that the number of countermeasure parts for suppressing the unnecessary radiation noise below the VCCI specified value increases. Further, since the raster density changes according to the change of the display timing, there is a problem that the screen brightness changes depending on the synchronization timing of the input video signal.

An object of the present invention is to provide a multi-scan type CRT capable of handling input video signals with various synchronization timings.
In a display device, it is an object of the present invention to provide a CRT display device in which a drive circuit can be simplified, there is no fluctuation in screen brightness, and VCCI measures can be easily taken.

[0005]

SUMMARY OF THE INVENTION The CRT display device of the present invention enables display with a constant display timing for input video signals of various synchronization timings. Specifically, a display timing generation unit that generates a predetermined constant display timing, a drive unit that deflects and drives the CRT in synchronization with the display timing, and a synchronization timing based on the synchronization signal of the input video signal. And a video signal processing means for adjusting the input video signal to the display timing and outputting the video signal as a video signal displayable on the CRT based on the display timing and the synchronization timing.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. The CRT 9 drives the deflection yoke 8 by the horizontal deflection current Ih and the vertical deflection current Iv to display an image according to the video signal S3.

By the way, the horizontal deflection current Ih and the vertical deflection current Iv are deflection currents having a predetermined display timing predetermined for display. Also, the video signal S3
Is a video signal which has been signal-processed so as to meet a predetermined constant display timing.

That is, by the display clock generator 1,
A display clock signal C2 having a predetermined display timing for display is generated, and this display clock signal C2 is supplied to the horizontal / vertical synchronization generator 5 to generate a horizontal synchronization signal Hs2 and a vertical synchronization signal Vs2, respectively. After that, by the horizontal deflection drive unit 6 and the vertical deflection drive unit 7,
The horizontal deflection current Ih and the vertical deflection current Iv are generated respectively.

Further, the video signal processing means 3 converts the input video signal S1 into the video signal S having a predetermined display timing.
It is converted to 2, amplified by the video amplifier 8 and supplied to the CRT 9 as a video signal S3.

The video signal processing means 3 receives a clock signal C1 indicating the synchronization timing of the input video signal S1 and a clock signal C2 indicating a predetermined display timing predetermined for display, respectively, and based on the timing difference. The input video signal S1 is converted into a video signal S2 having a predetermined display timing. The synchronization detector 2 is
Input horizontal synchronizing signal Hs1 and vertical synchronizing signal Vs1
Is detected to generate the clock signal C1.

Next, the video signal processing means 3 will be described.

FIG. 2 is a block diagram showing an example of the video signal processing means 3. In the figure, an A-D converter 31
Digitizes the input video signal S1. The buffer memory 32 temporarily stores the video data output by the AD converter 31.

The video data processing unit 33 receives the input clock signal C1 and the display clock signal C2 to obtain the timing difference, reads the video data once stored in the buffer memory 32, and displays a predetermined constant display. Process video data to meet timing. In this case, the video data thinning processing or interpolation processing is performed according to the difference between the display timing and the synchronization timing of the input video signal.

The buffer memory 34 temporarily stores the video data output from the video data processing unit 33, then reads it out at a predetermined constant display timing and outputs it to the DA conversion unit 35. The DA converter 35 converts the video data output from the buffer memory 34 into a video signal S2 and outputs the video signal S2 to the video amplifier 4.

By setting the vertical synchronizing frequency of the display timing to, for example, about 75 Hz, it is possible to reduce the flickering of the screen.

[0017]

As described above, according to the present invention, the deflection drive section operates at a constant frequency by displaying the input video signals at various timings at the preset constant display timing. It has the effects that it can be simplified, there is little fluctuation in the brightness of the screen, and the measures against VCCI can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a video signal converting means 3 shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 display clock generation part 2 synchronization detection part 3 video signal processing means 5 horizontal / vertical synchronization generation part 6,7 deflection drive part 8 deflection yoke 9 CRT 31 A-D conversion part 32,34 buffer memory 33 video data processing part 35 D- A converter C1, C2 clock signal S1, S2, S3 video signal Hs1, Hs2 horizontal sync signal Vs1, Vs2 vertical sync signal

Claims (2)

[Claims] 1. A display timing generating means for generating a predetermined fixed display timing, a driving means for deflecting and driving a CRT in synchronization with the display timing, and an input video signal based on a synchronizing signal of the input video signal. Sync timing generating means for generating sync timing; and video signal processing means for outputting the input video signal as a video signal which can be displayed by the CRT in conformity with the display timing based on the display timing and the synchronization timing. CRT display device characterized by: 2. The video signal processing means includes an AD converter for digitizing the input video signal, and the AD converter.
A buffer memory that temporarily stores the video data output by the D conversion unit, and a buffer memory that temporarily stores the video data based on the timing difference between the display timing generated by the display timing generation means and the synchronization timing generated by the synchronization timing generation means. A video data processing unit for reading out the video data stored therein and performing thinning processing or interpolation processing on the video data so as to match the display timing, and D for analogizing the video data processed by the video data processing unit. The CRT display device according to claim 1, further comprising a -A conversion unit.