JPH09139077A - Two-stage boost voltage circuit, semiconductor memory using the circuit and computer system using the memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a two-stage boost voltage circuit technique which can reduce the current consumption of the high-voltage generator compared with the case where a single body of high-voltage power source is used. SOLUTION: The boost voltage circuit which boosts the voltage level from 0V to VCH is composed of a low-voltage power source VCC and a high-voltage power source VCH different in voltage level and a NMOS transistor QN1 and a PMOS transistor QN2 connected to the respective power sources. First, using the low-voltage power source VCC, the input of a preboost signal IN1 preboosts the NMOS transistor QN1 from 0V to VCC-Vth level. After that, the high- voltage power source VCH is used to boost the voltage from the VCC-Vth level to the VCH level by the input of the boost signal IN2 and accordingly, the voltage is boosted in two-stages from 0V to VCH level to output an output signal OUT.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a boost voltage circuit technology, and more particularly to a two-stage boost voltage circuit suitable for use in boosting an output voltage of an output buffer or the like in a semiconductor memory such as a synchronous DRAM and the like. The present invention relates to a semiconductor memory used and a technique effectively applied to a computer system using the semiconductor memory.

[0002]

2. Description of the Related Art For example, according to a study by the inventor, it is considered that an output buffer of a synchronous DRAM is boosted to a high voltage level by a pumping capacity. Such a synchronous DR
Regarding technology related to semiconductor memory such as AM, for example, issued by Ohmsha Co., Ltd. on November 30, 1984,
"LSI Handbook" edited by The Institute of Electronics and Communication Engineers, P4
85-P533.

[0003]

In the boost circuit technology of the synchronous DRAM as described above, in order to enable high frequency operation, a relatively low power supply voltage (VCC) supplied from the outside is received. In the technology for forming a high voltage that enables the circuit to operate at high speed internally, if the circuit that obtains such a high voltage is an internal boost power supply (high voltage: VCH) instead of boosting by pumping, this high voltage is generated. Since it is necessary to increase the driving capability of the high voltage generator, it is considered that reducing the current consumption of the high voltage generator is an important factor.

Therefore, an object of the present invention is to combine a low-voltage power source and a high-voltage power source and use a method of boosting in two steps, so that the current consumption of the high-voltage generator is higher than that when the high-voltage power source is used alone. It is an object of the present invention to provide a two-stage boost voltage circuit capable of reducing the power consumption, a semiconductor memory using the same, and a computer system using the semiconductor memory.

[0005] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0006]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the two-stage boost voltage circuit of the present invention is a combination of a low-voltage power supply and a high-voltage power supply, and the relative low voltage is VCC and the high voltage is VCH by controlling the switching elements connected to each. , And if the threshold voltage is Vth, first use a low-voltage power supply to
To VCC-Vth level, then boost from VCC-Vth level to VCH level using a high voltage power supply, and 0V to VCH level is increased to 2
It is boosted and output in stages.

Specifically, as a switching element, a drain is connected to a low voltage power source, a pre-boost signal is input to the gate, and a source is connected to a drain of a PMOS transistor described later, and an NMOS transistor,
The source is connected to a high voltage power supply, the boost signal is input to the gate, and the drain is composed of a PMOS transistor connected to the source of the above-mentioned NMOS transistor.

With this configuration, first, a pre-boost signal is input to the gate of the NMOS transistor to input 0V to VC.
Pre-boost to C-Vth level, then PMOS
Input the boost signal to the gate of the transistor to VCC
-Boost from Vth level to VCH level,
A signal boosted in two steps from 0V to VCH level can be output from a common connection node of the source of the MOS transistor and the drain of the PMOS transistor.

In the semiconductor memory of the present invention, the two-stage boost voltage circuit is used as an output buffer or the like, a memory array including at least a plurality of memory cells, a decoder and address buffer for selecting the memory cells, a data read and The semiconductor memory has an input / output buffer for writing, and this semiconductor memory is particularly adapted to a synchronous DRAM.

Further, the computer system of the present invention uses the semiconductor memory as a storage device and has at least a central processing unit and its peripheral circuits in addition to the storage device.

Thus, in the two-stage boost voltage circuit which is a combination of the low-voltage power supply and the high-voltage power supply, the current consumption of the high-voltage generator can be reduced by using the method of boosting in two stages, and this can be further reduced. It is possible to reduce the power consumption of the used semiconductor memory, computer system, or the like.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a basic circuit diagram showing a two-stage boost voltage circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram of a two-stage boost voltage circuit according to the present embodiment, and FIG. 3 is a two-stage boost voltage circuit. 4 is a circuit diagram showing an output buffer using a circuit, FIG. 4 is a waveform diagram in the output buffer, FIGS. 5 and 6 are circuit diagrams showing a high voltage generator for generating a high voltage power supply, and FIG. 7 is a two-stage boost voltage circuit. FIG. 8 is a block diagram showing a synchronous DRAM using a synchronous DRAM.
It is a block diagram which shows the computer system using.

First, the basic configuration of the two-stage boost voltage circuit according to the present embodiment will be described with reference to FIG.

The two-stage boost voltage circuit of this embodiment is
For example, a boost voltage circuit that boosts the voltage level from 0 V to VCH is used, and switching is performed that is connected to the low voltage power supply VCC and the high voltage power supply VCH and the low voltage power supply VCC and the high voltage power supply VCH, respectively, which have different voltage levels. It is composed of an NMOS transistor QN1 and a PMOS transistor QN2 as elements, and outputs a two-step boost output signal OUT by inputting a pre-boost signal IN1 and a boost signal IN2.

The NMOS transistor QN1 has a drain connected to the low voltage power supply VCC, a gate to which the pre-boost signal IN1 is input, and a source connected to the drain of the PMOS transistor QN2 and output as an output signal OUT. In this NMOS transistor QN1, the pre-boost signal IN1 is used by using the low voltage power supply VCC.
Is pre-boosted from 0V to the VCC-Vth level.

The source of the PMOS transistor QN2 is connected to the high voltage power source VCH, and the boost signal I
N2 is input, and the drain is connected to the source of the NMOS transistor QN1 and output as the output signal OUT. In the PMOS transistor QN2, the high voltage power supply VCH is used, and the boost signal IN2 is input to boost the voltage from the VCC-Vth level to the VCH level.

Next, regarding the operation of this embodiment, 0 V
The two-stage boosting method from VCH to VCH will be described based on the waveform diagram of FIG.

First, in the circuit including the low voltage power supply VCC and the NMOS transistor QN1, the pre-boost signal I
N1 is set to "High" and the NMOS transistor QN1
Is turned on and the output signal OUT is output by using the low voltage power supply VCC.
Is pre-boosted from 0V to VCC-Vth level.

After that, in the circuit including the high voltage power supply VCH and the PMOS transistor QN2, the boost signal IN
2 is set to “Low” and the PMOS transistor QN2 is turned to O
N, and the output signal OUT is set to V using the high voltage power supply VCH.
Boost from CC-Vth level to VCH level. Thereby, the voltage level can be boosted in two steps from 0V to VCH.

The two-stage boost voltage circuit as described above can be used for an output buffer as shown in FIG. 3, for example. This output buffer is an NMOS transistor QN
In addition to the two-stage boost voltage circuit composed of 1 and the PMOS transistor QN2, a level conversion circuit for controlling the boost signal IN2 from 0V to the VCH level, a NAND gate NA
ND1, NOR gate NOR1, inverter IV1, driver D, PMOS transistor QN3, NMOS transistors QN4 to QN7 and resistors R1 and R2.

In this configuration, the NAND gate NAN
The output data signal D is applied to D1 and the NOR gate NOR1.
OjT and the output enable signal DOCkB are input, the boost signal IN2 is controlled from 0V to the VCH level by the level conversion circuit, and the two-stage boost voltage circuit, C
The output enable signal DOC is output via the PMOS transistor QN3 and the NMOS transistor QN4 of the MOS structure and the NMOS transistors QN5 to QN7 of the output stage.
The output data I / Oj is outputted when kB is "Low".

In this output buffer, the output data signal DOjT is "High" as shown in the waveform diagram of FIG.
When h ", the pre-boost signal IN1 generated from the output data signal DOjT changes from 0V to VCC-Vt.
The output signal OUT is pre-boosted to the h level and further boosted by the boost signal IN2 from the VCC-Vth level to the VCH level.

After that, when the output signal OUT is at the VCH level, the PMOS transistor whose source is supplied with the output signal OUT is turned on, the output MOS gate control signal DOBPO is raised to the VCH level, and "High".
The output data I / Oj of h ″ is read.

As described above, even when the two-stage boost voltage circuit is used for the output buffer and the output signal OUT is boosted to the VCH level for reading the output data I / Oj, it is boosted in two steps from 0V to VCH. As a result, the consumption current of the high-voltage generator can be reduced as compared to the high-voltage power source alone.

In order to generate this high voltage power supply VCH, a high voltage generator as shown in FIGS. 5 and 6, for example, is used. In FIG. 5, capacitors C1 to C5 and N are used.
It is a constant supply unit composed of MOS transistors QN8 to QN15, and is a generator unit which constantly pumps the capacitors C1 to C5 by the pulse signals AD and BD and holds the VCH level. FIG. 6 shows a NAND gate N
AND2,3, NOR gate NOR2, capacitor C6
To C10, inverters IV3 to IV13, PMOS transistors QN16 to QN20, NMOS transistor Q
The operating-time supply unit includes N21 to QN29, and is a generator unit that holds the VCH level by pumping the capacitors C6 to C10 by the pulse signal OSCH generated by the oscillator during operation of the high voltage power supply VCH. Note that VHTB is a test signal.

Further, an output buffer using a two-stage boost voltage circuit is used, for example, in a 16M-bit synchronous DRAM as shown in FIG. This synchronous DRAM has two banks and is
In addition to the memory array M-ARY corresponding to k0 and 1, the row decoder R-DCR, the column decoder C-DCR and the sense amplifier SA, a row address buffer R-AB,
Refresh counter RC, column address buffer C
-AB, column address counter C-AC, input buffer IB, output buffer OB, control circuit & timing generation circuit CONT & TG, power supply circuit PS and the like.

In this synchronous DRAM, the high-voltage power supply VCH, which is a feature of the present invention, is an internal power supply generated from the generator of the power supply circuit PS, and the low-voltage power supply VCC is supplied from the outside. . Further, the two-stage boost voltage circuit which is a feature of the present invention is used, for example, in the output buffer OB which needs to be boosted to the VCH level for reading output data.

The basic operation of this synchronous DRAM is
It has the same storage control method as DRAM, and requires precharge and refresh in order to perform read and write operations. These operation modes are characterized in that the DRAM controls the clock timing, while the synchronous DRAM controls using a command signal. This command signal conforms to the DRAM. / C
It is determined by a combination of input signal levels such as S, / RAS, / CAS, and / WE. The commands, addresses and data are input / output in synchronization with the basic clock signal CLK.

Therefore, according to the two-stage boost voltage circuit of the present embodiment, the low-voltage power supply VCC and the high-voltage power supply VCH having different voltage levels and the NMOs connected to them respectively.
S transistor QN1 and PMOS transistor QN
2 is configured to boost from 0V to VCH, from 0V to VCC-Vth level, VCC-
By boosting in two steps from the Vth level to the VCH level, it is possible to reduce the current consumption of the high voltage generator compared to when it is used as a single high voltage power supply. Furthermore, a semiconductor such as a synchronous DRAM using the same can be used. It is possible to reduce the power consumption of the memory.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,

For example, the case where the two-stage boost voltage circuit of the above-mentioned embodiment is applied to the synchronous DRAM has been described, but the present invention is not limited to the above-mentioned embodiment and is widely applied to all DRAMs. It is possible.

Further, it is widely used as a storage device for various systems such as a computer system, a digital still camera system, and an automobile system, not limited to the case where it is used for each storage device such as a synchronous DRAM. The computer system will be described with reference to FIG.

In FIG. 8, this computer system comprises a bus, a central processing unit CPU, a peripheral device control section, and a synchronous DRAM (SD) of the present invention as a main memory.
RAM) and its control unit, SRAM as backup memory and backup parity and its control unit,
It is composed of a ROM storing a program, a display system, and the like.

The peripheral device control section is connected to an external storage device, a keyboard KB and the like. Further, the display system is composed of a video RAM (VRAM) or the like, and the storage information in the VRAM is displayed by connecting to a display as an output device. Further, a power supply unit for supplying power to the internal circuit of the computer system is provided.

The central processing unit CPU controls the operation timing of each memory by forming a signal for controlling each memory. Here, an example in which the invention is applied to an SDRAM as a main memory has been described, but the display system VRAM is a multiport VRA.
If it is M, it can be applied to the random access part of the VRAM.

[0038]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

That is, by combining a relative low voltage power supply and a high voltage power supply, and controlling the switching elements by the NMOS transistor and the PMOS transistor respectively connected thereto, first, the low voltage power supply is used to make the NMOS.
0V by inputting pre-boost signal to transistor
To the VCC-Vth level from the VCC-Vth level to the VCH level by inputting a boost signal to the PMOS transistor using a high voltage power supply.
You can boost up to the level, so 0V to V
It is possible to boost up to the CH level in two steps and output.

As a result, in the two-stage boost voltage circuit, by using the method of boosting in two stages by the combination of the low-voltage power supply and the high-voltage power supply, the high-voltage generator of It is possible to reduce current consumption.

Furthermore, when the two-stage boost voltage circuit is used in a semiconductor memory such as a synchronous DRAM, or when it is used in various systems such as a computer system, low power consumption can be achieved by reducing the current consumption of the high voltage generator. It will be possible.

[Brief description of the drawings]

FIG. 1 is a basic circuit diagram showing a two-stage boost voltage circuit according to an embodiment of the present invention.

FIG. 2 is a waveform diagram in the two-stage boost voltage circuit according to the present embodiment.

FIG. 3 is a circuit diagram showing an output buffer using a two-stage boost voltage circuit according to the present embodiment.

FIG. 4 is a waveform diagram in the output buffer according to the present embodiment.

FIG. 5 is a circuit diagram showing a high voltage generator for generating a high voltage power supply (always) in the present embodiment.

FIG. 6 is a circuit diagram showing a high voltage generator for generating a high voltage power supply (during operation) according to the present embodiment.

FIG. 7 is a configuration diagram showing a synchronous DRAM using a two-stage boost voltage circuit according to the present embodiment.

FIG. 8 is a configuration diagram showing a computer system using the synchronous DRAM according to the present embodiment.

[Explanation of symbols]

 VCC low-voltage power supply VCH high-voltage power supply QN1, 4 to 15, 21 to 29 NMOS transistor QN2, 3, 16 to 20 PMOS transistor NAND1 to 3 NAND gate NOR1, NOR gate IV1, IV3 to 13 Inverter D driver R1, 2 resistance C1-13 capacitor IN1 pre-boost signal IN2 boost signal OUT output signal DOjT output data signal DOCkB output enable signal I / Oj output data DOBPO output MOS gate control signal AD, BD, OSCH pulse signal VHTB test signal M-ARY memory array R- DCR row decoder C-DCR column decoder SA sense amplifier R-AB row address buffer RC refresh counter C-AB column address buffer C-AC color Address counter IB input buffer OB output buffer CONT & TG control circuit and Timing generating circuit PS power supply circuit

Claims (5)

[Claims] 1. A boost voltage circuit for boosting a voltage level from 0V to a high voltage, wherein a relative low voltage power supply and a high voltage power supply having different voltage levels are combined, and the low voltage power supply and the high voltage power supply are combined. By pre-boost from 0V to (low voltage-threshold voltage) level by controlling the switching elements respectively connected to the high voltage power source (low voltage-threshold voltage). Voltage) to high voltage level
A two-stage boost voltage circuit that boosts and outputs from V to a high voltage level in two stages. 2. The two-stage boost voltage circuit according to claim 1, wherein, as the switching element, an NMOS transistor having a drain connected to the low-voltage power supply and a PMOS transistor having a source connected to the high-voltage power supply. And a pre-boost signal is input to the gate of the NMOS transistor to pre-boost from 0V to a (low voltage-threshold voltage) level, and then a boost signal is input to the gate of the PMOS transistor (low voltage). Voltage-threshold voltage) level to a high voltage level to boost the source of the NMOS transistor and the PMO.
0V from the common connection node with the drain of the S transistor
To a high voltage level, a two-stage boosted voltage circuit that outputs a boosted signal. 3. A semiconductor memory using the two-stage boost voltage circuit according to claim 1, wherein the two-stage boost voltage circuit is used as an output buffer or the like, and a memory array including at least a plurality of memory cells, and the memory. A semiconductor memory having a decoder and an address buffer for selecting cells, an input / output buffer for reading and writing data, and the like. 4. The semiconductor memory according to claim 3, wherein
The semiconductor memory is a synchronous DRAM. 5. A computer system using the semiconductor memory according to claim 3 or 4, wherein the semiconductor memory is used as a memory device, and in addition to the memory device, at least a central processing unit and peripheral circuits thereof are provided. A computer system characterized by the above.