JPH09134315A - Service interruption compensating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely confirm the soundness of data stored in a data storing element when power supply is restored. SOLUTION: At the time of service interruption, power is supplied from a capacitor 7 to the data storing element 2 and a CPU 1 detects the service interruption and sends an OFF command S2 to a power supply control circuit 4 to turn off a transistor(TR) 3, and when power supply is restored, a voltage judging circuit 5 judges whether the voltage of the capacitor 7 is more than data storage limiting voltage or not. When the judged result is no, an abnormal signal S3 is sent, the CPU 1 executes processing for the abnormality, turns on the command S2 after the processing, turns on the TR 3 and supplies power to the element 2 and the capacitor 7. When the judged result is more than the data storage limit, the abnormal signal S3 is not sent and normal power supply is executed. Thereby the soundness of data in the element 2 can be confirmed in accordance with the existence of the abnormal signal S3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power failure compensating circuit using a chargeable backup power source such as a capacitor, and more particularly to a circuit for reliably detecting the soundness of held data.

[0002]

2. Description of the Related Art FIG. 8 shows, for example, JP-A-62-61139.
It is a circuit diagram which shows the conventional blackout compensation circuit shown by the publication. In the figure, 1 is the CPU of the device, 2 is a data holding element that holds the data of the device, 3 is a transistor that supplies power to the data holding element 2 and limits the current to other circuits during backup, 6 is a charging resistor, Reference numeral 7 is a power source backup capacitor, and 11 is a power source detection unit that monitors the power source, controls the transistor 3, and outputs a power source rising signal P to another circuit.

Reference numeral 12 denotes a charge control section for controlling the charging current to the capacitor 7 by the abnormal signal S3 from the voltage detection circuit 13, and 13 compares the terminal voltage S4 of the capacitor 7 with the data holding limit voltage of the data holding element 2, A voltage detection circuit that determines a voltage based on a power supply rise detection pulse P from the power supply detection unit 11;
A signal bus for reading / writing the contents of S3, S3 is an abnormal signal output from the voltage detection circuit 13, and is a signal indicating that the contents of the data holding element 2 may be destroyed.

FIG. 9 shows an internal circuit of the charge controller 12.
When the abnormal signal S3 is input, the capacitor 7 is discharged. S4 is the terminal voltage of the backup capacitor 7.

Next, the operation will be described. When the power supply of the device is normal, power is supplied to the data holding element 2 through the transistor 3 and the CPU can read / write data. Further, the capacitor 7 is charged via the resistor 6.

When the power supply voltage of the device drops and becomes lower than the capacitor voltage, a current is supplied from the capacitor 7 to the data holding element 2 and the device data at the time of power failure is held.
Transistor 3 turns off for the current other than the data holding element
And the capacitor current is supplied only to the data holding element.

When the power is restored in this state, the power supply detection unit 11
The voltage rise circuit 13 compares the terminal voltage S4 of the capacitor 7 with the data holding limit voltage by using the power rising detection pulse P from No. 3 as a trigger, and outputs an abnormal signal S3 if S4 is less than the data holding limit voltage. This abnormal signal S3 causes the transistor 1 in the charge controller 12 shown in FIG.
22 is turned on, the capacitor 7 is discharged, the power supply to the data holding element is cut off, and the data is not held.

Before starting the operation, the CPU 1 detects the state of the abnormal signal S3 from the port input and determines that the content of the data holding element 2 is not sound. In this way, it is possible to check the soundness of the data of the data storage element 2.

[0009]

In the conventional power failure compensating circuit, after the power is turned on, the voltage detecting circuit 13 compares the terminal voltage S4 of the capacitor 7 with the holding limit voltage of the data holding element to determine the charge control unit. 12 is controlled and the charging current to the capacitor 7 is controlled.
As shown in, the capacitor 7 is charged during the abnormality detection time t. Therefore, the terminal voltage S4 of the capacitor 7
Is slightly lower than the data holding limit voltage, as a result of being charged during this abnormality detection time t, the voltage becomes higher than the holding limit voltage and the abnormality signal S3 is not output. C in the data
There was a possibility that PU1 would operate abnormally.

Further, when the abnormal signal S3 is output as shown in FIG. 11, since the circuit configuration is such that the capacitor 7 is completely discharged, it takes a long time to charge the capacitor 7 at the time of power recovery, and a power failure occurs again. However, there is a problem that there is a high possibility that an abnormality will occur when the power is restored.

The present invention has been made in order to solve such a problem, and it is an object of the present invention to obtain a power failure compensating circuit for surely and inexpensively confirming the soundness of the data of the data holding element at the time of power recovery. Has an aim.

[0012]

[Means for Solving the Problems]

(1) A power failure compensating circuit according to the present invention includes a data storage element that stores data, a rechargeable backup power source that supplies power to the data storage element in the event of a power failure, the data storage element and the backup power source from the power source. Control means for controlling on / off of the power supply circuit to the device by an on / off command, a voltage determining means for determining whether the voltage of the backup power source is equal to or higher than a data storage limit voltage, and a determination result of the voltage determining means. And a control means for sending the ON / OFF command to the power supply control means according to the above, and when a power failure occurs, the backup power supply supplies power to the data storage element and the control means turns off to the power supply control means. When a command is sent to turn off the power supply circuit and the power is restored, the voltage determination means detects the backup power supply voltage. Data is not less than the storage limit voltage, the control means sends an abnormal signal if the determination result is no, and if the determination result is not less than the data storage limit, an ON command to the power supply control means. The power is supplied to turn on the power supply circuit to supply power to the data storage element and the backup power supply.

(2) Further, in the above (1), instead of the control means or the control means and the voltage determination means, a CPU having an analog / digital conversion function is provided for processing.

(3) Further, in the above (2), when the determination result is negative, the CPU performs the corresponding processing when the data holding element does not hold the data, and then sends the ON signal to the power supply control means. Then, the power supply circuit is turned on to supply power to the data storage element and the backup power supply.

(4) In any one of the above items (1) to (3), the power supply control means uses a semiconductor with a gate, and a gate is provided with a signal pull-down element.
An ON / OFF command is given to the gate to control ON / OFF of the power supply circuit.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 is a circuit diagram showing an embodiment of the present invention. In the figure, 1-3, 6, 7, S1, S
3, S4 are the same as those described in the conventional device. Reference numeral 4 is a power supply control circuit, which connects the transistor 3 to the CPU
It is controlled by the port output signal S2 of 1. Reference numeral 5 denotes a voltage determination circuit, which compares and determines the terminal voltage S4 of the capacitor 7 and the holding limit voltage of the data holding element. Further, FIG. 4 shows the potential of each part and the timing of signals.

In the power failure compensating circuit configured as shown in FIG. 1, when the CPU 1 detects the power failure of the apparatus, as shown in FIG.
PU1 is in a power failure state. The power supply control circuit 4 receives the port output signal S2 and turns off the transistor 3. At this time, a current is supplied from the capacitor 7 to the data holding element 2 to hold the data.

When the power source of the device is restored in this state, the transistor 3 remains in the OFF state and the capacitor 7
The charging current does not flow to the capacitor 7, and the voltage of the capacitor 7 becomes the same voltage as the supply voltage supplied to the data holding device 2 immediately before the power failure. At this time, the voltage determination circuit 5 compares and determines the terminal voltage S4 and the holding limit voltage to make the abnormal signal S3 significant as described below.

When the CPU 1 detects the power recovery of the device, as shown in FIG. 3, the CPU 1 detects the state of this abnormal signal S3 from the port input, and the port input S3 is at the "0" potential, that is, the voltage of the capacitor 7 is the holding limit. If higher than voltage,
It is determined that the content of the data holding element 2 is sound, and the held data normal processing is performed.

When the port input S4 is at "1" potential, that is, when the voltage of the capacitor 7 is lower than the holding limit voltage, it is judged that the contents of the data holding element 2 are not healthy, and the held data abnormality process is executed. After this processing, S2 is output from the port output.
The signal is set to "1", the transistor 3 is turned on, and the device start-up process is performed.

Thus, the capacitor 7 at the time of power recovery
By comparing this voltage with the holding limit voltage of the data holding element 2, it is possible to reliably detect the soundness of the data in the data holding element 2. Further, since the capacitor 7 is not forcibly discharged unlike the conventional example, the charging time at the time of charging the capacitor can be shortened.

Embodiment 2 FIG. FIG. 5 shows a means for comparing the terminal voltage of the capacitor 7 with the holding limit voltage at the time of power recovery, without using the voltage determination circuit 5 and by using the CPU 1 such as a one-chip microcomputer with an analog / digital conversion function.
Is used to directly input the capacitor terminal voltage S4 to the analog input terminal of the CPU 1. In this case, the voltage determination circuit 5 is not necessary, so that the circuit is simple and the cost can be reduced.

Embodiment 3 FIG. 6 shows a power failure compensating circuit according to a third embodiment of the present invention, and FIG. 7 shows an internal circuit of the power supply control circuit 4. In the figure, 1 to 7, S1, S
3 and S4 are the same as those described in the first embodiment. Reference numeral 8 is a signal pull-down element (resistive element), which is provided to stabilize the signal level of the CPU1 port output signal S2 in order to reliably implement the OFF state of the transistor 3 at the time of power recovery. A transistor 41 controls ON / OFF of the transistor 3. Reference numeral 42 is a protection resistor for the transistors 3 and 41.

In this way, when the transistor 41 in the power supply control circuit 4 controls the on / off of the transistor 3, the signal pull-down element 8 is provided and the internal circuit of the power supply control circuit 4 is operated during the unstable period of the power supply voltage. Can be reliably operated, and the soundness of the data in the data holding element 2 can be detected more reliably. The transistor 41 may be a semiconductor switch with a gate.

Embodiment 4 In the first embodiment, the processing of FIG. 2 and FIG. 3 is processed by the CPU 1, but the CPU 1 is
It is also possible to carry out only the held data normal processing and the held data abnormal processing, and to carry out other processing by separately providing a control circuit.

Embodiment 5 In the above embodiment, the capacitor is charged and used as the backup power source of the data holding element, but a rechargeable battery, that is, a storage battery (secondary battery) may be used instead of the capacitor. The storage battery can back up for a long time in case of power failure.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a power failure compensation circuit showing a first embodiment of the present invention.

FIG. 2 is a flowchart showing the processing of the CPU during a power failure according to the first embodiment of the present invention.

FIG. 3 is a flowchart showing the processing of the CPU at power recovery according to the first embodiment of the present invention.

FIG. 4 is a timing chart showing the operation of the first embodiment of the present invention.

FIG. 5 is a circuit diagram of a power failure compensation circuit showing a second embodiment of the present invention.

FIG. 6 is a circuit diagram of a power failure compensation circuit showing a third embodiment of the present invention.

FIG. 7 is a circuit diagram of a power supply control circuit according to a third embodiment of the present invention.

FIG. 8 is a circuit diagram of a conventional power failure compensation circuit.

FIG. 9 is a charge control unit used in a conventional power failure compensation circuit.

FIG. 10 is a timing chart of a conventional power failure compensation circuit.

FIG. 11 is a timing chart showing when an abnormality is detected in the conventional power failure compensation circuit.

[Explanation of symbols]

1 CPU, 2 data holding elements, 3 transistors,
4 power control circuit, 5 voltage determination circuit, 6 charging resistor,
7 capacitor, 8 signal pull-down element, 11 power supply detection unit, 12 conventional charge control unit, 13 voltage detection circuit, 41 transistor, 42 current limiting resistor, 121
Discharge limiting resistor, 122 discharge transistor, S1
Address / data bus, S2 port output signal, S3
Abnormal signal, S4 capacitor terminal voltage.

Claims (4)

[Claims] 1. A data storage element for storing data, a rechargeable backup power supply for supplying power to the data storage element in the event of a power failure, and a power supply circuit from the power supply to the data storage element and the backup power supply are turned on.・
A power supply control means for performing on / off control by an off command, a voltage determination means for determining whether or not the voltage of the backup power supply is equal to or higher than a data storage limit voltage, and a power supply control means according to the determination result of the voltage determination means Control means for transmitting the on / off command, and in case of a power failure, the backup power supply supplies power to the data storage element, and the control means transmits an off command to the power control means to supply the power. When the supply circuit is turned off and the power is restored, the voltage determination means determines whether the voltage of the backup power supply is equal to or higher than the data storage limit voltage, and the control means sends an abnormal signal if the determination result is negative. If the determination result is equal to or more than the data storage limit, an ON command is sent to the power supply control means to turn on the power supply circuit, and the data storage element and Power failure compensation circuit, characterized in that so as to supply power to the backup power supply. 2. The power failure compensation circuit according to claim 1,
A power failure compensating circuit characterized in that a CPU having an analog / digital conversion function is provided in place of the control means or the control means and the voltage determination means for processing. 3. The power failure compensating circuit according to claim 2, when the determination result is negative, the CPU performs a corresponding process when the data holding element does not hold the data, and then sends an ON signal to the power supply control means. A power failure compensating circuit characterized in that the power is supplied to turn on the power supply circuit to supply power to the data storage element and the backup power supply. 4. The power failure compensating circuit according to claim 1, wherein the power supply control means uses a semiconductor with a gate, a gate is provided with a signal pull-down element, and the gate has an on / off command. The power failure compensating circuit is characterized in that the power supply circuit is turned on and off.