JPH09130999A - Semiconductor integrated circuit device and sound powered rfid using this device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sound powered RFID which can prevent the supply of overpower when a communication distance with a host station becomes shorter and also can prevent a malfunction when the supplied power decreases because of an extended communication distance. SOLUTION: A voltage regulator 2 is provided for regulating a DC voltage generated by a voltage commutation circuit 1 so as not to make it exceed a given value. This can prevent a DC voltage used as an internal supply voltage from building up more than required even if a high AC voltage is generated because of the electromagnetic induction caused by a shortened communication distance. Also, a reset circuit 3 is provided for resetting CPUs and EEPROMs when the DC voltage above decreases below the given level. This makes it possible for the CPUs and EEPROMs to stop operating in the case where there is a risk that an extended communication distance causes the internal supply voltage to drop to a level at which the CPUs and EEPROMs cannot operate properly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a battery-less RFID (Radio Fr.
equency Indentification).

[0002]

2. Description of the Related Art In recent years, ICs incorporating ICs (integrated circuits)
Cards are being used in various fields. The conventional IC card has a built-in EEPROM (electrically erasable programmable ROM), stores data in the EEPROM, and executes a predetermined command using the data stored in the EEPROM. It was designed to do.

However, when such an IC card is used, the IC is loaded in a dedicated reading device such as a card reader.
It was very troublesome because I had to insert the card. Therefore, recently, by exchanging data with the host side using radio waves in the radio frequency band, a non-contact type IC card that can be easily operated without inserting the card one by one, that is, an RFID (Radio Freq
uency Indentification) or data carriers have been proposed.

In order to operate the RFID, it is necessary to supply power to its built-in IC. Therefore, in the past, an R that has a built-in IC drive battery has been used.
Many FIDs have been proposed. On the other hand, in recent years, a batteryless RFID has also been proposed in which electric power can be internally generated by using electric waves sent from the host side.

That is, such a batteryless RFI
In D, an AC voltage is generated by electromagnetic induction from a radio wave sent from the host side and is rectified into a DC voltage, so that the electric power required for driving the IC can be internally generated.

[0006] Conventionally, such a batteryless RFID
Is an EEPROM for storing various data, a logic circuit that operates in accordance with the data stored in the EEPROM, an RF unit for exchanging data with the host side using radio waves, and a signal sent from the host side. It was generally provided with a power unit that generates electric power using the received radio waves.

[0007]

In the conventional batteryless RFID, the magnitude of electromotive force due to electromagnetic induction changes in proportion to the square of the distance (communication distance) between the host and the RFID. Was becoming. For this reason, if the communication distance becomes too short, excessive power will be supplied to the IC,
There has been a problem that the IC is burdened more than necessary.

On the other hand, as the communication distance increases, the power supplied to the IC decreases, and the IC does not operate due to insufficient power. In this case, the conventional RFID has been designed so that the IC continues to operate up to the limit at which it cannot operate due to power shortage. However, this has a problem that the IC continues to operate even though the power required for the IC to operate normally is not sufficiently obtained, which may cause a malfunction.

The present invention has been made to solve such a problem, and prevents an excessive power from being supplied when the communication distance with the host becomes short, and the communication distance with the host. The purpose is to prevent malfunctions when the power supply becomes low due to a long time.

[0010]

The semiconductor integrated circuit device of the present invention is a voltage rectifying means for rectifying an AC signal generated from electromagnetic waves transmitted from the outside by electromagnetic induction and supplied to generate a DC internal power supply voltage. A semiconductor integrated circuit device having a built-in circuit is provided with voltage control means for controlling the magnitude of the DC voltage obtained by the voltage rectification means so as not to exceed a predetermined value.

Another feature of the present invention is that storage means for storing data, a CPU that operates in accordance with the storage contents of the storage means, and electromagnetic waves generated from an externally transmitted electromagnetic wave are supplied. A semiconductor integrated circuit device having a voltage rectifying means for rectifying the generated AC signal to generate a DC internal power supply voltage, wherein the DC voltage obtained by the voltage rectifying means is below a predetermined level,
It is characterized in that a reset means for setting the CPU and the storage means in a reset state is provided.

The batteryless RFID of the present invention is
A battery-less R that has a built-in semiconductor integrated circuit device that is designed to transmit and receive data to and from the outside using radio waves and to generate an internal power supply voltage from the received radio waves.
FID, voltage generating means for generating an AC voltage from electromagnetic waves transmitted from outside the RFID by electromagnetic induction, voltage rectifying means for rectifying the AC voltage generated by the voltage generating means into a DC voltage, and And a voltage control means for controlling the magnitude of the DC voltage obtained by the voltage rectifying means so as not to exceed a predetermined value.

Another feature of the present invention is that the storage means for storing the data, the CPU operating according to the storage contents of the storage means, and the outside of the data by radio waves under the control of the CPU. A batteryless RFID that has a built-in semiconductor integrated circuit device that performs power transmission / reception and that has a power / transmission / reception means that creates an internal power supply voltage from the received radio wave, the electromagnetic induction from the radio wave transmitted from the outside of the RFID. By means of a voltage generating means for generating an AC voltage, a voltage rectifying means for rectifying the AC voltage generated by the voltage generating means into a DC voltage, and the DC voltage obtained by the voltage rectifying means is below a predetermined level, It is characterized by comprising a CPU and a reset means for setting the storage means in a reset state.

Another feature of the present invention is that storage means for storing data, a CPU operating in accordance with the stored contents of the storage means, and data transmitted by radio waves between the outside under the control of the CPU. A batteryless RFID that has a built-in semiconductor integrated circuit device that performs power transmission / reception and that has a power / transmission / reception means that creates an internal power supply voltage from the received radio wave, the electromagnetic induction from the radio wave transmitted from the outside of the RFID. A voltage generating means for generating an AC voltage by the voltage generating means, a voltage rectifying means for rectifying the AC voltage generated by the voltage generating means into a DC voltage,
Voltage control means for controlling the magnitude of the DC voltage obtained by the voltage rectifying means so as not to exceed a predetermined value; and the CPU and the memory when the DC voltage obtained by the voltage rectifying means is below a predetermined level. Reset means for resetting the means.

Another feature of the present invention is that in the reset means, when the DC voltage obtained by the voltage rectifying means gradually increases, the DC voltage is higher than a first threshold value. The above CPU when it grows
And when the direct current voltage obtained by the voltage rectifying means gradually decreases while the reset state of the storage means is released, and when the direct current voltage becomes smaller than a second threshold value, the storage The CPU is reset when the means is in a reset state and the DC voltage becomes smaller than a third threshold value which is smaller than the second threshold value.
Is characterized by being reset.

Another feature of the present invention is that the second threshold value is smaller than the first threshold value.

Another feature of the present invention is that it uses radio waves to transmit and receive data to and from the outside, and
Battery-free RFI incorporating a semiconductor integrated circuit device designed to generate an internal power supply voltage from received radio waves
D, voltage generating means for generating an AC voltage by electromagnetic induction from a radio wave transmitted from the outside of the RFID,
The voltage rectifying means for rectifying the AC voltage generated by the voltage generating means into a DC voltage, the storage means for storing the DC power obtained by the voltage rectifying means, and the DC voltage obtained by the voltage rectifying means are higher than a predetermined level. And a control means for controlling the DC power stored in the power storage means to be used as the internal power supply when the power becomes small.

Since the present invention comprises the above technical means, even if the voltage level of the AC signal generated and supplied by electromagnetic induction from the electric wave transmitted from the outside of the semiconductor integrated circuit device becomes very large, the internal power supply voltage is increased. The DC voltage used as is controlled so that it does not become larger than necessary. For example, when the semiconductor integrated circuit device of the present invention is applied to a battery-less RFID, the communication distance between the RFID and the communication partner device becomes short, and even if the AC voltage generated by electromagnetic induction becomes very large, The DC voltage used as the internal power supply voltage is controlled so as not to be higher than necessary.

According to another feature of the present invention, the voltage level of the AC signal generated and supplied by electromagnetic induction from a radio wave transmitted from the outside of the semiconductor integrated circuit device is reduced, and the generated internal power supply is generated. When the voltage is reduced to a level at which the CPU and the storage means may not operate normally, the CPU and the storage means do not continue to operate. For example, when the semiconductor integrated circuit device of the present invention is applied to a batteryless RFID,
As the communication distance between the RFID and the communication partner device becomes longer, the magnitude of the DC voltage generated by the voltage rectifying means becomes CP.
When the U and the storage means are reduced to a level where they may not operate normally, the CPU and the storage means do not continue to operate.

According to another feature of the present invention, when the reset means resets the CPU and the storage means, the storage means is first reset to inhibit the writing of data, and then the CPU As a result of resetting, it is possible to prevent the inconvenience that wrong data is written in the storage means due to a malfunction at the time of resetting.

According to another characteristic of the present invention, C
A second threshold value in which the storage means is reset to a level higher than a first threshold value in which the reset states of the PU and the storage means are released.
Since the threshold value of is smaller than the first threshold value, the storage means is not reset unless the internal power supply voltage generated by the voltage rectifying means is smaller than the first threshold value. The storage means is not easily reset when the internal power supply voltage falls below the first threshold value due to an unintentional fluctuation of the voltage level.

According to another feature of the present invention, the power is stored while the internal power supply voltage sufficient for the RFID of the present invention to operate normally is obtained, and the magnitude of the internal power supply voltage is increased. When the built-in IC is reduced to a level where it may not operate normally, the stored power is used as internal power supply power, and the internal power supply power that enables normal operation is secured for a longer time. Will be done.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a power / RF unit that best expresses the characteristics of the battery-less RFID according to the present embodiment, and FIG. 2 is a battery-free system using the power / RF unit shown in FIG. 3 is a block diagram showing the configuration of the RFID of FIG.

First, the overall configuration and operation of the batteryless RFID according to the present embodiment will be described with reference to FIG. In FIG. 2, 21 is a CPU, 22 is a ROM, and 23.
Is an EEPROM, and the ROM 22 and the EEPROM 23
The execution program of the CPU 21 and various data are stored in the.

The storage capacity of the ROM 22 is, for example, 10
24 words × 12 bits, and the EEPROM 23
The storage capacity of is, for example, 2048 words × 12 bits. The ROM 22 and the EEPROM 23 are located in the same memory space. Among them, EEPRO
In the memory space of M23, the execution program of the CPU 21 and various data can be rewritten.

That is, the CPU 21 has the ROM 22 and the E
Various instructions are executed according to the contents stored in the EPROM 23, and the instructions themselves can be freely rewritten using the EEPROM 23. That is, the CPU 21
The execution program of can be freely rewritten from outside the RFID.

As described above, in this embodiment, the CPU 21 is used instead of using the logic circuit in the conventional batteryless RFID. By incorporating the CPU 21, not only can a command execution protocol be freely configured, but also radio waves transmitted and received by a large number of RFIDs can be simultaneously recognized.

Further, in the logic circuit, the next operation cannot be performed until one operation is completed.
U21 can perform a plurality of operations at the same time. For example, while writing data to the EEPROM 23, the RO
The data stored in M22 can be read and processed. Therefore, the processing time as a whole can be shortened.

Data is exchanged between the CPU 21 and the ROM 22, and between the CPU 21 and the EEPROM 23 via an address bus 25 and a data bus 26, respectively. The bus widths of the address bus 25 and the data bus 26 are both 12 bits.
An ALU (not shown) provided in the CPU 21
(Arithmetic and logic unit) and 1 word of register is 12
Is a bit.

As described above, by setting the bus width and one word of the ALU and the register to 12 bits, the CPU
It is possible to describe the operation code and the operand that compose one instruction 21 in one word. Also, the immediate address can be described in one word.

Reference numeral 24 is a power / RF section. The power / RF unit 24 uses an electric wave (for example, a high-frequency electric wave such as a radio frequency band) to transmit / receive various data to / from a device on the host side, not shown, It also serves as a power unit that uses the received radio waves to generate internal power.

That is, among the several terminals provided in the power / RF section 24, S1 and S2 are terminals for transmitting and receiving radio waves, and these two terminals S for transmitting and receiving radio waves.
Data is transmitted and received by radio waves between the RFID of this embodiment and a host side (not shown) via S1 and S2.

A resonance circuit composed of a tuning coil 30 and a capacitor 31 is connected to the radio wave transmitting / receiving terminals S1 and S2. Then, an AC voltage is induced in the tuning coil 30 in response to a change in the magnetic field generated by an electric wave transmitted from an external host to the resonance circuit. The power / RF unit 24 inputs the AC voltage thus induced through the radio wave transmitting / receiving terminals S1 and S2,
The internal power supply power is obtained by rectifying it into a DC voltage.

The DC voltage generated by the power / RF unit 24 is output via the internal voltage terminal CVdd and the internal ground terminal CGND. The internal voltage terminal CVd
A smoothing capacitor 32 is connected to d and the internal ground terminal CGND to stabilize the output DC voltage.

The power / RF unit 24 is the I / O bus 2
CPU 21, timer 28 and serial I via
Connected to the / O port 29. In the present embodiment, by incorporating the timer 31 in this way, it is possible to realize the reset operation by software.
The timer 28 is, for example, a 24-bit timer.

Three input / output terminals I / O ₀ , I / O ₁ and I / O ₂ are connected to the serial I / O port 29, and these input / output terminals I / O ₀ and I / O ₀ , I / O ₁ ,
It is possible to connect an external load via I / O ₂ . As the external load, for example, an LED (not shown) can be used.

When the LEDs are connected in this way, the LEDs can be turned on when the RFID of the present embodiment and the host approach and enter the range where communication is possible. Can be made visible to the user at a glance. The power / RF unit 24 also creates a power supply for driving the LED which is the external load.
It is.

The semiconductor integrated circuit device according to the present embodiment includes the CPU 21, ROM 22, EEPROM 23, power / RF section 24, address bus 25, data bus 26, and
The I / O bus 27, the timer 28, and the serial I / O port 29 are integrated into one chip.

Next, the power / RF described above with reference to FIG.
The detailed configuration and operation of the unit 24 will be described. FIG.
As shown in FIG. 3, the power / RF unit 24 of this embodiment includes a voltage rectifier circuit 1, a voltage regulator 2, a reset circuit 3, an FSK (frequency shift keying) circuit 4, and a PSK (phase shift keying). The circuit 5 and the clock circuit 6 are provided.

Of these configurations, the voltage rectifier circuit 1, the voltage regulator 2 and the reset circuit 3 constitute the power section of the present embodiment described above. In addition, the FSK circuit 4, the PSK circuit 5, and the clock circuit 6 constitute the RF unit of this embodiment described above.

First, the power section will be described.
The voltage rectifier circuit 1 has two radio wave transmitting / receiving terminals S1 and S2 connected to its input side, and an internal voltage terminal CVdd and an internal ground terminal CGND connected to its output side.

The voltage rectifying circuit 1 controls the output voltage to be substantially constant by rectifying a single-phase AC voltage input from the two radio wave transmitting / receiving terminals S1 and S2 into a DC voltage. is there. In this voltage rectifier circuit 1,
It is preferable to use a full-wave rectifier circuit that converts the bidirectional components of AC (all for one cycle) into DC voltage.

FIG. 3 is a diagram showing a concrete configuration example of the voltage rectifier circuit 1. As shown in FIG. 3, the voltage rectifier circuit 1 of this embodiment has two radio wave transmitting / receiving terminals S1 and S2.
The four rectifying elements D1 to D4 are connected in a bridge configuration between the two. The DC voltage generated by the voltage rectifier circuit 1 is output via the internal voltage terminal CVdd and the internal ground terminal CGND.

The voltage regulator 2 is connected in parallel to the output side of the voltage rectifier circuit 1. That is, one input terminal of the voltage regulator 2 is connected to the internal voltage terminal CVdd, and the other input terminal is connected to the internal ground terminal CGND. As a result, the DC voltage generated by the voltage rectifier circuit 1 is supplied to the voltage regulator 2.

The voltage regulator 2 controls the DC voltage generated by the voltage rectifier circuit 1 so as to keep it below a certain level. That is, it is determined whether or not the DC voltage supplied from the voltage rectifier circuit 1 exceeds a predetermined threshold value (for example, 3V), and if it exceeds the threshold value, a limit operation is performed to thereby prevent the radio wave from the outside The control is performed so that the magnitude of the internal power supply voltage generated by using does not exceed the predetermined threshold value.

By providing such a voltage regulator 2, the communication distance between the RFID of this embodiment and a host (not shown) is shortened, and the AC voltage induced in the tuning coil 30 of FIG. 2 is greatly increased. Also, the magnitude of the DC voltage used as the internal power supply voltage can be prevented from becoming unnecessarily large. This enables RFID
When the host and the host approach each other, excessive power is prevented from being supplied to the built-in IC, and the load on the IC can be reduced.

Further, the reset circuit 3 is connected in parallel to the output side of the voltage rectifier circuit 1 as in the voltage regulator 2. That is, one input terminal of the reset circuit 3 is connected to the internal voltage terminal CVdd, and the other input terminal is connected to the internal ground terminal CGND. As a result, the DC voltage generated by the voltage rectifier circuit 1 (the voltage when the voltage regulator 2 is performing the limit operation) is supplied to the reset circuit 3.

The reset circuit 3 controls to reset the operations of the CPU 21 and the EEPROM 23 when the level of the DC voltage supplied from the voltage rectifier circuit 1 is smaller than a predetermined threshold value. Such control is performed by controlling the levels (“H” level or “L” level) of the two reset signals RST ₁ and RST ₂ . The predetermined threshold value used in the reset circuit 3 is set to the CPU 21 and the EEPROM.
23 is set to a voltage level sufficient for normal operation.

By providing such a reset circuit 3, the communication distance between the RFID of this embodiment and the host (not shown) becomes long, and the magnitude of the DC voltage generated by the voltage rectifier circuit 1 becomes extremely small. When the CPU 21
Also, it is possible to prevent the malfunction of the EEPROM 23 due to the continuous operation of the EEPROM 23.

By the way, it is possible that the RFID is in the process of communicating with the host when the reset circuit 3 resets the RFID. In this case, if all the built-in ICs are reset at the same time, E
It is possible that the contents of the EPROM 23 will be rewritten.

As is well known, the EEPROM 23 is a non-volatile memory, and its stored contents are not lost even when the power is turned off. Therefore, if the contents of the EEPROM 23 are rewritten due to an erroneous operation, the erroneous contents are left as they are, which is extremely inconvenient.

Therefore, in the present embodiment, the reset circuit 3
The above-mentioned inconvenience is prevented by operating the following. That is, in the present embodiment, as shown in FIG. 4, three types of reset voltages V _rst1 , V _rst2 , and V _{rst3 are used.}
Is used to control the reset operation of the CPU 21 and the EEPROM 23.

In the graph shown in FIG. 4, the vertical axis represents voltage level and the horizontal axis represents time. This graph is
The power supply voltage internally generated increases as the communication distance between the RFID of this embodiment and the host (not shown) gradually decreases, and then the power supply internally generated by the communication distance gradually increases. It shows how the voltage decreases.

In FIG. 4, the internal power supply voltage VDD
In the process in which (the voltage appearing at the internal voltage terminal CVdd in FIG. 1) gradually increases, the first and second reset signals RST ₁ are supplied until the voltage level reaches the first reset voltage V _rst1. , RST ₂ are both at “H” level (the same voltage as the internal power supply voltage VDD), and both the CPU 21 and the EEPROM 23 are in the reset state.

When the voltage level of the internal power supply voltage VDD reaches the first reset voltage V _rst1 , both the first and second reset signals RST ₁ and RST ₂ are at "L" level (the same as the internal ground voltage VGND). Voltage), and CP
Both U21 and EEPROM 23 are released from the reset state. The first reset voltage V _rst1 is, for example, 2.7V.

Next, when the level of the internal power supply voltage VDD further rises to reach 3V, the voltage regulator 2
With the control of, the voltage can be suppressed so that it does not rise further. After that, when the internal power supply voltage VDD gradually decreases and the voltage level decreases to the second reset voltage V _rst2 , the second reset signal RST _{2 first} becomes “H” level, and the EEPROM 23 is reset. It As a result, the writing of data to the EEPROM 23 is prohibited.

This second reset voltage V _rst2 is a value slightly smaller than the value of the first reset voltage V _rst1 ,
For example, it is set to 2.3V. Thus, by _setting the second reset voltage V _rst2 to a value smaller than the value of the first reset voltage V _rst1 , the following merits are obtained.

That is, in FIG. 4, for simplification of the drawing, when the communication distance between the RFID of this embodiment and the host (not shown) is sufficiently short, the level of the internal power supply voltage VDD generated internally is always constant. Although shown as being held at 3V, the voltage level is actually slightly fluctuating. Then, the fluctuating voltage level may fall below 2.7V which is the first reset voltage V _rst1 .

In this case, if the second reset voltage V _rst2 is set to 2.7 V, which is the same value as the first reset voltage V _rst1 , the _{EEPROM 23} will be set when the fluctuating voltage level falls below 2.7 V. It was reset even though it was not intended. Therefore, if the second reset voltage V _rst2 is set to 2.3 V, which is a value smaller than the first reset voltage V _rst1 , as in this embodiment, the _{EEPROM 23} is not easily reset due to the fluctuating voltage level. Can be

Next, when the internal power supply voltage VDD further decreases and the voltage level decreases to the third reset voltage _Vrst3 , the first reset signal RST ₁ next becomes "H" level and the CPU 21 is reset. . The third reset voltage _Vrst3 is set to 2.0V, for example.

As described above, in this embodiment, V
The relationship of _rst1 > V _rst2 > V _rst3 is maintained, and _CPU2
When 1 is reset, the EEPROM 23 has already been reset and writing of data is prohibited. As a result, it is possible to eliminate the inconvenience that incorrect data is written in the EEPROM 23 due to the malfunction of the CPU 21 at the time of reset.

FIG. 5 is a diagram showing a specific configuration example of the reset circuit 3 for realizing the above operation. The configuration and operation of the reset circuit 3 described with reference to FIG. 4 will be described below with reference to FIG.

In FIG. 5, MP ₁₁ , MP ₁₂ , MP ₁₃ ,
MP ₁₄ is the first to fourth P-channel enhancement type transistors, MN ₁₁ and MN ₁₂ are the first and second N-channel enhancement type transistors, MD ₁₁ is the N-channel depletion type transistor, IV ₁₁ and I
V ₁₂ , IV ₁₃ , and IV ₁₄ are first to fourth inverter circuits.

The gate terminal of the first P-channel enhancement type transistor MP ₁₁ is connected to the internal ground terminal CGND, and the source terminal is connected to the internal voltage terminal CVdd. The drain terminal is the second
P-channel enhancement type transistor MP ₁₂
Of the N-channel depletion type transistor MD _{11 and} the drain terminal and the gate terminal of the N-channel depletion type transistor MD ₁₁ , and the gate terminals of the first and second N-channel enhancement type transistors MN ₁₁ and MN ₁₂ .
Hereinafter, the voltage applied to this connection point will be referred to as a first voltage V ₁ .

The source terminal of the second P-channel enhancement type transistor MP ₁₂ is the internal voltage terminal CV.
dd and the gate terminal is the first inverter circuit I
It is connected to the input terminal of V ₁₁ . The source terminal of the N-channel depletion type transistor MD ₁₁ is connected to the internal ground terminal CGND.

The gate terminal of the third P-channel enhancement type transistor MP ₁₃ is connected to the internal ground terminal CGND and the source terminal thereof is connected to the internal voltage terminal CVdd. The drain terminal is the first N-channel enhancement type transistor MN.
_{11 is connected to} the drain terminal, the gate terminal of the second P-channel enhancement type transistor MP ₁₂ , and the input terminal of the first inverter circuit IV ₁₁ . Hereinafter, the voltage applied to this connection point will be referred to as the second voltage V ₂ .

The source terminal which is the remaining terminal of the first N-channel enhancement type transistor MN ₁₁ is connected to the internal ground terminal CGND. Further, the output terminal of the first inverter circuit IV ₁₁ is connected to the input terminal of the second inverter circuit IV _12, the first reset signal RST ₁ from the output terminal of the second inverter circuit IV ₁₂ is outputted It has become so.

The gate terminal of the fourth P-channel enhancement type transistor MP ₁₄ is connected to the internal ground terminal CGND, and the source terminal thereof is connected to the internal voltage terminal CVdd. The drain terminal is the second N-channel enhancement type transistor MN.
It is connected to the drain terminal of ₁₂ and the input terminal of the third inverter circuit IV ₁₃ . Hereinafter, the voltage applied to this connection point will be referred to as the third voltage V ₃ .

The source terminal, which is the remaining terminal of the second N-channel enhancement type transistor MN ₁₂ , is connected to the internal ground terminal CGND. Further, the output terminal of the third inverter circuit IV ₁₃ is connected to the input terminal of the fourth inverter circuit IV _14, the reset signal RST ₂ from the output terminal of the second of the fourth inverter circuit IV ₁₄ is outputted It has become so.

In such a structure, the above first to fourth
P-channel enhancement type transistor M
The threshold voltage of P ₁₁ , MP ₁₂ , MP ₁₃ , and MP _{14 and} the threshold voltage of the N-channel depletion type transistor MD ₁₁ are set to −0.6V, respectively.
The threshold voltages of the first and second N-channel enhancement type transistors MN ₁₁ and MN ₁₂ are set to + 0.6V, respectively.

The internal power supply voltage VDD generated by the voltage rectifier circuit 1 is supplied to the internal voltage terminal CVdd, and the internal ground voltage VGND is supplied to the internal ground terminal CGND. Also, the first reset signal R
The CPU 21 is reset when ST ₁ goes to "H" level, and the EEPROM 23 is reset when the second reset signal RST ₂ goes to "H" level.

The operation will be described below. First, the operation when the internal power supply voltage VDD gradually rises from the internal ground voltage VGND as shown in FIG. 4 will be described.

[0073] First, the internal power supply voltage VDD is higher than the threshold voltage of the first P-channel enhancement transistor MP _11, the first P-channel enhancement type transistor MP ₁₁ is turned on. Here, since the threshold voltage of the first P-channel enhancement type transistor MP ₁₁ is −0.6 V, the first P-channel enhancement type transistor MP ₁₁ is used.
₁₁ is always on regardless of the value of the internal power supply voltage VDD.

Further, since the threshold voltage of the third and fourth P-channel enhancement type transistors MP ₁₃ and MP ₁₄ is also −0.6V, each of these transistors MP ₁₃
Similarly to the first P-channel enhancement type transistor MP ₁₁ , ₁₃ and MP ₁₄ have the same internal power supply voltage VD.
It is always on regardless of the value of D.

The first P-channel enhancement type transistor MP ₁₁ is turned on, and the internal power supply voltage VD
When D becomes higher, the first voltage V ₁ becomes higher than the internal ground voltage VGND. At this time, the first voltage V ₁ is determined by the ratio of the ON resistance values of the first P-channel enhancement type transistor MP ₁₁ and the N-channel depletion type transistor MD ₁₁ .

The first voltage V ₁ is applied to the first and second N-channel enhancement type transistors MN.
_{When the} voltage becomes higher than the threshold voltage (+0.6 V) of ₁₁ , MN ₁₂ , the first and second N-channel enhancement type transistors MN ₁₁ , MN ₁₂ are turned on. At this time, the third and fourth P-channel enhancement type transistors MP ₁₃ and MP ₁₄ are already in the ON state.

Therefore, the second voltage V ₂ is the same as that of the third P-channel enhancement type transistor MP ₁₃
N-channel enhancement type transistor MN ₁₁
And the on-resistance value of The third voltage V ₃ is determined by the ratio of the on resistance values of the fourth P-channel enhancement type transistor MP ₁₄ and the second N-channel enhancement type transistor MN ₁₂ .

That is, before the first and second N-channel enhancement type transistors MN ₁₁ and MN ₁₂ are turned on, the second voltage V ₂ and the third voltage V ₃ are applied.
Are both equal to the internal power supply voltage VDD. On the other hand, as the internal power supply voltage VDD rises, the first voltage V ₁ rises and the first and second N-channel enhancement type transistors MN ₁₁ and MN ₁₂ are turned on. Voltage V ₂ and the third voltage V ₃ start falling from the internal power supply voltage VDD.

In this embodiment, the ON resistance of the first N-channel enhancement type transistor MN ₁₁ is the second
N-channel enhancement type transistor MN ₁₂
Each transistor MN to be smaller than the on resistance of
₁₁ and MN ₁₂ are set. By doing so, even if the first voltage V ₁ is the same, the second voltage V ₂ is lower than the third voltage V ₃ .

In this way, the second voltage V ₂ and the third voltage V ₂
Of the voltage V ₃ gradually decreases from the internal power supply voltage VDD, the second of the voltage V ₂ First (internal power supply voltage VDD + the second
P-channel enhancement type transistor MP ₁₂
Second threshold voltage), the second P-channel enhancement type transistor MP ₁₂ is turned on. This causes the first voltage V ₁ to rise rapidly.

[0081] Accordingly, when the second voltage V ₂ is below the logic inversion voltage of the first inverter circuit IV _11, the first inverter circuit IV ₁₁ and the second inverter circuit IV ₁₂ of the second The voltage of the first reset signal RST ₁ that is logically inverted from the voltage V ₂ and output is changed from the internal power supply voltage VDD (that is, “H” level) to the internal ground voltage VGND (that is, “L” level).

As the first P-channel enhancement type transistor MP ₁₂ is turned on to rapidly increase the first voltage V ₁ , the third voltage V ₃ also decreases and the third voltage V ₃ decreases. It falls below the logic inversion voltage by the inverter circuit IV ₁₃ . Then, the voltage of the second reset signal RST ₂ that is the logical inversion of the third voltage V ₃ output by the third inverter circuit IV ₁₃ and the fourth inverter circuit IV ₁₄ is also changed from the internal power supply voltage VDD to the internal ground. Transition to voltage VGND.

As described above, the first voltage V ₁ rapidly rises as the second P-channel enhancement type transistor MP ₁₂ is turned on, so that the first reset signal RST ₁ becomes “H”. The value of the internal power supply voltage VDD at the time of transition from the “level” to the “L” level and the value of the internal power supply voltage VDD at the time of the transition of the second reset signal RST ₂ from the “H” level to the “L” level , Become almost equal. The internal power supply voltage VDD at this time corresponds to the first reset voltage V _rst1 (for example, 2.7 V).

Next, when the internal power supply voltage VDD is saturated voltage (+
The operation when the voltage gradually decreases from (3 V) to the internal ground voltage VGND will be described. First voltage V
_{The value of 1} starts to drop as the internal power supply voltage VDD drops. At this time, the first voltage V ₁ is 1 / {(1 / ON resistance of the first P-channel enhancement transistor MP ₁₁ ) + (1 / ON resistance of the second P-channel enhancement transistor MP ₁₂ )} And the on-resistance value of the N-channel depletion type transistor MD ₁₁ are determined.

As the first voltage V ₁ drops, the second voltage V ₂ and the third voltage V ₃ start to rise. At this time, since the ON resistance value of the first N-channel enhancement type transistor MN ₁₁ is smaller than the ON resistance value of the second N-channel enhancement type transistor MN ₁₂ , the third voltage V ₃ is higher than the second voltage V ₂ . It's getting higher.

Therefore, as the internal power supply voltage VDD decreases, the third voltage V ₃ first becomes higher than the logic inversion voltage of the third inverter circuit IV ₁₃ . Thereby, the second
Of the reset signal RST ₂ of the internal ground voltage V
Internal power supply voltage VDD from GND (“L” level)
("H" level). The internal power supply voltage VDD at this time is the second reset voltage V _rst2 (for example, 2.3).
V).

When the internal power supply voltage VDD further decreases, the second voltage V _{2 then} changes to the first inverter circuit IV ₁₁
Higher than the logic inversion voltage of the first reset signal R
The voltage of ST ₁ changes from the internal ground voltage VGND (“L” level) to the internal power supply voltage VDD (“H” level). The internal power supply voltage VDD at this time corresponds to the third reset voltage V _rst3 (for example, 2.0 V).

As described above, in this embodiment, when the internal power supply voltage VDD decreases, the EEPROM ₂₃ is reset when the internal power supply voltage VDD first decreases to the second reset voltage V _rst2 . Further, the CPU 21 is reset when the internal power supply voltage VDD decreases to the third reset voltage _Vrst3 .
In other words, be sure to set EEPRO before resetting the CPU 21.
M23 is reset to prohibit writing of data.

By doing so, the erroneous data is EE due to the malfunction of the CPU 21 at the time of reset.
The inconvenience of being written in the PROM 23 can be eliminated, and the CPU 21 and the EEPROM 23 can always operate normally.

Next, the RF section shown in FIG. 1 will be described. FSK circuit 4 and PSK circuit 5 forming the RF unit
Are the above-mentioned two radio wave transmitting / receiving terminals S1 and S, respectively.
2 are connected. Here, the FSK circuit 4 is used for data reception, and the PSK circuit 5 is used for data transmission.

That is, the FSK circuit 4 transmits information by shifting the frequency. For example, a terminal S for transmitting and receiving radio waves
1 when the data value received in S1, S2 is "1"
A sine wave of 25 KHz is sent to the transmission line, and when the received data value is "0", a sine wave of 117.65 KHz is sent to the transmission line.

Further, the PSK circuit 5 transmits information by shifting the phase. For example, the carrier frequency is 62.5KH
Quadrature phase modulation of z can be used. in this case,
Since there are four types of signals, 0 °, 90 °, 180 °, and 270 ° in phase, 2-bit transmission is performed for each signal.

Further, the clock circuit 6 generates a clock pulse which serves as a reference for detecting signals of different frequencies in the FSK circuit 4. For example, the FS
The K circuit 4 detects the above 125 KHz signal and 117.65 KHz signal by dividing the clock pulse supplied from the clock circuit 6 with different division ratios according to the data values "1" and "0". To do.

As described above, in the present embodiment, the transmission and reception of radio waves are divided into the FSK system (reception) and the PSK system (transmission). Further, in the present embodiment, unlike the conventional logic circuit, the CPU 21 is incorporated. Therefore, the CPU 21 transmits the transmission radio wave and the reception radio wave.
Can be recognized, and data can be transmitted and received at the same time.

In the above embodiment, when the communication distance between the RFID and the host is increased and the internal power supply voltage VDD becomes lower than a predetermined level, the CPU 21 and the EE are not affected.
By resetting the PROM 23, the CPU 21 and the EEPROM 23 can be prevented from malfunctioning. On the other hand, it is possible to prevent malfunction by incorporating a storage battery.

That is, the CPU 21 and the EEPROM
The storage battery is charged while the internal power supply voltage VDD sufficient for normal operation of the battery 23 is obtained. And
The communication distance between the RFID and the host is long and the CPU 21 or E
When the internal power supply voltage VDD becomes small to the extent that the EPROM 23 may malfunction, the electric power stored in the storage battery is stored in the CPU 21 and EEPRO.
It is used to operate M23.

In this way, the CPU 21 and the EE
Power sufficient for the normal operation of the PROM 23 can be secured for a longer period of time, and the CPU 21 and EEPRO
It is possible to further reduce the risk that the M23 will malfunction. Such a thing can be realized, for example, by using the smoothing capacitor 32 shown in FIG. 2 as a storage battery.

However, even if the normal operation time can be extended by using the storage battery, it is possible that the CPU 21 and the EEPROM 23 malfunction when the storage battery runs out. However, such an erroneous operation can be avoided by using the storage battery and the above-described reset operation (correctly, operation similar to the reset operation) together.

That is, the CPU 21 and the EEPROM
The storage battery is charged while the internal power supply voltage VDD sufficient for normal operation of the battery 23 is obtained. And RF
The communication distance between the ID and the host is long, and the internal power supply voltage VDD
Is smaller than a predetermined value (a value sufficient for the CPU 21 and the EEPROM 23 to operate normally), the CPU 2
1 and the EEPROM 23 issue an instruction to end the process currently being executed.

When this termination command is issued, the CPU 21 and the EEPROM 23 operate to terminate the processing currently being performed by the CPU 21 and the EEPROM 23 using the electric power stored in the storage battery. By doing so, the power supply is less likely to be cut off during the processing of the CPU 21 and the EEPROM 23, and the risk of malfunction can be further reduced.

[0101]

As described above, the present invention is provided with the voltage control means for controlling the magnitude of the internal power supply voltage generated by the voltage rectification means so as not to exceed a predetermined value. Even if the voltage level of the AC signal generated by electromagnetic induction from the radio waves transmitted from the outside and supplied becomes extremely high, the magnitude of the DC voltage used as the internal power supply voltage should not be higher than necessary. You can

For example, the semiconductor integrated circuit device of the present invention is
When applied to a battery-less RFID that can send and receive data to and from the outside using radio waves and can generate internal power supply power from the received radio waves by electromagnetic induction, the RFID and the communication partner device Even if the communication distance becomes short and the AC voltage generated by electromagnetic induction becomes very large, the size of the DC voltage used as the internal power supply voltage can be prevented from becoming unnecessarily large. Prevents power from being supplied and R
The burden on the FID can be reduced.

Further, according to another feature of the present invention, the reset means is provided for setting the CPU and the storage means in the reset state when the voltage of the internal power supply generated by the voltage rectifying means is below a predetermined level. The voltage level of the AC signal generated and supplied by electromagnetic induction from the electric wave transmitted from the outside of the semiconductor integrated circuit device becomes small, and the generated internal power supply voltage may cause the CPU and the storage unit to not operate normally. It is possible to prevent the CPU and the storage means from continuing to operate even when the level is reduced to a certain level.

For example, when the semiconductor integrated circuit device of the present invention is applied to a battery-less RFID, the communication distance between the RFID and the communication partner device becomes long, and the CPU and storage means may not operate normally. When the internally generated power supply voltage is reduced to a certain level, the CPU and the storage means can be prevented from continuing to operate, and the inconvenience that the CPU and the EEPROM malfunction can be reduced.

Further, according to another feature of the present invention, when the voltage of the DC power obtained by the voltage rectifying means gradually decreases, the DC voltage becomes smaller than the second threshold value. Sometimes the storage means is reset,
Since the CPU is set to the reset state when the DC voltage becomes smaller than the third threshold value which is smaller than the second threshold value, the memory means is first reset to write the data. The CPU can be reset after the prohibition.
It is possible to eliminate the inconvenience that erroneous data is written in the storage means due to the erroneous operation.

According to another feature of the present invention, when the DC voltage obtained by the voltage rectifying means gradually increases, the first voltage becomes a reference voltage for releasing the reset state of the CPU and the storage means. Since the second threshold value is set smaller than the threshold value, the internal power supply voltage generated by the voltage rectifying means is stored even if it is smaller than the first threshold value but not smaller than the second threshold value. The means may not be reset and the storage means may not be easily reset if the voltage of the internal power supply falls below the first threshold value due to an unintended voltage level variation, whereby It is possible to stabilize the operation.

Further, according to another feature of the present invention, the storage means for storing the DC power generated from the induced AC voltage by the voltage rectification means and the DC voltage obtained by the voltage rectification means are smaller than a predetermined level. Since the control means for controlling the electric power stored in the power storage means to be used as an internal power source when it becomes, it is possible to secure an internally generated power source voltage capable of normal operation for a longer time, It is possible to reduce the risk that the RFID may malfunction due to insufficient power.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a power / RF unit, which is an embodiment of the present invention and best expresses the characteristics of a battery-less RFID according to the present invention.

FIG. 2 is a block diagram showing an overall configuration of a batteryless RFID according to the present embodiment using the power / RF unit shown in FIG.

FIG. 3 is a diagram showing a specific configuration example of the voltage rectifier circuit shown in FIG.

FIG. 4 is a diagram for explaining the operation of the reset circuit shown in FIG.

5 is a diagram showing a specific configuration example of the reset circuit shown in FIG.

[Explanation of symbols]

1 Voltage Rectifier Circuit 2 Voltage Regulator 3 Reset Circuit 4 FSK Circuit 5 PSK Circuit 6 Clock Circuit 21 CPU 22 ROM 23 EEPROM 24 Power / RF Section 28 Timer 29 Serial I / O Port 30 Tuning Coil 31 Capacitor 32 Smoothing Capacitor S1, S2 Radio wave transmitting / receiving terminal CVdd Internal voltage terminal CGND Internal ground terminal VDD Internal power supply voltage VGND Internal ground voltage RST ₁ , RST ₂ Reset signal V _rst1 , V _rst2 , V _rst3 Reset voltage

Claims (8)

[Claims] 1. A semiconductor integrated circuit device comprising voltage rectifying means for rectifying an AC signal generated and supplied by electromagnetic induction from a radio wave transmitted from the outside to generate a DC internal power supply voltage, wherein the voltage A semiconductor integrated circuit device comprising a voltage control means for controlling the magnitude of a DC voltage obtained by the rectifying means so as not to exceed a predetermined value. 2. Storage means for storing data, a CPU operating in accordance with the stored contents of the storage means, an AC signal generated by electromagnetic induction from a radio wave transmitted from the outside and rectified to generate a direct current. And a voltage rectifying means for generating an internal power supply voltage of the semiconductor integrated circuit device, which resets the CPU and the memory means when the DC voltage obtained by the voltage rectifying means is below a predetermined level. A semiconductor integrated circuit device comprising means. 3. A battery-less RFID having a built-in semiconductor integrated circuit device adapted to transmit / receive data to / from the outside using radio waves and to generate an internal power supply voltage from the received radio waves. A voltage generating means for generating an AC voltage by electromagnetic induction from a radio wave transmitted from the outside of the RFID, a voltage rectifying means for rectifying the AC voltage generated by the voltage generating means into a DC voltage, and the voltage rectifying means. A battery-less RFID, comprising: a voltage control unit that controls the magnitude of the DC voltage so as not to exceed a predetermined value. 4. Storage means for storing data, a CPU that operates according to the stored contents of the storage means, and data transmission and reception by radio waves between the outside under the control of the CPU, and from the received radio waves. A battery-less RFID having a built-in semiconductor integrated circuit device having power / transmission / reception means for generating an internal power supply voltage, the voltage generation means generating an AC voltage by electromagnetic induction from a radio wave transmitted from the outside of the RFID. A voltage rectifying means for rectifying an alternating voltage generated by the voltage generating means into a direct current voltage; and a resetting state of the CPU and the storing means when the direct current voltage obtained by the voltage rectifying means is below a predetermined level. A battery-less RFID, comprising: 5. A storage unit for storing data, a CPU that operates according to the stored contents of the storage unit, and data transmission and reception by radio waves between the outside under the control of the CPU, and from the received radio waves. A battery-less RFID having a built-in semiconductor integrated circuit device having power / transmission / reception means for generating an internal power supply voltage, the voltage generation means generating an AC voltage by electromagnetic induction from a radio wave transmitted from the outside of the RFID. Voltage rectifying means for rectifying the AC voltage generated by the voltage generating means into a DC voltage, and voltage control means for controlling the magnitude of the DC voltage obtained by the voltage rectifying means so as not to exceed a predetermined value. When the DC voltage obtained by the voltage rectifying means is below a predetermined level, the CPU and the storage means are RFID-free battery system characterized by comprising a reset means for setting conditions. 6. The reset means includes the CPU and the CPU when the DC voltage obtained by the voltage rectifying means gradually increases and the DC voltage exceeds a first threshold value. When the reset state of the storage means is released and the direct current voltage obtained by the voltage rectifying means gradually decreases, the storage means is operated when the direct current voltage becomes smaller than the second threshold value. 6. The CPU according to claim 4, wherein the CPU is brought into a reset state, and the CPU is brought into a reset state when the DC voltage becomes smaller than a third threshold value which is smaller than the second threshold value. Battery-less RFID. 7. The battery-less RFID according to claim 6, wherein the second threshold value is smaller than the first threshold value. 8. A battery-less RFID having a built-in semiconductor integrated circuit device, which is adapted to transmit / receive data to / from the outside using radio waves and generate an internal power supply voltage from the received radio waves. A voltage generating means for generating an AC voltage by electromagnetic induction from a radio wave transmitted from the outside of the RFID, a voltage rectifying means for rectifying the AC voltage generated by the voltage generating means into a DC voltage, and the voltage rectifying means. Power storage means for storing DC power, and control for controlling to use the DC power stored in the power storage means as internal power supply when the DC voltage obtained by the voltage rectification means becomes lower than a predetermined level. A batteryless R, characterized by comprising:
FID.