JPH09129746A - Cmos semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the production steps by using an SiO2 film used as an n-well forming mask again as a conventional second n-wells. SOLUTION: N-type impurity is implanted to form an n-well implanted region 5 through SiO2 films 2 and 3 formed as a mask on a p-type semiconductor substrate 1 and diffused to form an n-well region 5. Using the films 2 and 3 as a mask an n-type impurity is implanted to form a second n-well-formed region 6 in the region 5. Thus the films used as an ion-implanting mask for the region 5 are again used for the mask to form the region 6. This eliminates the use of exclusive resist films as before, thereby reducing the mask alignment steps.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a CMOS semiconductor device, and more particularly to a gate Si having two different thicknesses.
C by multi-oxide process with O2 film
The present invention relates to a technique capable of reducing the number of manufacturing steps of a MOS semiconductor device.

[0002]

2. Description of the Related Art A method of manufacturing a CMOS semiconductor device of this type will be described with reference to FIGS. As the film thickness of the gate SiO2 film used here, one is about 300Å for the MOS transistor of normal withstand voltage used for the 5V system of the normal circuit, and the other is for the 40V system for the high power supply circuit. Therefore, the film thickness is about 1000 Å for a high breakdown voltage MOS transistor capable of relaxing the electric field strength and withstanding a high voltage.

Reference numeral 51 shown in FIG. 19 is a P-type semiconductor substrate, and the entire surface of the substrate is oxidized at about 1000 ° C. to about 7,000 Å.
After the SiO2 film 52 having the film thickness is formed, etching is performed using a resist film (not shown) having an opening on the N well forming region as a mask. Next, as shown in FIG. 20, the entire surface of the substrate is pyrooxidized at about 875 ° C. to form an SiO 2 film 53 having a film thickness of about 550 Å, and then phosphorus ions (31 P +) are injected at an acceleration voltage of about 160 KeV and an implantation amount of 3.
5E12 / cm @ 2 (for example, 3.5E12 means 3.5 times 10.sup.12. The same applies hereinafter) to form an N well implantation region 54.

Subsequently, as shown in FIG. 21, about 120
3 hours in O2 atmosphere at 0 ° C and 5 in N2 atmosphere
Anneal for a time to form an N well region 55. next,
As shown in FIG. 22, after removing the SiO2 films 52 and 53, the pad SiO2 film 56 having a film thickness of about 500 Å is formed on the entire surface of the substrate by oxidizing at about 1000 ° C., and a resist film on the P-type semiconductor substrate. After forming 57, the resist film 57 is used as a mask to remove, for example, phosphorus ions (31P).
+) Is about acceleration voltage 160 KeV, injection amount 2.5E1
A second N well implantation region 58 is formed in the N well region 55 by implanting 2 / cm @ 2.

Subsequently, as shown in FIG. 23, after removing the resist film 57, about 1000 Å is formed on the entire surface of the substrate.
A silicon nitride film (SiN) 59 having a film thickness of is formed. Next, as shown in FIG. 24, after forming a resist film 60 having an opening on a LOCOS oxide film forming region to be formed on the N well region in a later step on the entire surface of the substrate, the LOCOS film is formed.
Ion implantation for forming the channel stopper layer of the S oxide film is performed. That is, using the resist film 60 as a mask, for example, phosphorus ions (31 P @ +) are injected with an accelerating voltage of 160 KeV and an injection amount of 2.0E13/cm@2 to form a channel stopper layer forming region 61.

Then, as shown in FIG. 25, the resist film 60 is removed, and LO formed on the entire surface of the substrate in a later step.
Resist film 6 having an opening on the region where the COS oxide film is formed
2 is formed, the silicon nitride film 59 and the pad SiO2 film 56 are etched using the resist film 62 as a mask. Then, as shown in FIG. 26, a high breakdown voltage N channel type MOS on the entire surface of the N well region and a P type substrate described later.
A resist film 63 is formed so as to cover the transistor formation region.
To form Then, using the resist films 62 and 63 as masks, for example, boron ions (11B +) are injected with an accelerating voltage of 80 KeV and an injection amount of 1.5E14/cm@2, and P
A channel stopper layer forming region 64 for a LOCOS oxide film is formed on the mold substrate.

Next, as shown in FIG. 27, after removing the resist films 62 and 63, annealing is performed in an N 2 atmosphere at about 1000 ° C. for 1 hour, and further wet oxidation is performed to form a LOCOS oxide film having a thickness of about 10000Å. 65 to form the silicon nitride film 59 and the pad SiO2 film 56.
Of the dummy SiO2 film 66 having a film thickness of about 550 Å by dummy oxidation at about 1000 ° C.
To form

Then, as shown in FIG. 28, an LN for a high breakdown voltage N channel type MOS transistor on the P type substrate.
After forming a resist film 67 having an opening on the diffusion layer forming region, for example, phosphorus ions (31 P +) are injected with an acceleration voltage of 130 KeV and an injection amount of 7.0E12 / cm 2 using the resist film 67 as a mask for the LN diffusion layer. The implanter layer 68 of is formed.

Similarly, as shown in FIG. 29, a resist film 6 having an opening on an LP diffusion layer forming region for a high breakdown voltage P channel type MOS transistor described later on the N well region.
After forming 9, the resist film 69 is used as a mask, and boron ions (11B +), for example, are accelerated to an accelerating voltage of 60 Ke.
Then, an implantation amount of 1.0E13/cm@2 is applied to form an implantation layer 70 for the LP diffusion layer.

Then, the resist film 69 is removed, and the resist film 69 is diffused in an N 2 atmosphere at about 1135 ° C. for 15 minutes.
As shown in FIG. 0, after forming the LN diffusion layer 71 and the LP diffusion layer 72, the dummy SiO2 film 66 is removed, and then pyrooxidized at about 875 ° C. to form a gate SiO2 film 73 with a thickness of about 950Å. . Next, as shown in FIG. 31, after forming a resist film 74 having an opening on the formation region of P-channel type and N-channel type MOS transistors having a normal withstand voltage which will be described later, the resist film 74 is used as a mask for the normal withstand voltage. The gate SiO2 film 73 on the formation region of the P channel type MOS transistor and the normal breakdown voltage N channel type MOS transistor is removed by etching. Then, after removing the resist film 74, as shown in FIG. 32, a gate SiO2 film 75 having a film thickness of approximately 300Å and a gate SiO2 film 73A having a film thickness of approximately 1000Å are formed by pyrooxidation in an atmosphere of approximately 900 ° C. To do.

Subsequently, as shown in FIG. 33, a resist film 76 having an opening is formed on a high breakdown voltage N channel type MOS transistor forming region on a P type substrate, and then, for example, boron ions are used with the resist film 76 as a mask. (11B +)
Acceleration voltage of 160 KeV, injection amount of 1.0E12 /
cm 2 is implanted to form a channel implantation layer 77 for the transistor, and the resist film 76 is removed.

Then, as shown in FIG. 34, after forming a resist film 78 having an opening on the high breakdown voltage P channel type MOS transistor forming region formed on the N well region, using the resist film 78 as a mask, for example, boron is used. Ion (11B +) is injected with an accelerating voltage of about 70 KeV and an injection amount of 1.
5E12 / cm @ 2 is injected to form a channel implantation layer 79 for the transistor, and the resist film 78 is removed.

Next, as shown in FIG. 35, after forming a resist film 80 having an opening on a normal breakdown voltage N-channel type MOS transistor forming region on a P-type substrate, using the resist film 80 as a mask, for example, boron ions are formed. (11B +)
Acceleration voltage of 160 KeV, injection amount of 1.0E12 /
cm 2 is implanted to form a first channel implantation layer 81 for the transistor, and thereafter, the resist film 8 is also formed.
With 0 as a mask, for example, boron ions (11B +) are implanted at an accelerating voltage of 35 KeV and an implantation amount of 8.0E11/cm@2 to form a second implantation layer 82, and the resist film 8 is formed.
Remove 0.

Then, as shown in FIG. 36, after forming a resist film 83 having an opening on the normal breakdown voltage P channel type MOS transistor forming region formed on the N well region, for example, using the resist film 83 as a mask, for example, boron. Ions (11B +) are implanted with an accelerating voltage of 35 KeV and an implantation amount of 1.25E12 / cm2 to form a channel implantation layer 84 for the transistor, and the resist film 83 is removed.

Next, after forming a polysilicon film on the entire surface, patterning is performed using a resist film (not shown) as a mask to form gate electrodes 85A, 85B, 8 as shown in FIG.
5C and 85D are formed. Then, after forming a resist film 86 having an opening on the N + type diffusion layer forming region of the high breakdown voltage N channel type MOS transistor formed on the P type substrate on the entire surface of the substrate, the resist film 86 and the gate electrode 8 are formed.
Using 5B as a mask, for example, phosphorus ions (31 P +) are implanted with an accelerating voltage of 80 KeV and an implantation amount of 4.0E15 / cm2 to form an N + type diffusion layer 87, and the resist film 86 is removed.

Then, as shown in FIG. 38, a resist film 8 having an opening on an N-type diffusion layer forming region for a normal breakdown voltage N channel type MOS transistor formed on a P type substrate.
8 is formed on the entire surface of the substrate, and then, for example, phosphorus ions (31P) are formed using the resist film 88 and the gate electrode 85A as a mask.
+) Is about 80 KeV in acceleration voltage and 3.5E13 in injection amount
/ Cm @ 2 to form an N @-type diffusion layer 89, and then, for example, arsenic ions (75 As @ +) are accelerated to about 8 by using the resist film 88 and the gate electrode 85A as a mask.
An N + type diffusion layer 90 is formed by implanting 0 KeV and an implantation amount of 5.0E15 / cm2, and the resist film 88 is removed.

Next, as shown in FIG. 39, after forming a resist film 91 having an opening on the P + type diffusion layer forming region formed on the N well region on the entire surface of the substrate, the resist film 9 is formed.
1 and the gate electrodes 85C and 85D are used as masks, for example, boron ions (11P +) are accelerated at an acceleration voltage of 40 KeV,
Implantation amount 1.0E15/cm@2 P + type diffusion layer 92
And the resist film 91 is removed. And FIG.
After forming the interlayer insulating film 93 on the entire surface as shown in 0,
A contact hole is formed on each diffusion layer through a resist film (not shown), patterning is performed to form a metal wiring 94 through the contact hole, and a passivation film (not shown) is further formed thereon. This allows two types of film thickness (300Å, 100) on the N well region and the P type substrate.
CMO having 0Å) gate SiO2 film 75, 73A
An S semiconductor device is formed.

As described above, in this example, although it is a single-layer wiring, 19 resist films (for forming the N well, for forming the second N well formed in the N well region (57), on the N well region). For forming a channel stopper layer of the LOCOS oxide film to be formed on (60) and for forming a LOCOS oxide film (6)
2), for forming a channel stopper layer of a LOCOS oxide film formed on a P-type substrate (63), for forming a low-concentration LN diffusion layer (67), for forming a low-concentration LP diffusion layer (69), with a normal breakdown voltage For etching gate SiO2 film of MOS transistor (74), high breakdown voltage N channel type M on P type substrate
For forming channel implant layer of OS transistor (7
6), for forming a channel implantation layer of a high breakdown voltage P channel type MOS transistor on the N well region (78), for forming a channel implantation layer of a normal breakdown voltage N channel type MOS transistor on a P type substrate (80), N N + of a high breakdown voltage N-channel type MOS transistor for forming a channel implantation layer (83) of a normal breakdown voltage P-channel type MOS transistor on a well region, forming a gate electrode, and a P-type substrate
Type diffusion layer formation (86), N-type and N + type diffusion layer formation of a normal breakdown voltage N channel type MOS transistor on a P type substrate (88), P + type diffusion layer formation on the N well region (91), for forming contact holes, for forming metal wiring and for forming a passivation film) is a long process, which requires a large number of mask alignment steps and increases the cost of the mask, resulting in an increase in cost. It was

[0019]

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide a method for manufacturing a CMOS semiconductor device which can reduce the number of manufacturing steps.

[0020]

Therefore, according to the present invention, the N 2 is formed by using the SiO 2 film 2 formed on the P-type semiconductor substrate 1 as a mask.
A step of implanting a type impurity and then diffusing it to form an N well region 5, and forming a pad SiO2 film 7 and a silicon nitride film 8 on the substrate, and then forming an L on the N well region 5.
Resist film 9 having openings on the OCOS oxide film forming region
A step of implanting an N-type impurity for the channel stopper layer forming region 10 through the via, and a normal breakdown voltage and a high breakdown voltage of P-type and N-type.
Type pad other than the MOS transistor formation region
A step of removing the O2 film 7 and the silicon nitride film 8 and a resist film 12 formed so as to cover the entire surface of the N well region and the pad SiO2 film 7 and the silicon nitride film 8 on the high breakdown voltage MOS transistor forming region on the substrate. A step of implanting a P-type impurity for the channel stopper layer forming region 13 as a mask, a step of removing the resist film 12 and then field oxidizing the substrate to form a LOCOS oxide film 14, and a mask of the LOCOS oxide film 14. As a step of removing the pad SiO2 film 7 and the silicon nitride film 8 and then oxidizing the pad SiO2 film 7 to form a gate SiO2 film 22, a resist film 23 having an opening on the normal breakdown voltage P-type and N-type MOS transistor forming regions is formed. The MOS as a mask
Implanting P-type impurities for the channel implantation layer 24 for the transistor, and removing the gate SiO2 film 22 on the P-type and N-type MOS transistor forming regions of the normal breakdown voltage using the resist film 23 as a mask, After removing the resist film 23, the entire surface of the substrate is oxidized to form a gate SiO2 film 22A on the P-type and N-type MOS transistor forming regions of normal breakdown voltage and the gate SiO2 on the P-type and N-type MOS transistor forming regions of high breakdown voltage. It comprises a step of forming a gate SiO2 film 22B thicker than the film 22A, and a step of forming a normal breakdown voltage and high breakdown voltage MOS transistor on the substrate and the N well region, respectively.

The present invention also includes a step of forming an N well region 5 by implanting an N type impurity using the SiO 2 film 2 formed on the P type semiconductor substrate 1 as a mask and then diffusing it.
The N 2 -type impurity is implanted by using the iO 2 film 2 as a mask.
Forming a second N well forming region 6 in the well region 5, forming a pad SiO2 film 7 and a silicon nitride film 8 over the entire surface of the substrate after removing the SiO2 film 2, and the N well region 5 A step of forming a resist film 9 having an opening on the LOCOS oxide film forming region formed above and then implanting a P-type impurity for the channel stopper layer forming region 10 using the resist film 9 as a mask, and a normal breakdown voltage and a high breakdown voltage. The step of removing the pad SiO2 film 7 and the silicon nitride film 8 other than on the P-type and N-type MOS transistor forming regions, and the pad SiO2 film 7 on the entire N well region and the high breakdown voltage MOS transistor forming region on the substrate. And a resist film 1 formed so as to cover the silicon nitride film 8.
2 as a mask, a step of implanting a P-type impurity for the channel stopper layer forming region 13, a step of removing the resist film 12 and then field oxidizing the substrate to form a LOCOS oxide film 14, and a step of forming the LOCOS oxide film 14 Using the mask as a mask to remove the pad SiO2 film 7 and the silicon nitride film 8 and then oxidize to form a gate SiO2 film 22, and formation of a low concentration LN diffusion layer for a high breakdown voltage MOS transistor formed on the substrate. A step of implanting an N-type impurity for forming an LN diffusion layer through a resist film 16 having an opening on the region, and a low concentration LP diffusion layer forming region for a high breakdown voltage MOS transistor formed on the N well region The step of implanting a P-type impurity for forming an LP diffusion layer through the resist film 18 having an opening above, and the resist film 18 was removed. Forming a low-concentration LN diffusion layer 20 and LP diffusion layer 21 for high breakdown voltage P-type and N-type MOS transistors which are to be diffused and formed on the substrate and N-well region; and on the N-well region. A step of oxidizing the entire surface of the substrate to form a gate SiO2 film 22 and a channel implantation layer 24 for the MOS transistor using the resist film 23 having an opening on the P-type and N-type MOS transistor forming regions of the normal breakdown voltage as a mask. The step of implanting the P-type impurities, the step of removing the gate SiO2 film 22 on the P-type and N-type MOS transistor forming regions of the normal breakdown voltage by using the resist film 23 as a mask, and after removing the resist film 23. The gate SiO2 film 22A and the high withstand voltage P-type and N-type MOS transistors are formed on the P-type and N-type MOS transistor forming regions with the normal withstand voltage by oxidation. A gate S thicker than the gate SiO2 film 22A is formed on the transistor forming region.
It comprises a step of forming an iO2 film 22B and a step of forming a normal breakdown voltage and a high breakdown voltage MOS transistor on the substrate and the N well region, respectively.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Two kinds of gates S of the present invention having different thicknesses.
1 to 1 show a method of manufacturing a CMOS semiconductor device by a multi-oxide process having an iO2 film.
It will be described with reference to FIG. Reference numeral 1 shown in FIG. 1 is a P-type semiconductor substrate. After the entire surface of the substrate is oxidized at about 1000 ° C. to form a SiO 2 film 2 having a thickness of about 7,000 Å, a resist film (not shown) having an opening on the N well formation region is formed. Etch using as a mask.

Next, as shown in FIG. 2, the entire surface of the substrate is pyrooxidized at about 875 ° C. to form Si having a film thickness of about 550Å.
After the O2 film 3 is formed, phosphorus ions (31P +), for example, are applied to the accelerating voltage 1 with the SiO2 films 2 and 3 as a mask.
60 KeV, injection amount 3.5E12 / cm2, first injection
The N well implantation region 4 is formed. Then, about 12
N well region 5 by diffusing for 8 hours in N2 atmosphere at 00 ° C
Is formed (see FIG. 3).

Next, as shown in FIG. 4, using the SiO 2 films 2 and 3 as a mask, for example, phosphorus ions (31 P +) are accelerated at an acceleration voltage of 160 KeV and the implantation amount is 2.5E12 / cm.
2 implantation is performed to form a second N well implantation region 6. Thus, in this step, the SiO2 film 2 used as a mask for ion implantation for forming the N well region 5,
Since 3 also serves as a mask for forming the second N well implantation region 6, it is not necessary to use a dedicated resist film (resist film 57 shown in FIG. 22) as in the conventional case, and this mask alignment step can be reduced. .

Then, after removing the SiO2 film on the entire surface of the substrate, pad oxidation is performed at about 1000.degree. C. to form a pad SiO2 film 7 having a film thickness of about 500 .ANG. As shown in FIG. A silicon nitride film (SiN) 8 having a film thickness of is formed. Next, as shown in FIG. 6, after forming a resist film 9 having an opening on a formation region of a LOCOS oxide film which will be formed on the N well region in a later step, which will be described later, on the entire surface of the substrate, a channel of the LOCOS oxide film is formed. Ion implantation for forming the stopper layer is performed. That is, using the resist film 9 as a mask, for example, phosphorus ions (31P +)
Acceleration voltage of 160 KeV, injection amount of 2.0E13 /
A channel stopper layer forming region 10 is formed by implanting cm 2.

Subsequently, as shown in FIG. 7, the resist film 9 is removed, and a resist film 11 having an opening is formed on the entire surface of the substrate on a LOCOS oxide film forming region to be formed in a later step. As shown, a resist film 12 is formed so as to cover the N well region and the formation region of a high breakdown voltage P channel type MOS transistor on a P type semiconductor substrate described later. Then, using the resist films 11 and 12 as masks, for example, boron ions (11B +) are accelerated to about 16
A channel stopper layer forming region 13 for a LOCOS oxide film to be formed on a P-type substrate is formed by injecting 0 KeV and an injection amount of 2.0E14/cm@2. By optimizing the implantation conditions of the ion implantation at this time, a normal breakdown voltage N-channel MO formed on a P-type substrate shown in FIG.
Since the step of forming the N + type diffusion layer 31 for the S-transistor can be performed by one-time phosphorus ion (31P +) implantation, as shown in FIG. And it is not necessary to form the N + type diffusion layer 90 by implanting arsenic ions (75 As +),
This can be simultaneously formed in the step of forming the N + type diffusion layer 87 for the high breakdown voltage N channel type MOS transistor in the previous step shown in FIG.

Next, after removing the resist films 11 and 12, the resist film 11 and 12 are annealed in an N 2 atmosphere at about 1000 ° C. for 1 hour, and further wet-oxidized to form a LOCOS oxide film 14 having a thickness of about 10000Å. After the silicon nitride film 8 and the SiO2 film 7 are removed by etching, dummy oxidation is performed at about 1000 DEG C. to form a SiO2 film 15 having a film thickness of about 550Å.

Then, as shown in FIG. 10, an LN for a high breakdown voltage N channel type MOS transistor on the P type substrate.
After forming the resist film 16 having an opening on the diffusion layer formation region, for example, phosphorus ions (31 P +) are injected with an acceleration voltage of 140 KeV and an injection amount of 6.0E12 / cm2 using the resist film 16 as a mask for the LN diffusion layer. The implanter layer 17 is formed.

Similarly, as shown in FIG. 11, a resist film 1 having an opening on an LP diffusion layer forming region for a later-described high breakdown voltage P channel type MOS transistor on the N well region.
8 is formed, then, with the resist film 18 as a mask, for example, boron ions (11B +) are accelerated to about 60 Ke.
Then, the implantation amount of V is 9.0E12/cm@2 and the implantation layer 19 for the LP diffusion layer is formed.

Then, the resist film 18 is removed and N 2
Diffusion for 60 minutes at about 1135 ℃ in the atmosphere,
As shown in FIG. 2, after the LN diffusion layer 20 and the LP diffusion layer 21 are formed, the dummy SiO2 film 15 is removed and then pyrooxidized at about 875 ° C. to form a gate oxide film 22 having a thickness of about 1000Å. . Next, as shown in FIG. 13, after forming a resist film 23 having an opening on a formation region of a normal breakdown voltage P-channel type and N-channel type MOS transistor, which will be described later, using the resist film 23 as a mask, for example, boron ions ( 11B +) with an accelerating voltage of 35 KeV or boron fluoride ion (49BF2 +)
With an accelerating voltage of 80 KeV and an injection amount of 1.0E12 /
cm 2 is implanted to form a channel implantation layer 24 for each transistor. Then, after the gate oxide film 22 in both the transistor forming regions is removed by etching using the resist film 23 as a mask, the resist film 23 is removed to remove 9
Pyrooxidation is performed in an atmosphere of 00 ° C. to form a gate SiO 2 film 22A having a film thickness of about 300Å and a gate SiO2 film 22B having a film thickness of about 1000Å. Thus, in this embodiment, the normal breakdown voltage P-channel MOS shown in FIG.
As shown in FIG. 13, a resist film 23 as a mask for etching and removing the gate SiO2 film 22 on a transistor and a normal breakdown voltage N channel type MOS transistor forming region is used for ion implantation for forming a channel implantation layer 24 for the transistor. Since it also serves as the mask, the conventional ion implantation process using the resist films 80 and 83 shown in FIGS. 35 and 36 is not required, and the mask alignment process can be reduced.

Next, as shown in FIG. 15, after forming a resist film 25 on the N well region, using the resist film 25 as a mask, for example, boron ions (11B +) are accelerated at an acceleration voltage of 160 KeV and an implantation amount of 1.0E12. / Cm @ 2 to form a second implantation layer 26. Subsequently, FIG.
After forming a resist film 27 having an opening on a high breakdown voltage P channel type MOS transistor forming region formed on the N well region as shown in FIG. An acceleration voltage of 70 KeV and an injection amount of 1.5E12/cm@2 are injected to form a third implantation layer 28, and the resist film 27 is removed.

Next, after forming a polysilicon film on the entire surface, patterning is performed using a resist film (not shown) as a mask to form gate electrodes 29A, 29B, 2 as shown in FIG.
9C and 29D are formed. Then, the resist film 3 having an opening on the N + type diffusion layer forming region formed on the P type substrate
3. After forming 0 on the entire surface of the substrate, phosphorus ions (31 P +), for example, are accelerated at an acceleration voltage of 80 KeV with the resist film 30 and the gate electrodes 29A and 29B as a mask and the implantation amount is 4.
Implantation of 0E15 / cm @ 2 is performed to form an N @ + type diffusion layer 31.

Similarly, as shown in FIG. 18, after forming a resist film 32 having an opening on the P + type diffusion layer forming region formed on the N well region on the entire surface of the substrate, the resist film 32 and the gate electrode 29C are formed. , 29D as a mask, for example, boron ions (11B +) are accelerated at about 40 Ke.
Then, a P + type diffusion layer 33 is formed by injecting V at an injection amount of 1.0E15/cm@2, and the resist film 32 is removed. And
Although not shown, after forming an interlayer insulating film on the entire surface, contact holes are formed on each diffusion layer through a resist film (not shown), and patterning is performed to form metal wiring through the contact holes. A passivation film (not shown) is formed. As a result, the N well region and P
A CMOS semiconductor device having two types of film thicknesses (300Å, 1000Å) of the gate oxide films 22A and 22B is formed on the mold substrate.

As described above, according to the present invention, the process of using 19 resist films in the past is performed in the same manner as in the case of forming 15 resist films (N well formation and second N well formation in the N well region, LOCOS formed on N well region
For forming channel stopper layer of oxide film (9), LOCOS
LOCO for forming oxide film (11) on P-type substrate
For forming a channel stopper layer of an S oxide film (12), for forming a low-concentration LN diffusion layer (16), for forming a low-concentration LP diffusion layer (18), for forming a channel implantation layer of a normal breakdown voltage MOS transistor, and For etching the gate SiO2 film on the transistor formation region (23), for forming the channel implantation layer of the N channel type MOS transistor on the P type substrate (25), and for the channel of the high breakdown voltage P channel type MOS transistor on the N well region. For forming an implantation layer (27), for forming a gate electrode, for forming an N + type diffusion layer of an N channel type MOS transistor on a P type substrate (30),
P of the P channel type MOS transistor on the N well region
It can be formed by + type diffusion layer formation (32), contact hole formation, metal wiring formation, and passivation film formation, which can reduce the number of mask alignment steps and lower the cost of the mask, resulting in cost reduction. Be peeled off.

As described above, according to the present invention, the SiO 2 films 2 and 3 used as the mask for forming the N well as shown in FIG. 4 are formed in the conventional N well region shown in FIG. It can also be used as a mask for forming a region, and the number of mask alignment steps can be reduced. Also,
By optimizing the implantation condition of boron ion (11B +) for the channel stopper layer under the LOCOS oxide film formed on the P-type substrate shown in FIG. 8, one resist film is used as shown in FIG. Then, by implanting phosphorus ions (31P +), a normal breakdown voltage and high breakdown voltage N-channel type MO
It is possible to form an N + type diffusion layer for an S transistor, and at the same time, as shown in FIG.
There is no need to implant two types of ions, +) and arsenic ions (75As +). Further, by optimizing the process conditions, the breakdown voltage can be increased from the conventional 40V to 45V.

Further, as shown in FIG. 13, the gate SiO2
Since the resist film for etching the film is used to perform the ion implantation for forming the channel implantation layer for the normal breakdown voltage P-channel type and N-channel type MOS transistors, the conventional N shown in FIGS. It is possible to reduce the two mask aligning steps for forming the channel implantation layer on the well region and the MOS transistor forming region of the normal breakdown voltage on the P-type substrate.

[0037]

As described above, according to the method of manufacturing the CMOS semiconductor device of the present invention, the SiO2 film used as the mask for forming the N well is also used as the mask for forming the second conventional N well, thereby forming a mask. The number of processes can be reduced. Also, a normal level MO on the N well region and on the P type substrate
Since the mask for removing the gate oxide film on the S-transistor formation region is also used as the mask for the channel implantation of the transistor, the conventional channel implantation of the MOS transistor formation region on the N-well region and the P-type substrate is performed. It is possible to eliminate the step of aligning two masks for forming layers.

[Brief description of the drawings]

FIG. 1 is a first cross-sectional view showing a method for manufacturing a CMOS semiconductor device of the present invention.

FIG. 2 is a second cross-sectional view showing the method of manufacturing the CMOS semiconductor device of the present invention.

FIG. 3 is a third cross-sectional view showing the method of manufacturing the CMOS semiconductor device of the present invention.

FIG. 4 is a fourth cross-sectional view showing the method of manufacturing the CMOS semiconductor device of the present invention.

FIG. 5 is a fifth cross-sectional view showing the method of manufacturing the CMOS semiconductor device of the present invention.

FIG. 6 is a sixth cross-sectional view showing the method of manufacturing the CMOS semiconductor device of the present invention.

FIG. 7 is a seventh cross-sectional view showing the method of manufacturing the CMOS semiconductor device of the present invention.

FIG. 8 is an eighth cross-sectional view showing the method of manufacturing the CMOS semiconductor device of the present invention.

FIG. 9 is a ninth cross-sectional view showing the method of manufacturing the CMOS semiconductor device of the present invention.

FIG. 10 is a tenth sectional view showing the method for manufacturing the CMOS semiconductor device of the present invention.

FIG. 11 is an eleventh cross-sectional view showing the method of manufacturing the CMOS semiconductor device of the present invention.

FIG. 12 is a twelfth sectional view showing the method of manufacturing the CMOS semiconductor device of the present invention.

FIG. 13 is a thirteenth sectional view showing the method of manufacturing the CMOS semiconductor device of the present invention.

FIG. 14 is a fourteenth sectional view showing the method of manufacturing the CMOS semiconductor device of the present invention.

FIG. 15 is a fifteenth sectional view showing the method of manufacturing the CMOS semiconductor device of the present invention.

FIG. 16 is a sixteenth sectional view showing the method for manufacturing the CMOS semiconductor device of the present invention.

FIG. 17 is a seventeenth sectional view showing the method for manufacturing the CMOS semiconductor device of the present invention.

FIG. 18 is an eighteenth sectional view showing the method for manufacturing the CMOS semiconductor device of the present invention.

FIG. 19 is a first cross-sectional view showing the method of manufacturing the conventional CMOS semiconductor device.

FIG. 20 is a second cross-sectional view showing the method of manufacturing the conventional CMOS semiconductor device.

FIG. 21 is a third cross-sectional view showing the method of manufacturing the conventional CMOS semiconductor device.

FIG. 22 is a fourth cross-sectional view showing the method of manufacturing the conventional CMOS semiconductor device.

FIG. 23 is a fifth cross-sectional view showing the method of manufacturing the conventional CMOS semiconductor device.

FIG. 24 is a sixth cross-sectional view showing the method of manufacturing the conventional CMOS semiconductor device.

FIG. 25 is a seventh cross-sectional view showing the method of manufacturing the conventional CMOS semiconductor device.

FIG. 26 is an eighth cross-sectional view showing the method of manufacturing the conventional CMOS semiconductor device.

FIG. 27 is a ninth cross-sectional view showing the method of manufacturing the conventional CMOS semiconductor device.

FIG. 28 is a tenth sectional view showing the method for manufacturing the conventional CMOS semiconductor device.

FIG. 29 is an eleventh sectional view showing the method for manufacturing the conventional CMOS semiconductor device.

FIG. 30 is a twelfth sectional view showing the method for manufacturing the conventional CMOS semiconductor device.

FIG. 31 is a thirteenth cross-sectional view showing the method of manufacturing the conventional CMOS semiconductor device.

FIG. 32 is a fourteenth sectional view showing the method for manufacturing the conventional CMOS semiconductor device.

FIG. 33 is a fifteenth sectional view showing the method of manufacturing the conventional CMOS semiconductor device.

FIG. 34 is a sixteenth sectional view showing the method for manufacturing the conventional CMOS semiconductor device.

FIG. 35 is a seventeenth sectional view showing the method for manufacturing the conventional CMOS semiconductor device.

FIG. 36 is an eighteenth sectional view showing the method for manufacturing the conventional CMOS semiconductor device.

FIG. 37 is a nineteenth sectional view showing the method for manufacturing the conventional CMOS semiconductor device.

FIG. 38 is a twentieth sectional view showing the method for manufacturing the conventional CMOS semiconductor device.

FIG. 39 is a 21st sectional view showing the method for manufacturing the conventional CMOS semiconductor device.

FIG. 40 is a twenty-second cross-sectional view showing the method of manufacturing the conventional CMOS semiconductor device.

Claims (2)

[Claims] 1. SiO 2 formed on a P-type semiconductor substrate 1.
A step of implanting N-type impurities using the film 2 as a mask and then diffusing it to form an N well region 5, and a pad SiO2 film 7 and a silicon nitride film 8 on the substrate.
After the formation of the N-type well, a step of implanting an N-type impurity for the channel stopper layer forming region 10 through the resist film 9 having an opening on the LOCOS oxide film forming region on the N well region 5, and a normal breakdown voltage and a high breakdown voltage. A step of removing the pad SiO2 film 7 and the silicon nitride film 8 other than on the P-type and N-type MOS transistor forming regions, and the pad SiO2 film 7 on the entire surface of the N-well region and the high breakdown voltage MOS transistor forming region on the substrate. A step of implanting P-type impurities for the channel stopper layer forming region 13 using the resist film 12 formed so as to cover the silicon nitride film 8 as a mask, and after removing the resist film 12, the substrate is field-oxidized to LOCOS oxide film. And forming the pad S using the LOCOS oxide film 14 as a mask.
A step of removing the iO2 film 7 and the silicon nitride film 8 and then oxidizing the gate SiO2 film 22 to form a gate SiO2 film 22, and using the resist film 23 having an opening on the P-type and N-type MOS transistor forming regions of the normal breakdown voltage as a mask. P for the channel implantation layer 24 for the MOS transistor
Implanting a type impurity, and using the resist film 23 as a mask, the gate SiO on the P-type and N-type MOS transistor forming regions of the normal breakdown voltage.
2 step of removing the film 22, and after removing the resist film 23, the entire surface of the substrate is oxidized to form a gate SiO2 film 22A and a high withstand voltage P-type and N-type on the normal withstand voltage P-type and N-type MOS transistor formation region. MO
The gate SiO2 film 22 is formed on the S transistor forming region.
A method of manufacturing a CMOS semiconductor device, comprising: forming a gate SiO2 film 22B thicker than A; and forming a normal breakdown voltage and high breakdown voltage MOS transistor on the substrate and the N well region, respectively. 2. SiO 2 formed on a P-type semiconductor substrate 1.
A step of implanting an N-type impurity using the film 2 as a mask and then diffusing it to form an N-well region 5; and a step of implanting an N-type impurity using the SiO 2 film 2 as a mask to implant a second N-type A step of forming a well forming region 6, and a pad Si on the entire surface of the substrate after removing the SiO2 film 2.
A step of forming an O2 film 7 and a silicon nitride film 8, and a channel stopper layer using the resist film 9 as a mask after forming a resist film 9 having an opening on the LOCOS oxide film forming region formed on the N well region 5. A step of implanting P-type impurities for the formation region 10, a step of removing the pad SiO2 film 7 and the silicon nitride film 8 other than those on the normal and high breakdown voltage P-type and N-type MOS transistor formation regions, and an N well A P-type impurity for the channel stopper layer forming region 13 is implanted using the resist film 12 formed so as to cover the pad SiO2 film 7 and the silicon nitride film 8 over the entire region and the high breakdown voltage MOS transistor forming region on the substrate as a mask. A step of forming the LOCOS oxide film 14 by field-oxidizing the substrate after removing the resist film 12; Said pad S a serial LOCOS oxide film 14 as a mask
A step of removing the iO2 film 7 and the silicon nitride film 8 and then oxidizing it to form a gate SiO2 film 22, and forming an opening on a low concentration LN diffusion layer forming region for a high breakdown voltage MOS transistor formed on the substrate. A step of implanting an N-type impurity for forming an LN diffusion layer through the resist film 16 which has, and an opening on a low concentration LP diffusion layer forming region for a high breakdown voltage MOS transistor formed on the N well region. A step of implanting a P-type impurity for forming an LP diffusion layer through the resist film 18, and a high breakdown voltage P-type and N-type which is diffused and formed on the substrate and the N-well region after the resist film 18 is removed. MOS
Forming a low concentration LN diffusion layer 20 and an LP diffusion layer 21 for a transistor, and oxidizing the entire surface of the substrate on the N well region to form a gate SiO
2 step of forming the film 22, and using the resist film 23 having an opening on the P-type and N-type MOS transistor forming regions of the normal breakdown voltage as a mask, forming a P for the channel implantation layer 24 for the MOS transistor.
Implanting a type impurity, and using the resist film 23 as a mask, the gate SiO on the P-type and N-type MOS transistor forming regions of the normal breakdown voltage.
2 a step of removing the film 22, and a step of removing the resist film 23 and then oxidizing it to form a gate S on the P-type and N-type MOS transistor forming regions of normal breakdown voltage.
a step of forming a gate SiO2 film 22B thicker than the gate SiO2 film 22A on the iO2 film 22A and a high withstand voltage P-type and N-type MOS transistor forming region, and a normal withstand voltage and a high withstand voltage on the substrate and the N well region, respectively. And a step of forming a MOS transistor, the method for manufacturing a CMOS semiconductor device.