JPH09129404A - Chip-type varistor - Google Patents
Chip-type varistorInfo
- Publication number
- JPH09129404A JPH09129404A JP7278801A JP27880195A JPH09129404A JP H09129404 A JPH09129404 A JP H09129404A JP 7278801 A JP7278801 A JP 7278801A JP 27880195 A JP27880195 A JP 27880195A JP H09129404 A JPH09129404 A JP H09129404A
- Authority
- JP
- Japan
- Prior art keywords
- varistor
- lead terminal
- chip
- ceramic
- molding resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明はテレビジョン受像
機、洗濯機、自動車電装装置などの電源回路に生じるサ
ージ電圧を吸収する異常電圧対策に用いるチップ型バリ
スタに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip type varistor used as a countermeasure against an abnormal voltage that absorbs a surge voltage generated in a power supply circuit of a television receiver, a washing machine, an automobile electrical equipment and the like.
【0002】[0002]
【従来の技術】図15、図16において、11はバリス
タ素子である。12a,12bはバリスタ素子11の主
平面に設けた電極、13a,13bはリード端子、14
a,14bは電極12a,12bとリード端子13a,
13bを接続する導電性接着剤である。15はモールド
樹脂である。以上のように構成されたチップ型バリスタ
について、以下その動作について説明する。2. Description of the Related Art In FIG. 15 and FIG. 16, 11 is a varistor element. 12a and 12b are electrodes provided on the main plane of the varistor element 11, 13a and 13b are lead terminals, 14
a and 14b are electrodes 12a and 12b and lead terminals 13a,
It is a conductive adhesive that connects 13b. Reference numeral 15 is a mold resin. The operation of the chip-type varistor having the above structure will be described below.
【0003】まず、バリスタ素子11自身が耐え得ない
ような異常高電圧が負荷された場合、バリスタ素子11
が貫通破壊を起こす。First, when an abnormally high voltage that the varistor element 11 itself cannot withstand is loaded, the varistor element 11 is
Causes penetration failure.
【0004】[0004]
【発明が解決しようとする課題】前記の従来の構成では
モールド樹脂15によって覆われており、バリスタ素子
11が貫通破壊した際に、それに伴って発生する高圧ガ
スがモールド樹脂15を破壊し、バリスタ素子11とリ
ード端子13a,13bの導通を断つ。しかしモールド
樹脂15の破壊される箇所によっては、バリスタ素子1
1が開放状態にならないおそれがあるという問題を有し
ていた。In the above conventional structure, the mold resin 15 is covered, and when the varistor element 11 breaks through, the high pressure gas generated therewith breaks the mold resin 15 and the varistor is generated. The conduction between the element 11 and the lead terminals 13a and 13b is cut off. However, depending on where the mold resin 15 is destroyed, the varistor element 1
1 had a problem that it might not be in an open state.
【0005】本発明は従来の課題を解決するもので、バ
リスタ素子11が貫通破壊した場合、確実に開放状態と
なるようにすることを目的とする。The present invention solves the conventional problems, and an object of the present invention is to ensure that the varistor element 11 will be in an open state when it is broken through.
【0006】[0006]
【課題を解決するための手段】この目的を達成するため
に本発明のチップ型バリスタは、リード端子外周に沿っ
たモールド樹脂の上部表面に溝を設け、これにより初期
の目的を達成するものである。In order to achieve this object, the chip type varistor of the present invention achieves the initial purpose by providing a groove on the upper surface of the mold resin along the outer circumference of the lead terminal. is there.
【0007】[0007]
【発明の実施の形態】本発明の請求項1に記載の発明に
よれば、モールド樹脂の上部表面に設けた溝の部分の機
械的強度が溝の無い部分より弱くなる。したがってバリ
スタ素子が貫通破壊を起こした場合、発生したガスの圧
力により溝の部分よりせん断され、リード端子と共にリ
ード端子上面のモールド樹脂が蓋が開くように剥離す
る。このため電極とリード端子間は電気的に開放状態と
なる。According to the invention described in claim 1 of the present invention, the mechanical strength of the groove portion provided on the upper surface of the mold resin is weaker than that of the portion having no groove. Therefore, when the varistor element breaks through, it is sheared from the groove portion by the pressure of the generated gas, and the mold resin on the upper surface of the lead terminal is peeled off so that the lid opens together with the lead terminal. Therefore, the electrode and the lead terminal are electrically opened.
【0008】(実施形態1)図1は本発明の実施例にお
けるチップ型バリスタの上面図、図2は上面透視図、図
3は図1のA−A断面図を示すものである。図3におい
て、21は酸化亜鉛系のセラミックバリスタ素子であ
る。22はセラミックバリスタ素子21の主平面に設け
た電極、23a,23bはリード端子である。24は電
極22とリード端子23a,23bを電気的に接続する
導電性接着剤である。25はバリスタ全体を覆ったエポ
キシ絶縁樹脂よりなるモールド樹脂、26はリード端子
23b外周に沿ってモールド樹脂25の上部表面に設け
られた溝である。以上のように構成されたバリスタの動
作について図を用いて説明する。(Embodiment 1) FIG. 1 is a top view of a chip type varistor in an embodiment of the present invention, FIG. 2 is a top perspective view, and FIG. 3 is a sectional view taken along line AA of FIG. In FIG. 3, reference numeral 21 is a zinc oxide-based ceramic varistor element. Reference numeral 22 is an electrode provided on the main plane of the ceramic varistor element 21, and 23a and 23b are lead terminals. Reference numeral 24 is a conductive adhesive that electrically connects the electrode 22 and the lead terminals 23a and 23b. Reference numeral 25 is a molding resin made of epoxy insulating resin which covers the entire varistor, and 26 is a groove provided on the upper surface of the molding resin 25 along the outer periphery of the lead terminal 23b. The operation of the varistor configured as above will be described with reference to the drawings.
【0009】セラミックバリスタ素子21は定常状態で
は良好な絶縁体であるが、セラミックバリスタ素子21
自身が耐え得ないような異常高電圧が印加されると、セ
ラミックバリスタ素子21が貫通破壊をおこす。この
際、破壊したセラミックバリスタ素子21が高温にな
り、組成の一部が蒸発する。これに伴って高温、高圧の
ガスが発生する。このガスの圧力はモールド樹脂25を
破壊するように働き機械的強度の弱い溝26の部分に沿
って亀裂を生じ、せん断させ、そのガスの圧力によりリ
ード端子23bと共にセラミックバリスタ素子21上面
のモールド樹脂25が、蓋が開くように剥離し、電気的
に開放状態となる。図4、図5に本実施形態におけるリ
ード端子23bと共に、上面のモールド樹脂25が蓋が
開くように剥離した状態を示す。図6に本実施例に用い
たリード端子23a,23bの上面図、図7に同じく側
面図を示す。本実施例におけるチップ型バリスタの貫通
破壊後の抵抗値と従来例のチップ型バリスタの貫通破壊
後の抵抗値を(表1)に比較して示している。なおセラ
ミックバリスタ素子21には最大許容電圧の2倍の電圧
を印加し過電圧破壊を起こさせたものである。Although the ceramic varistor element 21 is a good insulator in the steady state, the ceramic varistor element 21 is
When an abnormally high voltage that cannot be endured by itself is applied, the ceramic varistor element 21 causes breakthrough. At this time, the destroyed ceramic varistor element 21 becomes high in temperature and a part of the composition evaporates. Along with this, high temperature and high pressure gas is generated. The pressure of this gas acts to destroy the mold resin 25, causes a crack along the groove 26 having weak mechanical strength, and causes shearing, and the pressure of the gas causes the mold resin on the upper surface of the ceramic varistor element 21 together with the lead terminal 23b. 25 is peeled off so that the lid is opened, and is electrically opened. FIG. 4 and FIG. 5 show a state in which the mold resin 25 on the upper surface is peeled off so that the lid is opened together with the lead terminal 23b in the present embodiment. FIG. 6 is a top view of the lead terminals 23a and 23b used in this embodiment, and FIG. 7 is a side view of the same. The resistance value of the chip-type varistor in this example after the through-breakage is compared with the resistance value of the conventional chip-type varistor after the break-through in (Table 1). It should be noted that the ceramic varistor element 21 is applied with a voltage twice the maximum allowable voltage to cause overvoltage breakdown.
【0010】[0010]
【表1】 [Table 1]
【0011】この(表1)から明らかなように、本発明
によるチップ型バリスタは破壊後の抵抗値が開放状態に
なる事がわかる。以上のように本実施形態は、リード端
子23bの外周に沿ってモールド樹脂25の上部表面に
溝26を設けたものであり、セラミックバリスタ素子2
1が貫通破壊した際のチップ型バリスタの故障モードを
開放状態にすることができる。As is clear from this (Table 1), it can be seen that the chip-type varistor according to the present invention has an open resistance value after breakage. As described above, in the present embodiment, the groove 26 is provided on the upper surface of the mold resin 25 along the outer periphery of the lead terminal 23b.
The failure mode of the chip type varistor when 1 is pierced and broken can be set to an open state.
【0012】(実施形態2)図8〜図10において、3
1はセラミックバリスタ素子、32は電極、33a,3
3bはリード端子、34は導電性接着剤、35はモール
ド樹脂、36はモールド樹脂35の上部表面の溝であ
り、実施形態1と同様な構成である。実施形態1と異な
るのは、リード端子33bにセラミックバリスタ素子3
1が貫通破壊したときに離れやすいようにバネ性を持た
せた点である。図13に本実施例に用いたリード端子3
3a,33bの上面図、図14に同じく側面図を示し
た。本実施例に用いたリード端子33bの途中より45
°の角度に曲げ加工しているので、これをセラミックバ
リスタ素子31側へ押圧してモールド樹脂35で覆うと
バネ性が発揮される。図11、図12は本実施形態にお
ける、セラミックバリスタ素子31が貫通破壊したと
き、リード端子33bと共に、セラミックバリスタ素子
31電極32上面のモールド樹脂35が溝36に沿って
蓋が開くように剥離した状態図を示す。(Second Embodiment) In FIGS. 8 to 10, 3
1 is a ceramic varistor element, 32 is an electrode, 33a, 3
3b is a lead terminal, 34 is a conductive adhesive, 35 is a mold resin, and 36 is a groove on the upper surface of the mold resin 35, which has the same configuration as in the first embodiment. The difference from the first embodiment is that the ceramic varistor element 3 is connected to the lead terminal 33b.
This is the point that 1 has a spring property so that it is easy to separate when it breaks through. FIG. 13 shows the lead terminal 3 used in this embodiment.
3a and 33b are top views and FIG. 14 is a side view thereof. 45 from the middle of the lead terminal 33b used in this embodiment.
Since it is bent at an angle of °, when it is pressed toward the ceramic varistor element 31 side and covered with the mold resin 35, spring properties are exhibited. 11 and 12, when the ceramic varistor element 31 in this embodiment is pierced and broken, the mold resin 35 on the upper surface of the electrode 32 of the ceramic varistor element 31 is peeled off along with the groove 36 so that the lid opens along with the lead terminal 33b. A state diagram is shown.
【0013】以上のように構成されたチップ型バリスタ
の動作について、図を用いて説明する。セラミックバリ
スタ素子31の貫通破壊で、リード端子33bがモール
ド樹脂35をせん断するまでのプロセスは、実施形態1
と同様であるが本実施形態2に用いているリード端子3
3bはバネ性を持っているため、ガスの圧力により剥離
したリード端子33bの開く角度が大きく、実施形態1
の場合より、より確実に開放状態にすることができるこ
とを示している。The operation of the chip type varistor constructed as described above will be described with reference to the drawings. The process until the lead terminal 33b shears the mold resin 35 due to the through breakage of the ceramic varistor element 31 is the same as in the first embodiment.
The same as the lead terminal 3 used in the second embodiment.
Since 3b has a spring property, the opening angle of the lead terminal 33b peeled off due to the pressure of gas is large.
It is shown that the open state can be achieved more reliably than in the case of.
【0014】本実施形態2におけるチップ型バリスタの
貫通破壊後の抵抗値と、従来例のチップ型バリスタの貫
通破壊後の抵抗値を(表1)に示している。この(表
1)から明らかなように、実施形態2によるチップ型バ
リスタは、使用するリード端子33bにばね性をもたせ
ることによりセラミックバリスタ素子31の貫通破壊
後、チップ型バリスタの故障モードをより確実に開放状
態にすることができることが分かる。Table 1 shows the resistance value of the chip type varistor in the second embodiment after the breakthrough and the resistance value of the conventional chip type varistor after the breakthrough. As is clear from this (Table 1), the chip-type varistor according to the second embodiment is more reliable in the failure mode of the chip-type varistor after the ceramic varistor element 31 is pierced by breaking the lead terminal 33b used. You can see that it can be opened.
【0015】[0015]
【発明の効果】以上のように、本発明は故障時に確実に
開放するチップ型バリスタの提供が可能になる。As described above, according to the present invention, it is possible to provide a chip type varistor that is reliably opened when a failure occurs.
【図1】本発明の実施形態1によるチップ型バリスタの
上面図FIG. 1 is a top view of a chip type varistor according to a first embodiment of the present invention.
【図2】同実施形態1によるチップ型バリスタの上面透
視図FIG. 2 is a top perspective view of the chip varistor according to the first embodiment.
【図3】図1のA−A断面図FIG. 3 is a sectional view taken along line AA of FIG. 1;
【図4】同実施形態1によるチップ型バリスタの破壊状
態を示す上面図FIG. 4 is a top view showing a broken state of the chip type varistor according to the first embodiment.
【図5】図4のA−A断面図FIG. 5 is a sectional view taken along line AA of FIG. 4;
【図6】同実施形態1によるリード端子の上面図FIG. 6 is a top view of the lead terminal according to the first embodiment.
【図7】同実施形態1によるリード端子の側面図FIG. 7 is a side view of the lead terminal according to the first embodiment.
【図8】本発明の実施形態2によるチップ型バリスタの
上面図FIG. 8 is a top view of a chip type varistor according to Embodiment 2 of the present invention.
【図9】同実施形態2によるチップ型バリスタの上面透
視図FIG. 9 is a top perspective view of the chip type varistor according to the second embodiment.
【図10】図8のA−A断面図10 is a cross-sectional view taken along the line AA of FIG.
【図11】同実施形態2によるチップ型バリスタの破壊
状態を示す上面図FIG. 11 is a top view showing a broken state of the chip type varistor according to the second embodiment.
【図12】図11のA−A断面図FIG. 12 is a sectional view taken along line AA of FIG. 11;
【図13】同実施形態2によるリード端子の上面図FIG. 13 is a top view of the lead terminal according to the second embodiment.
【図14】同実施形態2によるリード端子の側面図FIG. 14 is a side view of the lead terminal according to the second embodiment.
【図15】従来例のチップ型バリスタの上面透視図FIG. 15 is a top perspective view of a conventional chip-type varistor.
【図16】図15のA−A断面図16 is a cross-sectional view taken along the line AA of FIG.
21 セラミックバリスタ素子 22 電極 23b リード端子 25 モールド樹脂 26 溝 21 Ceramic Varistor Element 22 Electrode 23b Lead Terminal 25 Mold Resin 26 Groove
Claims (2)
極と、前記電極に電気的に接続したリード端子と、前記
バリスタ素子と電極およびリード端子の少なくとも電極
との接続部を覆った樹脂モールドとを備え、前記リード
端子外周に沿ってモールド樹脂の上部表面に溝を設けた
ことを特徴とするチップ型バリスタ。1. A resin mold which covers a varistor element, an electrode provided on the main plane, a lead terminal electrically connected to the electrode, and a connection portion between the varistor element and the electrode and at least the electrode of the lead terminal. And a groove provided on the upper surface of the mold resin along the outer periphery of the lead terminal.
項1記載のチップ型バリスタ。2. The chip type varistor according to claim 1, wherein the lead terminal has a spring property.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27880195A JP3381485B2 (en) | 1995-10-26 | 1995-10-26 | Chip type varistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27880195A JP3381485B2 (en) | 1995-10-26 | 1995-10-26 | Chip type varistor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH09129404A true JPH09129404A (en) | 1997-05-16 |
JP3381485B2 JP3381485B2 (en) | 2003-02-24 |
Family
ID=17602370
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP27880195A Expired - Fee Related JP3381485B2 (en) | 1995-10-26 | 1995-10-26 | Chip type varistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3381485B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7164341B2 (en) | 2000-10-24 | 2007-01-16 | Murata Manufacturing Co., Ltd. | Surface-mountable PTC thermistor and mounting method thereof |
CN104733143A (en) * | 2013-12-18 | 2015-06-24 | 孙巍巍 | Piezoresistor based on novel pin design method |
CN107768052A (en) * | 2017-10-20 | 2018-03-06 | 惠州市欣旭电子有限公司 | A kind of SMD piezo-resistance manufacture craft and SMD piezo-resistance |
-
1995
- 1995-10-26 JP JP27880195A patent/JP3381485B2/en not_active Expired - Fee Related
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7164341B2 (en) | 2000-10-24 | 2007-01-16 | Murata Manufacturing Co., Ltd. | Surface-mountable PTC thermistor and mounting method thereof |
CN104733143A (en) * | 2013-12-18 | 2015-06-24 | 孙巍巍 | Piezoresistor based on novel pin design method |
CN107768052A (en) * | 2017-10-20 | 2018-03-06 | 惠州市欣旭电子有限公司 | A kind of SMD piezo-resistance manufacture craft and SMD piezo-resistance |
Also Published As
Publication number | Publication date |
---|---|
JP3381485B2 (en) | 2003-02-24 |
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