JPH09128995A - Partial memory single article acquisition method, semiconductor memory, memory module and compute system using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the areas other than the specified area of an external address usable by switching connection between the external address and an internal address of a partial memory with a partial defect based on specified logic. SOLUTION: An external address circuit 2 receives an address signal input to select a required memory cell of a memory cell array 1 through a connection switch circuit 6, an internal address circuit 3 and a decoder 4. A switch instruction circuit 5 selects a proper pattern among plural prescribed switch logic patterns of external/internal address by cutting a fuse to instruct to the connection switch circuit 6. For instance, by driving a physical defective address existing discretely into the area of the farthest address counting from '00' on a logical address, that is, (an upper part area), remaining addresses are used as the continuously accessible areas. At this time, a free address control circuit 7 makes a chip into a non-selection state when the upper part area is accessed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a defect repair technique for a partial memory, and more particularly, it repairs a partial memory having some defects which are discrete or continuous as a result of a probe inspection (P inspection) and is made into an upper region, for example. By collecting those that move only 12 Mbits from the head of 16 Mbit regular products and making a 12 MB memory module, you can use other areas except a specific area without any practical problems or burst avoidance method Partial memory individual product acquisition method and semiconductor memory suitable for use as a memory for audio or image without causing a problem with transient bit defects, and a memory module and computer system using the same Related to effective technology.

Regarding the above-mentioned upper area formation, a physical address having a memory defect is driven into an area which is easy to use as a memory with a logical address by rearranging an internal address, for example, an address farthest from the logical address 00. In order to use the defective memory practically without any problem, driving to this specific address is called "upper area conversion".

Regarding the burst avoidance method,
Use physical addresses with memory defects for audio and image by rearranging logical addresses to avoid burst failures that are not a problem, so that temporary bit failures can be used without problems In this case, this is called a "burst avoidance method".

[0004]

2. Description of the Related Art For example, according to a study by the inventor, regarding a semiconductor memory which is judged to be defective in the P inspection, it is considered that the defect repair of this semiconductor memory is performed as follows. To be

(1). As a result of defect repair of a semiconductor memory, a product in which all bits do not operate is defective.

(2) Regarding the product which has become defective in the above (1), whether the defective location is half the address space, I
/ O belongs to a specific bit, and the former is called an address partial and the latter is called a bit partial.
Sold as a memory module. For example, a DRAM module using address partials and a DRAM module using bit partials manufactured by Hitachi are listed.

(3). LSIs that are defective in burst due to line defects or the like are discarded.

As described above, the partial memory is relieved as a memory module by address partial or bit partial.

[0009]

By the way, it is considered that the defect repair technique for the partial memory as described above is used as follows, for example.

(1). In the case of address partial, for example, only half of the total number of bits is used.

(2). Even a bit partial uses only 75% of 3/4 at most.

(3) In the case of commercializing a partial memory from a memory having a .times.4 bit structure, for example, there are at least two types of address partials and at least four types of bit partials, which increases the product management cost. It is necessary to prepare a plurality of module substrates incorporating different patterns.

(4) For example, one current idea of memory cost calculation is to calculate the cost by the number of normally operating bits excluding the non-operating bits. For this reason,
If the address that cannot be accessed in the partial memory is not physically determined, a high cost will be set even though it is a partial product. For this reason, neither a module that employs a method of limiting the number of operating bits on the module nor a single partial product can be shipped (if this can be set as an area where a single product cannot operate, it can be sold with appropriate pricing).

(5). If there is a line defect, physical address = logical address, and external address = internal address makes it difficult to avoid a burst defect.

Therefore, an object of the present invention is to remedy a partial defect resulting from the P inspection, in particular, a partial memory in which this partial defect is discrete, and to use the other region except the specific region by making it an upper region. A method for obtaining a partial memory and a semiconductor memory, which can be used without problems.
Another object is to provide a memory module and a computer system using the same.

Another object of the present invention is to remedy a partial memory having a partial defect in a continuous manner so that a temporary bit defect can be used without any problem by a burst avoidance method. (EN) Provided are a partial memory single item acquiring method and a semiconductor memory, a memory module using the same, and a computer system.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0018]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, according to the partial memory single item acquiring method and the semiconductor memory of the present invention, the connection between the external address and the internal address of the partial memory which is determined to be partially defective as a result of the P inspection is switched, and the partial memory single item is selected. Is repaired so that it can be used at a logical address.

In particular, when the defective physical addresses are discrete, the defective physical addresses of the memory are logical addresses that are easy to use as a memory by rearranging the internal addresses by changing the upper area, for example, logical 00. The semiconductor memory has a built-in address switching means for driving the address farthest from the address. As a result, the areas other than the upper area can be used, and the memory, which has been conventionally defective, can be used without any practical problems. Furthermore, the upper area of the driven-in address is empty as a logical address and can be an inaccessible area.

On the other hand, when the defective physical addresses are continuous, the semiconductor memory is provided with an address switching means for replacing the defective physical addresses of the memory in the order of avoiding the burst failure by rearranging the logical addresses by the burst avoidance method. It is designed to be built into. As a result, it is possible to use it for a temporary bit defect and use it for audio and images without causing a problem.

As a result, a partial memory having a partial defect resulting from the P inspection, which is discrete or continuous, can be repaired so that it can be used as a memory without any practical problems, or can be used as an audio or image memory. In addition, it is possible to improve the versatility by increasing the application to memory modules, computer systems, and the like.

[0023]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a schematic block diagram showing a main part of a semiconductor memory according to a first embodiment of the present invention.
2 is a circuit diagram showing an example of a switching instruction circuit in the first embodiment, FIG. 3 is a circuit diagram showing an example of a connection switching circuit, FIG. 4 is a circuit diagram showing an example of an empty address control circuit,
FIG. 5 is an explanatory view showing the outline of the upper area formation, and FIG. 6 is an explanatory view showing the upper area formation method.

First, the main structure of the semiconductor memory according to the first embodiment will be described with reference to FIG.

In the semiconductor memory of the first embodiment, for example, the connection between the external address and the internal address of the partial memory which is determined to be partially defective as a result of the P test is switched, and the partial memory is repaired separately. A memory array 1 having a plurality of memory cells that can be used at a logical address, an external address circuit 2 that selects an arbitrary memory cell in the memory array 1, an internal address circuit 3 and a decoder 4, and defect repair. It is composed of a switching instruction circuit 5, a connection switching circuit 6, an empty address control circuit 7, and a control signal generation circuit 8 which are address switching means for. The decoder 4 includes a Y system decoder and an X system decoder.

The basic operation of this DRAM is that an X-system address is designated by an X-system decoder 4 from an external address circuit 2 to which an address signal is input, a connection switching circuit 6 and an internal address circuit 3, while a Y-system address is specified. As for the above, an arbitrary memory cell of the memory array 1 is selected by the designation by the Y-system decoder 4 via the connection switching circuit 6 and the internal address circuit 3. And
With respect to the selected memory cell, the data of the memory cell is output as output data from the output terminal at the time of reading, and the input data from the input terminal is written to the memory cell at the time of writing.

The switching instructing circuit 5 is a circuit for instructing address replacement to a memory which is judged to be non-defective in all bits at the P detection stage and further judged to be able to be formed into an upper region by the P detection tester. For example, as shown in FIG. 2, some sets, in the present embodiment, three sets of circuits corresponding to the three sets of rearrangement signals (set 1, set 2, set 3) are provided, each of which has a power supply potential. And resistors F1 to R3 and fuses F1 to F3 that are connected in series between the inverters IV1 to IV3 and the connection nodes.

In the switching instruction circuit 5, ON
Alternatively, the fuses F1 to F3 of the circuits of the respective groups are cut or left untouched in accordance with the rearrangement signal to be turned off. For example, by cutting the fuses F2 and F3, the output of the inverter IV1 is High and the output of the inverter IV2 is high.
The output of 3 becomes Low, and the set 1 is used. Alternatively, a method such as writing the rewriting table in a nonvolatile ROM instead of the fuse may be used.

The connection switching circuit 6 is a circuit for receiving the signal from the switching instruction circuit 5 and switching the connection between the external address and the internal address. For example, as shown in FIG. Between the four sets of inverters IV4 to IV7 and the outputs of the respective inverters IV4 to IV7 and the internal address circuit 3 for the internal address signal, the four MOS transistors Q1 to Q1 corresponding to the rearrangement signal. It is composed of Q12. Although the transfer circuit is configured here, it is not particularly limited, such as forming a logic.

In this connection switching circuit 6, the circuit connected to the corresponding rearrangement signal is turned on or off by the signal from the switching instruction circuit 5, and, for example, O
The external address and the internal address are connected by N. Note that this causes complication of an arbitrary switching signal, so that, for example, a method of previously patterning a specific pattern is used.

The empty address control circuit 7 automatically deselects the chip when the upper area is accessed,
Alternatively, as shown in FIG. 4, a NAND gate G1 to which an internal address signal is input, and an inverter IV for this output signal are circuits for preventing output.
And 8. By this empty address control circuit 7, the upper area is empty as a logical address and cannot be accessed.

Next, with regard to the operation of the first embodiment, the connection between the external address and the internal address is specifically switched, and the partial memory is relieved by the upper area so that the partial memory can be used at the logical address. A method for obtaining a single item will be described.

That is, as shown in FIG. 5, by forming an upper area, a physical address having a memory defect is changed to an area which is easy to use as a memory with a logical address by rearranging an internal address, for example, an address farthest from the logical address 00. It is possible to use the memory, which has been defective in the past, without any problems in practical use. further,
The upper area of the driven-in address can be an area which is empty and cannot be accessed as a logical address.

Here, as a simple example, FIG.
16-bit example is shown. In this example, when it is determined as a partial defect that the physical addresses of 6h, 7h, and Fh are defective as a result of P inspection, this defect is an intermittent address, and the LSI cannot be used as it is. So A
If 1 is replaced with A3, the defect is a logical address and C
It can be switched to h, Dh, Fh.

That is, the external addresses A1 and A3 are
The circuit of the set 2 is used to replace the internal addresses a3 and a1, the fuse F2 of the circuit corresponding to the set 2 is not cut by the switching instruction circuit 5 of FIG. 2, and the output of the inverter IV2 is set to the high state. As for the other circuits, the fuses F1 and F3 are blown and the outputs of the inverters IV1 and IV3 are low, and the circuits are not used.

In the connection switching circuit 6 of FIG. 3, only the MOS transistors Q5 to Q8 connected to the set 2 are in the operating state, and the correspondence between the external address and the internal address remains A0 at A0 and A1 at a3. Switch to A
2 remains a2 and A3 is switched to a1. As a result, the external address A1 can be switched to the internal address a3, and the external address A3 can be switched to the internal address a1.

Therefore, the defective addresses existing discretely before the switching can be driven into the upper region of Ch to Fh of the last ¼ of the 16-bit address space in total. By doing so, it is possible to use the space from address 0h to address Bh as a continuously accessible space that does not include any defect.

Here, according to the above-described concept of calculating the memory cost, the number of operating bits excluding the number of defective bits is counted as the operating area, and the cost is set. In general, partials are limited in usage to users, and are often priced lower than genuine products that are perfectly good. However, with this idea, the setting is very high.

For example, a 16 Mbit memory is 1000
Even if there is a bit defect, the price will be 99.994% of the genuine product. In order to prevent such a situation, the memory thus switched has a built-in circuit that automatically brings the chip into a non-selected state when the upper region is accessed.

That is, by the empty address control circuit 7 as shown in FIG. 4, for example, in the above-mentioned example, A3 becomes High.
If h and A2 are also accessed in the High area,
CE (Chip Enabl
By controlling e) and OE (Out-put Enable), the LSI can be deselected or output can be prevented.

Therefore, according to the DRAM of the first embodiment, by incorporating the switching instruction circuit 5, the connection switching circuit 6, and the empty address control circuit 7 as the address switching means, the defective physical addresses are discrete. In this case, the switching instruction circuit 5 and the connection switching circuit 6 can drive the defective physical address of the memory into an area that is easy to use as a memory with a logical address by rearranging the internal address by changing the upper area. Other areas except for can be used without any practical problems.

Further, the upper area of the driven-in address can not be accessed by the empty address control circuit 7 because the LSI can be deselected or the output can be prevented from being output. It can be a region.

(Second Embodiment) FIG. 7 is an explanatory view showing an outline of a burst avoidance method in a semiconductor memory according to a second embodiment of the present invention, and FIG. 8 is an explanatory view showing a method of the burst avoidance method.

The semiconductor memory according to the second embodiment switches the connection between the external address and the internal address of the partial memory, which is determined to be partially defective as a result of the P test, as in the first embodiment. The partial memory is a DRAM which is salvaged and can be used at a logical address. The difference from the first embodiment is that it is judged that the P-test cannot be a completely good product, and the P-test tester can avoid the burst. This is the point of instructing the address replacement to the memory which is determined to be.

That is, in the switching instruction circuit and the connection switching circuit, which are the address switching means of the second embodiment, as shown in FIG. 7, a continuous physical address having a memory defect is assigned to a logical address by a burst avoidance method. By changing the order of avoiding the burst failure by rearranging, it is possible to use it for audio and image so that it does not become a problem.

For example, in recent DRAMs, in order to reduce the resistance and capacitance of word lines and data lines, a plural mat system is usually adopted, and in the present embodiment, a mat system by four divisions as shown in FIG. 8 is adopted. . On this one mat
If there is a thick line defect, it becomes a burst defect. When such a defect is used for audio, it cannot be used because it includes a continuous defect due to interleaving and cannot be corrected.

Therefore, in such a case, similar to the first embodiment, the switching instruction circuit and the connection switching circuit, for example, transfer A9 to A1 and A8 to A0.
That is, the external address A9 is switched to the internal address a1, and the external address A8 is switched to the internal address a0. As a result, a matte scan is performed for reading from an external address, and it is possible to prevent only one defect from being included in address 4 and not to cause a burst defect.

Therefore, according to the DRAM of the second embodiment, when the defective physical addresses are continuous, the defective physical addresses of the memory are burst defective by rearranging the logical addresses by the burst avoidance method. Since they can be replaced in the order of avoidance, they can be used for transient bit defects and can be used for audio and images without causing a problem.

Although the invention made by the present inventor has been specifically described based on the first and second embodiments of the present invention, the present invention is not limited to the above embodiments and does not depart from the gist of the invention. It goes without saying that various changes can be made within the range.

For example, the DRAM of the above-mentioned embodiment is not limited to the case of being used in a semiconductor memory unit,
A plurality of memories are mounted on a memory board and configured to be connectable to the outside through input / output terminals or connectors.
It is widely used as a memory module such as a RAM module, and also as a storage device of various systems such as a computer system, a digital still camera system, and an automobile system. As an example, a computer system will be described with reference to FIG.

In FIG. 9, this computer system includes a bus, a central processing unit CPU, a peripheral device control unit, a DRAM of the present invention as a main memory and its control unit,
SRAM as backup memory, backup parity, its control unit, and RO storing programs
M, display system, etc. The peripheral device control unit is connected to an external storage device, a keyboard KB and the like.

The display system is a video RAM (VRAM).
The storage information in the VRAM is displayed by being connected to a display as an output device. Further, a power supply unit for supplying power to the internal circuit of the computer system is provided.
The central processing unit CPU controls the operation timing of each memory by forming a signal for controlling each memory.

Here, an example in which the present invention is applied to a DRAM as a main memory has been described. However, when the VRAM of the display system is a multiport VRAM, it may be applied to a random access section of the VRAM. It is possible. As described above, the memory module such as the DRAM of the present invention can be widely applied as a main memory of a computer system.

[0055]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). For a memory that has discrete defective bits and cannot be used for any purpose, by rearranging the internal address by changing the upper area to drive the defect only to the upper area of the address space, Since it is possible to use the area other than the area, it is possible to obtain a practical memory product.

(2). When an address area that should not be used in the upper area is accessed, it is possible to automatically deactivate the LSI so that no data is output. Is equivalent to having no memory, and the number of operating bits is physically regulated inside the LSI. Therefore, the number of operating bits corresponding to the concept of memory cost calculation can be reduced.

(3) For a memory which has consecutive defective bits in the physical address and cannot be used for such a purpose due to a burst defect such as voice or image, the internal address and the external address are appropriately exchanged by the burst avoidance method. As a result, a memory including defects that are not continuous in physical address can be provided, and thus it can be used as a memory product for audio and image.

(4) By the above (1) to (3), the partial memory having some defects discretely or continuously is relieved,
It can be used as a memory without any practical problems, or it can be used in specific fields such as audio and images,
Further, it is possible to improve the versatility by increasing the application to a memory module configured using this memory, a computer system, or the like.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing a main part of a semiconductor memory according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a switching instruction circuit according to the first embodiment.

FIG. 3 is a circuit diagram showing an example of a connection switching circuit according to the first embodiment.

FIG. 4 is a circuit diagram showing an example of an empty address control circuit according to the first embodiment.

FIG. 5 is an explanatory diagram showing an outline of forming an upper region in the first embodiment.

FIG. 6 is an explanatory diagram showing a method of forming an upper region in the first embodiment.

FIG. 7 is an explanatory diagram showing an outline of a burst avoidance method in the semiconductor memory according to the second embodiment of the present invention.

FIG. 8 is an explanatory diagram showing a method of a burst avoidance method according to the second embodiment.

FIG. 9 is a functional block diagram showing a computer system using the semiconductor memory according to the embodiment.

[Explanation of symbols]

 1 memory array 2 external address circuit 3 internal address circuit 4 decoder 5 switching instruction circuit (address switching means) 6 connection switching circuit (address switching means) 7 empty address control circuit (address switching means) 8 control signal generation circuits R1 to R3 resistors F1 to F3 fuses IV1 to IV8 inverters Q1 to Q12 MOS transistors G1 NAND gate

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshio Kanno 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. (72) Inventor Yoichi Matsuno Kamimizumoto-cho, Kodaira-shi, Tokyo 5-20-1 Hitachi Ltd. Semiconductor Division

Claims (9)

[Claims] 1. The presence / absence of a defect is judged by inspection, and as a result, the connection between the external address and the internal address of the partial memory which is judged to be partially defective is switched, and a single piece of the partial memory is relieved to logic. Partial memory single item acquisition method characterized by enabling use at an address. 2. The partial memory single item acquiring method according to claim 1, wherein a physical address having a defect in the partial memory is extracted, and when the extracted physical address having a defect is discrete, A partial memory single product acquisition method characterized in that a defective physical address is relocated to an easy-to-use area with a logical address by rearranging the internal address. 3. The partial memory single item acquiring method according to claim 2, wherein the driven-in physical address area is
Partial memory single item acquisition method characterized in that the logical address is an empty and inaccessible area. 4. The partial memory single item acquiring method according to claim 1, wherein a physical address having a defect in the partial memory is extracted, and when the extracted physical addresses having the defect are continuous, A partial memory single-item acquisition method characterized in that defective physical addresses are replaced in the order in which burst failures are avoided by rearranging logical addresses. 5. A semiconductor memory that relieves a partial memory in which some defects are discriminated to be discrete as a result of inspection, and a physical address having a defect in the partial memory is converted into a logical address by rearranging an internal address. A semiconductor memory that has a built-in address switching means that drives into an easy-to-use area, and that can use other areas excluding the physical address that was driven in without any practical problems. 6. A semiconductor memory that relieves a partial memory that is determined to be partially defective continuously as a result of the inspection, and a defective physical address of the partial memory is rearranged with a logical address to cause a burst defect. A semiconductor memory having a built-in address switching means for switching in an order of avoidance so that a temporary bit failure can be used without causing a problem by this switching. 7. The semiconductor memory according to claim 5, wherein the semiconductor memory is a DRAM. 8. A memory module using the semiconductor memory according to claim 5, 6 or 7, wherein the semiconductor memory is mounted on a memory board and is connectable to the outside through an input / output terminal or a connector. A memory module characterized by being provided. 9. A computer system using the semiconductor memory according to claim 5, 6 or 7, wherein at least a central processing unit and its peripheral circuits are provided in addition to the semiconductor memory. .