JPH09128875A - Device and method for recording data, device and method for preventing illegal copy and data recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a digital data from being illegally copied. SOLUTION: A data B as a part of a bit stream and a key K stored in a memory 31 are calculated by a calculation circuit 32 to obtain a 1st block and a 2nd block in position. The LSBs of DC differentials of the 1st block and the 2nd block specified by the calculation circuit 32 are read out by a detection circuit 33, and are stored in a memory 34. Whether or not the two stored values in the memory 34 are coincident with each other is decided by a decision circuit 38, and a result of the decision is outputted to a control circuit 39. Upon noncoincidence of the two values, 'the bit stream is due to copy' is displayed on a display device 40, and simultaneously, recording operation of a recording device 37 is inhibited.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data recording device and method, an illegal copy protection device and method, and a data recording medium, and more particularly to preventing illegal copying of a disc on which digital data is recorded. The present invention relates to a data recording device and method, an unauthorized copy protection device and method, and a data recording medium.

[0002]

2. Description of the Related Art Recently, video tape recorders have become popular.
It has become possible to record a broadcast program on a video tape and enjoy the program at any timing and any number of times. The number of shops that rent video tapes has increased, and you can enjoy and rent video tapes. Various proposals have been made to prevent a large amount of illegally copied rental video tapes.

Further, recently, apparatuses for digitally recording video data on a disk or tape are becoming popular. In the case of analog video tape, since the video signal is recorded and reproduced in analog fashion, the image quality deteriorates when copying is repeated multiple times.
It is practically difficult to repeat the process of further copying.

On the other hand, in a digital video disc, for example, since video data is digitally recorded on the disc, even if the process of copying from an illegally copied disc to another disc is repeated. In principle, the image quality hardly deteriorates.
Therefore, preventing unauthorized copying of digital video discs is far more important than preventing unauthorized copying of analog video tapes.

[0005]

For example, in a conventional analog video tape recorder, when a video signal is copied, a flag is recorded in a vertical blanking interval and the video signal in which the flag is recorded is copied. Prohibits copying, for example by prohibiting copying.

However, in most of the devices that digitally record a video signal, the signal in the vertical blanking interval does not form a substantial image, and therefore is often not recorded on the recording medium. As a result, this method cannot reliably prevent unauthorized copying.

The present invention has been made in view of such a situation, and it is possible to reliably prevent illegal copying.

[0008]

According to a first aspect of the present invention, there is provided a data recording apparatus for recording recording data on a recording medium, the recording method including an orthogonal transform coefficient converted into a variable length code and a fixed length code. Of a bitstream of data,
According to the standard, a designation means for designating a predetermined one out of fixed length codes, and a writing means for writing key data for preventing illegal copy to at least a part of the fixed length code designated by the designating means And is provided.

A data recording method according to a seventh aspect is a data recording method for recording recording data on a recording medium,
The specified fixed length is specified from the code that is always the fixed length code according to the standard of the bit stream of the recording data including the orthogonal transform coefficient converted into the variable length code and the fixed length code. Key data for preventing illegal copying is written in at least a part of the code.

The illegal copy protection device according to claim 8 is
Among the orthogonal transform coefficients converted from the variable length code and the fixed length code from the bit stream of the input recording data, the key data of the illegal copy protection written in the code that is always the fixed length code according to the standard is always used. It is characterized by comprising a detecting means for detecting and a generating means for generating a display signal for displaying the detection result of the detecting means.

The illegal copy protection method according to claim 9 is
Among the orthogonal transform coefficients converted from the variable length code and the fixed length code from the bit stream of the input recording data, the key data of the illegal copy protection written in the code that is always the fixed length code according to the standard is always used. It is characterized by detecting and generating a display signal for displaying the detection result.

A data recording medium according to a tenth aspect is a data recording medium in which an orthogonal transformation code is converted into a variable length code and a fixed length code and recorded as recording data.
It is characterized in that key data for preventing illegal copying is always written in a code that is a fixed length code.

According to another aspect of the data recording apparatus of the present invention, the designating means includes a bit stream of recording data including orthogonal transform coefficients converted into a variable length code and a fixed length code,
According to the standard, a predetermined code is always designated from the fixed-length codes, and the writing means writes the illegal copy prevention key data in at least a part of the fixed-length code designated by the designating means.

According to a seventh aspect of the data recording method of the present invention, a bit stream of recording data including an orthogonal transform coefficient converted into a variable length code and a fixed length code is coded as a fixed length code according to the standard. A predetermined one is designated from the inside, and the key data for preventing illegal copy is written in at least a part of the designated fixed-length code.

In the illegal copy preventing apparatus according to the present invention, the detecting means is one of the orthogonal transform coefficients converted from the bit stream of the input recording data into the variable length code and the fixed length code, according to the standard. Key data for preventing illegal copy written in a code that is a fixed-length code is always detected, and the generation means generates a display signal for displaying the detection result of the detection means.

In the illegal copy prevention method according to the ninth aspect, among the orthogonal transform coefficients converted from the bit stream of the input recording data into the variable length code and the fixed length code, the fixed length is always fixed according to the standard. Key data for preventing illegal copy written in the code is detected, and a display signal for displaying the detection result is generated.

In the data recording medium according to the tenth aspect of the present invention, the key data for preventing illegal copying is always written in the code which is the fixed length code according to the standard.

[0018]

1 shows the principle of recording key data for preventing illegal copy according to the present invention. As shown in the figure, GOP (Group Of Pictu)
res) is one I picture, a plurality of P pictures,
And a plurality of B pictures. FIG.
In the embodiment, one GOP is composed of 15 pictures. Further, in this embodiment, the I picture is selected from the pictures forming the GOP in order to record the key data.

Like other pictures, the I picture is composed of a plurality of slices, and each slice is composed of a predetermined number of macroblocks. In this embodiment, a predetermined one of these macroblocks is preselected.

In the case of the luminance signal (Y), the 16 × 16 pixel macro block is composed of four blocks of 8 × 8 pixels. The color difference signals Cb and Cr are expressed by a block of 8 × 8 pixels for one macro block of 16 × 16 pixels. These pixel data are DCT (Dis
It is converted into a DCT coefficient by a crate cosine transform (discrete cosine transform).

8 × 8 DCT coefficients C of one block
oeff [0] [0] to Coeff [7] [7] are
The quantization level QF is quantized in a predetermined quantization step.
[0] [0] to QF [7] [7] are converted.

Of the DCT coefficients, the upper left Coeff
[0] [0] (scan [0]) represents a direct current component (DC component), and from this direct current component, a difference value with the direct current component of the immediately preceding block as a predicted value is calculated, and the difference value is calculated. Is encoded. The remaining AC component (AC component) is sc as a DC component by zigzag scanning in the block.
Following an [0], scan [1] to scan [6
3] and then encoded.

In this embodiment, three blocks are selected for key data recording. The first block is a block for determining a bit of key data, the second block is a block in which the bit determined in the first block is set (written), and the third block Is a block for writing correction data for suppressing a mismatch caused by setting the second bit.

For example, as shown in FIG. 2, the second block is selected from macroblocks different from the first block, and the third block is the same macroblock as the second block. You can choose from a number of blocks.

Further, as shown in FIG. 3, the first to third blocks can be selected from blocks in the same macroblock.

However, the first to third blocks are selected in the order of processing the difference of the DC components.

That is, as shown in FIG. 4, the difference between the DC component of the DCT coefficient and the immediately preceding DC component is calculated, and the difference value is encoded. In the case of the luminance signal, the order of the four blocks is upper left, upper right, lower left, and lower right. Therefore, as the DC component of the upper left block,
The difference with the DC component of the lower right block of the immediately preceding macroblock is encoded, and the difference with the DC component of the upper left block is encoded as the DC component of the upper right block,
The DC component of the lower left block is encoded as the difference from the DC component of the upper right block, and the DC component of the block of the lower right block is encoded as the difference of the DC component of the lower left block.

In the case of a color difference signal, the difference from the DC component of the immediately preceding block of the corresponding color difference signal is encoded.

As described above, when the difference value of the DC component is encoded, the DC component is represented by the size and the actual value represented by the size (DC Differential). The former is a variable length code (VLC: Variable).
Length Code), and the latter is a fixed length code (FLC).

The size of the DC component is defined as shown in FIG. 5A for a luminance signal, and as shown in FIG. 5B for a color difference signal. Also, for example, when the size of the DC component is 3, DC D
The differential is defined as shown in FIG.

Therefore, for example, in the case of a luminance signal, when the size of the DC component is 3 and the actual value zz [0] is -6, the difference value is represented by 101001.

In the present embodiment, the key data is recorded by setting the LSB of the DC Differential of the second block to the same value as the LSB of the DC Differential of the first block.
For example, the DC Differential of the first block
al is 010, and DC Diff of the second block
When the erial is 101, the LSB of the DC Differential of the second block is rewritten to 0 and set to 100. In addition, the DC Differential of the first block is 001, and the DC Differential of the second block is 01.
When it is 0, the DC Diffe of the second block
In rent, the LSB is rewritten to 1 and 0
11

As a result, in the case of this embodiment, the rewriting of the DC Differential of the second block is performed as shown by the arrow in FIG. For example,
When the value is 001, when the LSB is rewritten to 0, the value is rewritten to 000 and not to 010. Further, for example, when the value is 010, the value after rewriting is 011. On the contrary, when the value is 011 the value after rewriting is 010.
In this way, only the LSB is rewritten.

Also, the DC Diffe of the second block
r LSB is the DC D of the first block
If it is originally the same as the LSB of the differential, the key data has already been recorded, so the DC Differential of the second block
The LSB of ial is left as it is.

Thus, the DC Di of the second block
differential LSB (values in the left column of FIG. 6)
Is rewritten, the actual value of the DCT coefficient (the value in the right column of FIG. 6) will increase or decrease by 1.
Then, in order to absorb the increase or decrease of the actual value of this DCT coefficient, the DC Differ of the third block is absorbed.
The value of initial is corrected.

That is, the DC Dif of the second block
When the LSB of the differential is rewritten from 0 to 1, the actual value of the DCT coefficient is increased by 1. Therefore, the DC Differential of the third block is changed.
l is rewritten so that the actual value of the DCT coefficient is reduced by 1 and the DC Difference of the second block is changed.
When the LSB of tial is rewritten from 1 to 0, DCT
Since the actual value of the coefficient has decreased by 1,
The DC Differential of the block is DC
It is rewritten so that the actual value of the T coefficient increases by one.

For example, the DC Diff of the second block
When 010 of erential is rewritten to 011
Since the actual value of the DCT coefficient is increased from -5 to -4 by 1, for example, the DC Difference of the third block
If the initial is 110, this is rewritten to 101, and the actual value of the DCT coefficient is reduced by 1 from 6 to 5. Similarly, for example, the DC of the second block
When 011 of Differential is rewritten to 010, the actual value of the DCT coefficient decreases by 1 from -4 to -5, so that, for example, DC Di of the third block
If the differential is 110, it is rewritten to 111, and the actual value of the DCT coefficient is increased by 1 from 6 to 7.

Since 1-bit key data is written in one block as described above, FIG.
As shown in FIG. 3, when the key data is composed of n bits, the DC Differential of n blocks is
Will be rewritten. However, this n
The bit key data is the DC of the selected first block.
The result is defined by the LSB of Differential, and is not prepared in advance as the data to be recorded.

Next, an example of the configuration of an apparatus for recording / reproducing key data according to such a principle will be described. FIG. 8 shows a configuration example of the encoder. This encoder manufactures a regular master (magnetic tape, magneto-optical disk, optical disk, etc.) from the original source shown in FIG.

The analog video signal is A / D converted and supplied to the frame memory 1 for storage. The video data stored in the frame memory 1 is read therefrom and supplied to the DCT circuit 3 via the subtractor 2.
The DCT circuit 3 performs DCT conversion on the input data, and then outputs the data to the quantization circuit 4. The quantization circuit 4 quantizes the input DCT coefficient.

The data output from the quantization circuit 4 is V
In addition to being supplied to the LC circuit 5, it is supplied to the inverse quantum circuit 6, inversely quantized, and supplied to the IDCT circuit 7. The IDCT circuit 7 performs inverse DCT processing on the input data, and outputs it to the motion compensation circuit 9 via the adder 8. The motion compensation circuit 9 is adapted to perform motion compensation on the input data corresponding to the motion vector, and then store the data in the prediction memory 10. The data stored in the prediction memory 10 is supplied to the subtractor 2 and subtracted from the data supplied from the frame memory 1. In addition, the adder 8 adds the data from the IDCT circuit 9.

The motion vector detection circuit 11 detects the motion vector of the data output from the frame memory 1,
The detection result is supplied to the motion compensation circuit 9.

Next, the operation will be described. In the case of an I picture, the data read from the frame memory 1 is directly supplied to the DCT circuit 3 via the adder 2. On the other hand, in the case of a P picture or a B picture, the difference from the motion prediction image stored in the prediction memory 10 is obtained by the subtractor 2, and the difference data is D
It is supplied to the CT circuit 3.

The DCT circuit 3 performs DCT conversion on the input data in block units of each macroblock and converts it into DCT coefficients Coeff [u] [v].

The quantization circuit 4 converts the DCT coefficient Coeff [u] [v] supplied from the DCT circuit 3 into a quantization level QF [u] [v]. Then, as shown in FIG. 1, this quantization level QF [u] [v] is zigzag scanned.

The inverse quantization circuit 6 inversely quantizes the data output from the quantization circuit 4. That is, the quantization circuit 4
The process opposite to the process in is performed. The data output from the inverse quantization circuit 6 is input to the IDCT circuit 7 and the inverse DC
T processed. That is, a process reverse to that in the DCT circuit 3 is performed.

The output data from the IDCT circuit 7 is added to the predicted image data supplied from the prediction memory 10 in the adder 8, and the difference data is restored to the original data.
Then, this data is input to the motion compensation circuit 9. The motion vector is input to the motion compensation circuit 9 from the motion vector detection circuit 11, and the motion compensation circuit 9 performs motion compensation of the data input from the IDCT circuit 7 in correspondence with this motion vector. Then, the data after motion compensation is supplied to the prediction memory 10 and stored therein. In this way, the motion prediction image is stored in the prediction memory 10.

On the other hand, the VLC circuit 5 converts the data of the quantization level QF [u] [v] input from the quantization circuit 4 into a variable length code. The variable-length coded data by the VLC circuit 5 is supplied to a device (not shown) as a bit stream and recorded on the master disk MD (recording medium).

As described above, the encoder basically operates similarly to the conventional case.

The data encoded by the encoder shown in FIG. 8 is recorded on the master disk MD. When a large number of replica disks (ROM disks) are manufactured from this master disk MD, the master disk MD is supplied to the formatter. The formatter manufactures a large number of discs from the provided master disc MD. FIG. 9 shows a configuration example of this formatter.

In this embodiment, the arithmetic circuit 32
The (designating means) is a predetermined key K stored in the memory 31 (a key for determining a block for recording key data, which is a key different from the n-bit key data shown in FIG. 7). Then, a part of the data B included in the bit stream obtained by reproducing the master disk MD is calculated, and the above-mentioned first and second blocks are determined from the calculation result. The detection circuit 33 is
From the block specified by the output of the arithmetic circuit 32 to DC D
It is designed to detect differentials. Then, the DC of the first block and the second block
The LSB of the Differential and the DC Differential of the third block are supplied to and stored in the memory 34. When receiving the detection signal of the second block from the detection circuit 33, the key data insertion circuit 35 (writing means) receives the DC differential LSB of the second block in the bit stream.
Is the DC of the first block supplied from the memory 34.
The process of rewriting with the LSB of Differential is executed.

The correction circuit (correction means) 36 is the detection circuit 3
When the input of the detection signal of the third block from 3 is received,
The correction data is written in the third block in the bit stream (key data is written in the second block) supplied from the key data insertion circuit 35.

The data output from the correction circuit 36 is supplied to the recording device 37. The recording device 37 records the input data on the master OD, and a large number of replica disks D are manufactured from the master OD.

The determination circuit 38 (detection means) is composed of the memory 34.
Of the first block and the second block stored in
The LSBs of the Differential are compared, and the comparison result is output to the control circuit 39 (generation means). The control circuit 39 displays a display corresponding to the determination result of the determination circuit 38 on the display device 40, and controls the recording device 37 in accordance with the determination result.

Next, with reference to the flow charts of FIGS. 10 to 12, the operation in the case of manufacturing a disc on which a bitstream is recorded will be described.

First, in step S1, the arithmetic circuit 3
2 reads the bit stream obtained by reproducing the master disk MD to a predetermined position. And step S
In 2, the arithmetic circuit 32 reads out predetermined data of the bit stream of the I picture in the GOP and sets it as B. Next, in step S3,
The arithmetic circuit 32 uses the key (K) stored in the memory 31 to obtain X according to the following equation. X = B / K

Next, in step S4, the arithmetic circuit 32
Determines the positions of the first block and the second block from the value X calculated in step S3. For example, the position of the first block can be a position represented by 4 bits on the MSB side of X, and the position of the second block can be a position represented by 4 bits on the LSB side of X.

In addition, for example, the macroblock may be designated by 6 bits on the MSB side, and the block in the macroblock may be designated as the first block by the lower 2 bits. In this case, the second block is the first
It can be a block following the block of.

Next, in step S5, the detection circuit 33
Executes the process of reading the bitstream up to the first block. Then, in step S6, the detection circuit 33 reads the DC Size of the first block. Then, the detection circuit 33, in step S7,
It is determined whether or not the DC Size is 0, and if it is not 0, the process proceeds to step S8 and DC Dif
The LSB of the peripheral is read, is output to the memory 34, and is set (stored) in the Register_1. When DC Size is 0, the process proceeds to step S9, and the detection circuit 33 outputs 0 to the memory 34 and sets it in Register_1.
That is, in this case, DC Differe
Although the value of ntial does not exist, it is assumed that the value is 0, and the subsequent processing proceeds.

Next, the detection circuit 33 continues reading the bit stream up to the second block in step S10, and in step S11.
Reads the DC Size of the second block. Then, in step S12, the detection circuit 33 causes the DC S
It is determined whether or not the size is 0. If DC Size is not 0, the process proceeds to step S13, and the detection circuit 33 determines the LS of the DC Differential of the second block.
B is output to the memory 34 and set in its Register_2.

Next, in step S14, the values stored in Register_1 and Register_2 of the memory 34 (that is, the DC Differ of the first block).
LSB of the initial and DC Dif of the second block
The detection circuit 33 determines whether or not the LSBs of the peripherals are equal. If both are the same, it means that the key data has already been written, and there is no need to change the data, so the process proceeds to step S26.

On the other hand, in step S14,
When the detection circuit 33 determines that the values of Register_1 and Register_2 are different, the process proceeds to step S15, and the key data insertion circuit 35 causes the LS of the DC Differential of the second block.
B to the value of Register_1 (D of the first block
Overwrite with LSB of C Differential. That is, the DC Difference of the second block
the LSB of the initial DC Diff of the first block
Set to the same value as the LSB of the erential.

By the above processing, the writing of the data for 1 bit of the key data is completed. By recording such key data, for example, when the DC value of one block is quantized by 8 bits, the deviation from the decoded image of the original bit stream becomes 1 deviation, and when it is quantized by 9 bits. When it becomes, the shift becomes 0.5,
In the case of 10-bit quantization, it is 0.25, and in the case of 11-bit quantization, it is 0.125. Therefore, next, a correction process is performed in order to suppress the mismatch caused by the writing of the key data. Therefore, in step S16,
The detection circuit 33 proceeds to read the bitstream up to the next block (third block), and in step S17, the detection circuit 33 determines the DC Si of the third block.
read ze.

In step S18, the detection circuit 33 determines whether or not the DC Size of the third block is 0. If DC Size is 0, then DC Dif
The correction processing cannot be performed because the peripheral does not exist. Therefore, returning to step S16, the detection circuit 33 further reads the bit stream up to the next block, sets the block as the third block, and reads the DC Size in step S17.

That is, as shown in FIG.
As the third block, DC S of the designated block
When the size is 0, the next block is selected as the third block. And the DC Si of that block
If ze is not 0, the block is selected as the third block.

When the detection circuit 33 determines in step S18 that the DC Size of the third block is not 0, the detection circuit 33 proceeds to step S19, reads the DC Differential of the third block, and stores the read value in the memory. 34 Register_3. As a result, the 3-bit value of 000 to 111 shown in the left column in FIG. 6, for example, of the third block is stored in Register_3.

Next, in step S20, the memory 34
Detection circuit 33 determines whether or not the value stored in Register_1 of 0 is 0. If the value is 0, the process proceeds to step S21, and the detection circuit 33 determines whether the value of DC Differential of the third block written in Register_3 in step S19 is equal to 2 ^ (DC Size) -1, or It is determined whether it is equal to 2 ^ (DC Size-1) -1. Here, ^ means exponentiation.

That is, since the value of Register_1 is 0 (step S20), the LSB of the DC Differential of the second block is changed from 1 to 0.
(The actual value (difference value) of the DCT coefficient is decreased by 1) (step S15). Therefore, in order to offset this decrease, 1 may be added to the LSB of the DC Differential of the third block (basically, as shown in FIG. 6, DC D
If the differential is increased by 1, the difference value of the DCT coefficient is also increased by 1.) This addition process is performed in step S22, and as shown in FIG. 6, for example, the DC Differential of the third block is
If the value of l is 111 (DC Size = 3, 2 ³ −1
= 7 = “111”) (when the value of the difference value of the DCT coefficient is 7), that value is the maximum value, and therefore the difference value cannot be set to a value higher than that.
That is, the block is not an appropriate block in executing the correction process.

Similarly, the value of Register_3 (DC Differential of the third block) is 2
When it is equal to ^ (DC Size-1) -1, that is, the value of Register_3 is 2 ^(3-1) -1 = 3 (= "0
11 ″), the value of the difference value is −4, and the value of −3, which is the value increased by 1, is not defined, so that the process of increasing the value by 1 cannot be executed. That is, this block is also unsuitable as a block for performing the correction process.

As described above, in step S21, the detection circuit 3 determines that the block is unsuitable for correction.
If it is determined in step 3, the process returns to step S16, and the detection circuit 33 selects the next block as the third block.

If it is determined in step S21 that the third block is appropriate as the block to be corrected, the process proceeds to step S22, in which the detection circuit 33 causes the Regi
1 is added to the stored value of ster_3. Then, in step S25, the correction circuit 36 sets the value of DC Differential of the third block as Regi
The value set in ster_3 is written.

On the other hand, when the detection circuit 33 determines in step S20 that the value of Register_1 is not 0 (is 1), the process proceeds to step S23, where Reg
It is determined whether the value of ister_3 is equal to 2 ^ (DC Size-1) or equal to 0.

That is, since Register_1 is 1 now, DC Difference of the second block
The LSB of the initial is rewritten from 0 to 1 (the difference value of the DCT coefficient is increased by 1). Therefore, to correct this, step S24
Then, the DC Differential of the third block
However, as shown in FIG. 6, the value of DC Differential is 4 (= 2).
^(3-1) = 2 ² = 4 = "100"), the difference value is 4
The difference value 3 is defined as
Is not specified. Similarly, DC Differen
When the tial is “000”, the difference value is specified as −7, and the difference value −8, which is one less than that, is not specified. Therefore, the block currently selected as the third block is not an appropriate block for performing the correction process. Therefore, in this case, the process returns to step S16, and the detection circuit 33 selects the next block as the third block.

When the detection circuit 33 determines in step S23 that the third block is a block that can be corrected, the process proceeds to step S24, where Reg
Decrement the value of ister_3 by 1. Then, the process proceeds to step S25, and the correction circuit 36 decrements the value of 1 by the DC Diffe of the third block.
Overwrite to rental.

Next, in step S26, the control circuit 39
Determines whether or not to continue the process of recording the key data, and if so, returns to the start and repeats the subsequent processes. By repeating this process a plurality of times, n-bit key data as shown in FIG. 7 is recorded in the block at the position defined by the key (K) stored in the memory 31.

The overwrite processing performed in step S15 is
This is performed by the key data insertion circuit 35. That is, the key data insertion circuit 35, when the detection signal indicating the second block is input from the detection circuit 33, the DC differential of the input bit stream.
The value stored in Register_1 of the memory 34 is overwritten on the LSB of al.

The correction process in step S25 is performed by the correction circuit 36. That is, the correction circuit 36 receives the DC D of the bit stream input through the key data insertion circuit 35 when the detection signal indicating the third block is input from the detection circuit 33.
register the register of the memory 34
Rewrite with the data stored in er_3.

The writing of the correction data is not always a necessary process and can be omitted. However, if omitted, some noise will appear in the image.
In reality, it is hardly noticed by the viewer since it is just rewritten. Further, since the DC component differential encoding (DPCM) is closed in units of Slice, the influence thereof is also the Slice in which the block exists.
Fits within.

In this way, the key data insertion circuit 35
The bit stream processed by the correction circuit 36 is supplied to the recording device 37 and recorded on the master OD. A stamper is created from this master OD, and a large number of replica discs (ROM discs) D are produced from the stamper.
Is manufactured.

Next, the determination process performed by the formatter will be described with reference to FIGS. 14 and 15.

First, in step S41, the control circuit 39 initializes the variable N to 0. Next step S
42 through S45 are the same as steps S1 through S in FIG.
This is the same processing as the processing of No. 4. That is, the arithmetic circuit 32
Reads the bitstream to a predetermined position and reads predetermined data as B. Then, the read data B is divided by the key data K stored in the memory 31, and the positions of the first block and the second block are determined from the quotient X.

Thereafter, in step S46, the detection circuit 33 proceeds to read the bit stream up to the first block, and in step S47, the DC of the first block is read.
Load the Size. The detection circuit 33, step S4
8, it is determined whether or not DC Size is 0, and if it is not 0, the LSB of DC Differential of the first block is stored in the memory 3 in step S49.
4 and set it to Register_1. D
When it is determined that C Size is 0,
In step S50, the detection circuit 33 causes the register
Set 0 to er_1.

Next, the detection circuit 33 proceeds to step S51 to read the bit stream up to the second block, and then proceeds to step S52 where the DC of the second block is DC.
The process of reading the Size is executed.

In step S53, the detection circuit 33
Is the DC of the second block read in step S52.
It is determined whether Size is 0 or not. DC Siz
If e is not 0, the process proceeds to step S54 and the detection circuit 3
3 is the DCDifferential of the second block
To Register_2. Step S5
5, the determination circuit 38 determines that the value of Register_1 set in step S49 or S50 and Register_2 set in step S54.
To the value of. The determination circuit 38 determines the result of this comparison as
When it is determined that the two are not equal, the determination result is output to the control circuit 39. When the determination result is obtained, the control circuit 39 proceeds to step S59 and determines that the bit stream is the original one. Then, the control circuit 39 causes the display device 40 to display the fact, controls the recording device 37, and permits the operation. As a result, as described above, the data reproduced from the master disc MD is recorded on the master disc OD and further recorded on a large number of discs D.

In step S55, Register
When the determination circuit 38 determines that the values of r_1 and Register_2 are equal to each other, the control circuit 39 controls the step S5.
At 6, the variable N is incremented by 1. Then, in step S57, the control circuit 39 checks whether or not there is a block to be determined, and if there is a block to be further determined, step S57.
Returning to 42, the subsequent processing is executed. That is, in this case, since the first bit of the key data has been determined, the process returns to step S42 and the same process is repeated. Then, similar determination processing is performed on the n-bit key data, and when the n-bit data match, the process proceeds to step S58, and the control circuit 39 determines that the bit stream currently input has a probability of 1-1 / 1-1. Two
^N determines that the bit stream was illegally copied. At this time, the control circuit 39 notifies the display device 4 to that effect.
0 is output and displayed, and the recording device 37 is controlled to prohibit the recording operation.

If it is determined in step S53 that the DC size of the second block is 0,
Since no key data is recorded in the second block, the processes of steps S54 to S56 are skipped.

FIG. 16 shows a configuration example of a player for reproducing a disc manufactured by the formatter shown in FIG. In this embodiment, a bit stream obtained by reproducing the disc D is input to a VLD (variable length code decoding circuit) 61 and subjected to a variable length decoding process. The output of the VLD 61 is input to the inverse quantization circuit 62 and inversely quantized.
The output of the inverse quantization circuit 62 is supplied to the IDCT circuit 63 and is subjected to IDCT processing.

The adder 64 adds the data supplied from the IDCT circuit 63 and the predicted image data stored in advance in the prediction memory 66 and outputs the result to a display device such as a CRT (not shown). There is. Also, the adder 64
The data output by is subjected to motion compensation in the motion compensation circuit 65, and then stored in the prediction memory 66 as a predicted image.

Next, the operation will be described. The bit stream reproduced and output from the disc D is V
It is input to the LD 61 and subjected to variable length decoding processing. The inverse quantization circuit 62 inversely quantizes the variable length decoded data input from the VLD 61 and outputs it to the IDCT circuit 63.
The IDCT circuit 63 performs IDCT processing on the input data and outputs it to the adder 64. The adder 64 receives the predicted image data read from the prediction memory 66 and the IDCT circuit 6
The data supplied from No. 3 is added and output to a CRT or the like (not shown) for display.

The data output from the adder 64 is motion-compensated by the motion compensation circuit 65 and then supplied to the prediction memory 66 and stored as a prediction image.

The motion vector necessary for the motion compensation circuit 65 to perform motion compensation is separated and extracted from the bit stream.

The above processing is summarized as shown in FIG. That is, the data obtained from the original source is recorded on the magnetic tape or the high-density magneto-optical disk (MD) by the encoder to obtain the regular master (the master disk MD in the above embodiments). This processing is usually performed in a broadcasting station, studio or the like.

As described above, when the data recorded on the regular master is recorded on a large number of discs, the master is provided to the formatter. The formatter reproduces this master and records it on the master disc. And at this time, DC D
Record the key data in the differential. In this way, from the master disc on which the bitstream was recorded,
Create a stamper and duplicate a large number of replica disks from that stamper. This replica disc is sold as a product for sale to general users. The user can play this disc with the player shown in FIG.

Further, there are cases where the disks for sale are brought to the formatter and a large number of disks are requested to be manufactured. Alternatively, a master tape or a master magneto-optical disk may be manufactured from this disk, and the formatter may be requested to manufacture a large number of disks.
In this case as well, the formatter, like the case described above,
Play the master and get the bitstream. However, since the key data is recorded in this bit stream, the key data is detected by the determination processing shown in the flowcharts of FIGS. 14 and 15 described above. As a result, the display device 40 displays that the bitstream has been copied from the disc once manufactured by the formatter, and the recording device 37 is controlled by the control device 39 to prohibit the recording operation. .
This prevents illegal copying.

However, if the formatter manufactures a large number of replica discs from this unauthorized master and the discs are sold to general users, the general users can reproduce the discs as if they were legitimate discs. Becomes

In other words, in the case of this embodiment, the general user does not become unable to play either a legitimate disc or an illegally copied disc, and it is the formatter's responsibility to prevent illegal copying. To be executed.

Differential encoding (DPCM) of the DC component is S
It is closed in units of licenses. Therefore, if the position of the second block is designated as the end of Slice, the DC component shift due to differential encoding (DPCM) does not propagate to the subsequent blocks. Therefore, in this case, the correction process for the third block is unnecessary.

Further, both the first block and the second block may be the same kind of block of the luminance (Y) signal or the color difference (Cb, Cr) signal. For example, the first block is the block of the luminance signal. It is also possible to use the second block as a color difference signal block. However, the type of the second block and the type of the third block need to match because of correction.

In the above embodiment, the LSB of the DC Differential of the second block is also used.
To the DC Differential of the first block
However, when the preset key data is recorded, the first block becomes unnecessary, and the preset key data is directly recorded in the second block, and the third block is recorded. The block may correct this.

In the above embodiment, DC Dif
Although the key data is recorded in the differential, the Motion_resi in the code that encodes the difference value of the Motion Vector (motion vector) is used.
It is also possible to use dual (FLC).

That is, in the MPEG system, FIG.
As described with reference to FIG.
The motion vector of the P picture and the B picture is detected by, and the motion vector is encoded and included in the bit stream for transmission. This Motion Vect
or is a VLC that is VLC as shown in FIG.
n_code and Motion_res as FLC
It is represented by idual. Motion_code is M
Represents a rough value of the motion vector, Mot
ion_residual represents a correction value for representing a fine value. Also, f_code is Motion_c
It represents the accuracy (magnification) of ode.

For example, when f_code is 1, Mot
Ion_code represents a value with a precision of 0.5. Since this represents a sufficiently fine value, in this case Moti
on_residual is not used.

If f_code is 2, then Motionio
n_code represents integer precision, and Motion_res
idual represents a value with a precision of 0.5. That is, at this time, Motion_residual is represented by a 1-bit FLC indicating 0 or 0.5.

Further, when f_code is 3, M
motion_code represents a value with a precision of a multiple of 2, and M
option_residual is 0, 0.5, 1.0
Alternatively, it is a 2-bit FLC representing 1.5.

As in the case of DC Differential, when Motion_code is 0, Motion_residual does not exist.

Motion_r which is such FLC
In the esidual, the above mentioned DCDifferenti
As in the case of al, key data for preventing illegal copying can be recorded.

Note that Motion_residual exists in P pictures and B pictures, but M in B pictures
If you use option_residual,
Since the B picture is not used for prediction of other pictures, it is possible to prevent the influence of key data insertion on other pictures.

In the above embodiment, the key data is composed of n bits, but the n bits of data may be arranged in one screen (picture) or a plurality of screens. It is also possible to disperse and arrange them in (picture).

Further, in the above-mentioned embodiment, the predetermined block is obtained by calculation. However, the calculation formula can be appropriately changed if necessary.

Further, instead of obtaining a predetermined block by calculation, it is possible to store it in the pattern ROM in advance.

These embodiments have the following features.

(1) The standard as MPEG Video is satisfied.

(2) Since the key data is inserted in the code which is always FLC in the bit stream according to the standard,
No processing is required in the encoder. as a result,
It is possible to more reliably prevent illegal copying. This is because the encoders are usually mounted in a studio or the like, and the number thereof is relatively large. On the other hand, a formatter that manufactures a large number of disks requires a relatively large-scale facility, and is usually owned by a manufacturer or the like, and the number thereof is much smaller than that of an encoder.

(3) Since the key data is inserted in the FLC, the bit stream length does not change. When the key data is inserted into VLC, the length of the bitstream changes, so that the encoder side assumes VBV (Video Bu) as a buffer on the decoder side.
It becomes impossible to prevent the underflow and overflow of the buffer.

(4) Since only the lower bits in the FLC are rewritten, the noise given to the image can be substantially ignored.

(5) Since the key data exists in the data, it is difficult to decipher the key data.

Although the present invention has been described by taking the case of compressing data by the MPEG system as an example, the present invention is also applicable to the case of compressing data by the JPEG system (however, Motion_residual is not prescribed in the JPEG system). It is possible to apply.

Further, as a method for orthogonally transforming data, a method other than DCT can be used.

[0119]

As described above, according to the data recording device of the first aspect and the data recording method of the seventh aspect, at least a part of the code which is always a fixed length code according to the standard is illegal. Since the key data for the copy protection is written, it is possible to easily and surely prevent the illegal copy. Further, since it is not necessary to perform special processing at the encoding stage, it can be applied to an existing bit stream.

The same effect can be achieved in the illegal copy preventing apparatus according to the eighth aspect, the illegal copy preventing method according to the ninth aspect, and the data recording medium according to the tenth aspect.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a principle of illegal copy prevention of the present invention.

FIG. 2 is a diagram illustrating selection of first to third blocks.

FIG. 3 is another diagram illustrating selection of first to third blocks.

FIG. 4 is a diagram illustrating coding of DC components of DCT coefficients.

FIG. 5 is a diagram illustrating a sign of a size of a DC component of a DCT coefficient.

FIG. 6 is a diagram illustrating a sign of a difference between DC components of DCT coefficients.

FIG. 7 is a diagram illustrating key data.

FIG. 8 is a block diagram showing a configuration example of an encoder.

FIG. 9 is a block diagram illustrating a configuration example of a formatter.

FIG. 10 is a flowchart illustrating an operation during recording according to the exemplary embodiment of FIG.

11 is a flowchart following FIG.

FIG. 12 is a flowchart following FIG. 11.

FIG. 13 is a diagram illustrating a process of step S18 of FIG.

FIG. 14 is a flowchart illustrating a determination process according to the embodiment of FIG.

FIG. 15 is a flowchart following FIG.

FIG. 16 is a block diagram showing a configuration example of a player.

FIG. 17 is a diagram illustrating the principle of key data recording according to the present invention.

FIG. 18 is a diagram illustrating motion_code.

[Explanation of symbols]

31 memory, 32 arithmetic circuit, 33 detection circuit,
34 memory, 35 key data insertion circuit, 36
Correction circuit, 37 recording device, 38 determination circuit,
39 control circuit, 40 display device

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasushi Fujinami 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation

Claims (10)

[Claims] 1. A data recording apparatus for recording recording data on a recording medium, wherein a bit stream of the recording data including an orthogonal transform coefficient converted into a variable length code and a fixed length code is always a fixed length code according to a standard. The specified code from among the codes to be specified, and a writing means for writing the key data for preventing illegal copy to at least a part of the fixed length code specified by the specifying means. And a data recording device. 2. The recording data is data compressed by an MPEG system, and the fixed length code designated by the designating means is DC Differential or Motion_residual. Data recorder. 3. The Mo for a B picture is specified by the specifying means.
3. The data recording device according to claim 2, wherein a region_residual is designated. 4. The designating means designates a first fixed length code and a second fixed length code, and the writing means stores the second data as the key data.
Of the fixed-length code of
The data recording device according to claim 1, wherein the value is set to a value corresponding to B. 5. The data recording apparatus according to claim 3, wherein the designating unit sets a block to which the second fixed-length code belongs to as a last block of a slice. 6. The data recording apparatus according to claim 1, further comprising a correction unit configured to record correction data for correcting the key data in the other fixed-length code. 7. A data recording method for recording recording data on a recording medium, wherein a bit stream of the recording data including an orthogonal transform coefficient converted into a variable length code and a fixed length code is always a fixed length code according to the standard. A data recording method, wherein a predetermined code is designated from among the designated codes, and key data for preventing illegal copying is written in at least a part of the designated fixed-length code. 8. Among the orthogonal transform coefficients converted from the variable length code and the fixed length code from the bit stream of the input recording data, the illegality is always written in the code which is the fixed length code according to the standard. An unauthorized copy protection apparatus comprising: a detection unit that detects copy protection key data; and a generation unit that generates a display signal that displays the detection result of the detection unit. 9. An illegal write always written in a code which is a fixed-length code in a standard among orthogonal transform coefficients converted from a variable-length code and a fixed-length code from a bit stream of input recording data. An illegal copy prevention method characterized by detecting key data for copy prevention and generating a display signal for displaying the detection result. 10. A data recording medium in which an orthogonal transformation code is converted into a variable-length code and a fixed-length code and recorded as recording data. In the standard, the fixed-length code is always added to the code to prevent illegal copying. A data recording medium on which data is written.