JPH09128357A - Chaotic neuron circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To unnecessitate the arrangement of a converting circuit in connection with a pre-existed electronic circuit and to simplify circuit configuration by using an integrating circuit which is cascade-connected to a chaotic neuron circuit. SOLUTION: The chaotic neuron circuit is provided with a pre-processing circuit part and a post-processing circuit part capable of dealing with digital data. The post-processing circuit part provided at the output stage of the circuit is constituted of a central processing unit(CPU) 21, RAM 22, an interface circuit 23, a counter 24, an adder(ALU 1) 25, a pipeline register(PR) 26, the adder(ALU 2) and the integrating circuit 28. In the integrating circuit 28, a reciprocal is obtained from a counter value which is outputted from the counter 24, the reciprocal and an output xk from ALU 2 are inputted and their integrated value is inputted to one input terminal of ALU 2. The cascade-connected integrating circuit 28 is used so that the input/output of a digital chaos signal is easily attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chaotic neuron circuit, and more particularly to a chaotic neuron circuit which does not require a conversion circuit to be connected to an existing electronic circuit and can simplify the circuit configuration.

[0002]

2. Description of the Related Art In general, fractal theory defines the complexity of geometric structures existing in nature and gives a methodology for describing them. In that sense, it has a close relationship with the chaos phenomenon, which is one of the mechanisms of complexity generation, and in recent years, fractal theory is concerned with the fractal nature of image data in the advanced information society such as multimedia. New image compression technology and image processing / image recognition technology based on are being developed. In particular, fractal theory has been studied for application in neural networks.

Here, regarding information processing of a fractal image, there is generation of a fractal image by an iterative function method using affine reduction conversion. The affine transformation is to obtain a figure of an invariant set by performing a reduction transformation of a specific figure by a combination of movement, rotation, enlargement or reduction.

The iterative function method using the affine contraction transformation can be realized by the circuit model shown in FIG. 3, and an image can be generated by linear calculation. FIG. 3 is an explanatory diagram showing an outline of a cyclic circuit model of an iterative function system. That is, the circuit model of FIG. 3 becomes a model of the fractal coding circuit.

In the circuit model of FIG. 3, by using the property that all sequences starting from an arbitrary initial value are the same invariant set, a parallel computer having a large number of processors and operating in parallel at high speed can be used at high speed. Images can be generated.

That is, each pixel of an image is associated with a processor, and each processor performs reduction conversion with probability and point sequence {x
The number C (i, j) of points where k, yk} falls in the minute area corresponding to the pixel (i, j) is counted. Each processor obtains a processor address corresponding to the coordinates of the conversion result (xk, yk) and counts up C (i, j) through inter-processor communication. In this way, images can be generated at high speed by simultaneous parallel processing.

The circuit model of FIG. 3 is basically
Two adder circuits Σ1 and Σ2 and two delay operation circuits D1 and D
And 2. In order to output the conversion result (xk, yk), (ei, pi) is input to the adder circuit Σ1 from the outside, and further, the delay operation circuits D1 to (ai, pi) and the delay operation circuit D2 to (bi, pi). ) Is input and addition operation is performed,
The converted result (xk) is output. Also, adder circuit Σ2
(Fi, pi) is input from the outside to the delay calculation circuits D1 to (di, pi) and the delay calculation circuit D2 to (ci,
pi) is input and addition operation is performed, and the conversion result (yk)
Is output. Regarding the above-mentioned fractal image information processing, Ohmsha, published October 25, 1993, "Chaos Application Strategy" Kazuyuki Aihara, supervised by Ryuji Tokunaga, p98-
p124.

In order to realize the model of FIG. 3, the chaos chip shown in FIG. 4 is required. FIG.
[Fig. 3] is a block diagram showing the configuration of a chaos chip. As shown in FIG. 4, the chaotic chip is composed of a nonlinear delay element composed of a nonlinear function circuit and a delay circuit, a linear delay element composed of a linear function circuit and a delay circuit, and an addition element composed of an addition circuit. Regarding the above-mentioned chaotic chip, Ohmsha, issued October 25, 1993, "Chaos Application Strategy"
Kazuyuki Aihara, Ryuji Tokunaga supervision p82-p86.

In the image processing, which uses a neural network method, a method of extracting individual characteristic portions of a subject is described in Japanese Patent Laid-Open No. 4-264985, and features of the subject and the object are described. A method for obtaining data is described in JP-A-2-300871.

In the speech processing using the neural network method, after extracting local features using the neural net, more global features are extracted in the upper hidden layer. A method of recognizing voice recognition is described in Japanese Patent Laid-Open No. 140800/1992, and a method of outputting a phoneme recognition result of a feature vector sequence having a frame length for an input voice is described in Japanese Patent Laid-Open No. 1-204099. .

The fractal image or audio data that has been affine-reduced and converted by using a neural network is generally transmitted through a transmission line. However, if an uncorrectable error occurs during the data transmission, it is received. The side was able to output a resend request to the transmitting side so that the data in the erroneous part would be transmitted again, and it was possible to obtain error-free data.

[0012]

However, in the first conventional example (JP-A-1-147657) or the second conventional example (chaotic strategy), a chaotic signal is output from a certain basic circuit. , It was necessary to have at least an analog electronic circuit containing a non-linear delay circuit in a part of the entire circuit, so a conversion circuit for converting analog to digital is required for a digital chaotic neuron circuit, There is a problem that the circuit configuration becomes complicated.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a chaotic neuron circuit capable of inputting and outputting a digital chaotic signal without providing a converting circuit for connection with an electronic circuit. To do.

[0014]

DISCLOSURE OF THE INVENTION The present invention for solving the above-mentioned problems of the prior art is a chaotic neuron circuit which comprises a first adder circuit, a second adder circuit, a third adder circuit and a third adder circuit. A first delay circuit for delaying an output, and the fourth delay circuit
A second delay circuit for delaying the output from the delay circuit, and the first adder circuit receives (ei, pi) from the outside and the output from the second delay circuit, (Fi, pi) and the output from the first delay circuit are input to the second adder circuit from the outside, and the third adder circuit outputs the signals from the first adder circuit and the first delay circuit. A preprocessing circuit portion to which an output is input and the outputs from the second adder circuit and the second delay circuit are input to the fourth adder circuit; fifth and sixth adder circuits; A third delay circuit for delaying the output from the adder circuit of No. 5, storage means for storing the output (xk, yk) from the preprocessing circuit portion, and input / output control for the storage means to perform an integration loop. Control means for outputting the number, and counting the integrated loop number to output a counter count. Counter and an integrating circuit for multiplying the output from the sixth adding circuit by the reciprocal of the counter count, and the fifth adding circuit includes the output from the control means and the sixth adding circuit. And a post-processing circuit portion to which the output from the third delay circuit and the output from the integrating circuit are input to the sixth adder circuit, It is not necessary to install a conversion circuit to connect with an existing electronic circuit, and the circuit configuration can be simplified.

[0015]

Embodiments of the present invention will be described with reference to the drawings. The chaotic neuron circuit according to the embodiment of the present invention provides a digital chaotic neuron circuit with a simple configuration by using an integrating circuit cascade-connected to the circuit.

A chaotic neuron circuit (present circuit) according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG.
FIG. 4 is a configuration block diagram showing a basic configuration of a chaotic neuron circuit according to an embodiment of the present invention, which is a specific circuit for realizing the circuit model shown in FIG. 3, and FIG. 2 shows an output stage of FIG. It is a block diagram of a circuit to be connected. Although FIG. 2 is connected to the respective output stages of xk and yk, only the output stage of xk will be described for simplification of description. However, the yk output stage is also the same as in FIG. Here, the circuit of FIG. 1 is used as a pre-processing circuit portion of this circuit, and the circuit of FIG. 2 is used as a post-processing circuit portion of this circuit.

First, the preprocessing circuit portion of this circuit realizes an iterative function method using affine contraction transformation by a cyclic circuit model like a neural network, and generates an invariant set from arbitrary initial values. is there. In the neural network, a plurality of circuits shown in FIG. 1 are used, and the output (ei, pi) from the previous circuit is used.
) And (bi, pi) are input and the result (xk, yk) is output, and at the same time, (ei + 1, pi + 1) and (bi + 1, pi + 1) are output to the next circuit. It is like this.

As shown in FIG. 1, the basic structure of the preprocessing circuit portion of this circuit is basically composed of an adder circuit and a delay circuit.

The part consisting of the adder circuit and the delay circuit is (e
i, pi) and (bi, pi) are input to the adder (AL
U) 1, an adder (ALU) 2 to which (fi, pi) and (di, pi) are input, and an output from ALU1 and (ai, p)
i) is input to output an addition result (xk), and an adder (ALU) 3 is input to the output from ALU 2 and (ci, pi) to output an addition result (yk) ( A
LU) 4 and (xk) are delayed and ALU2 and ALU3
A flip-flop (DQ) 5 of a delay circuit for outputting to
It is composed of a delay circuit flip-flop (DQ) 6 which delays (yk) and outputs it to ALU1 and ALU4.

ALU1 and ALU3 in the above configuration
Corresponds to the adder Σ1 of FIG. 3, ALU2 and ALU4 correspond to the adder Σ2 of FIG. 3, and DQ5 corresponds to the delay circuit D1 of FIG.
Q6 corresponds to the delay circuit D2 in FIG.

Next, as shown in FIG. 2, the post-processing circuit portion provided at the output stage of this circuit is a central processing unit (CP).
U) 21, RAM 22, interface circuit 23
, Counter 24, adder (ALU1) 25, pipeline register (PR) 26, adder (ALU1)
2) 27 and an integrating circuit 28.

Further, each part of the post-processing circuit part will be specifically described. The RAM 22 is a writable storage unit that stores the values of the outputs (xk, yk) shown in FIG.
The output values are read by the operation of 21.

The central processing unit (CPU) 21 is a RAM 2
The output value (xk) is read from 2 and output to the interface circuit 23, and the integrated loop number corresponding to the output (xk) is output to the interface circuit 23. Further, the CPU 21 receives (xk) input as the negative logic D2 by the interface section 23 and performs arithmetic processing. The CPU 21 can preset the number of integrated loops and can change the number during the calculation process.

The interface circuit 23 inputs the output (xk) read from the RAM 22 by the processing of the CPU 21 as a negative logic D0, and also inputs the cumulative loop number output from the CPU 21 to the counter 24 of the negative logic. It is output as D1. Further, the interface circuit 23 receives the negative logic D2 (xk) output from the counter 24 and outputs it to the CPU 21.

The counter 24 outputs the input xk as a negative logic D1 to one terminal of the ALU 1, calculates a counter value from the input integration loop number, and outputs it to the integration circuit 28. Also, the output of ALU1 (x
k), and the negative logic D2 is input to the interface circuit 23.
Is output.

The adder (ALU1) 24 has one input terminal (xk) as negative logic D1 from the counter 24.
Is input to the other input terminal, and the output (x
k) is input and the addition result is output.

The pipeline register (PR) 26 is A
It is a register that temporarily stores the output value from LU1, and its output is output to one terminal of ALU2.

In the adder (ALU2) 27, the value from the PR 26 is input to one input terminal, the output from the integrating circuit 28 is input to the other input terminal, and the integrated result (xk)
Is output.

The integrating circuit 28 obtains the reciprocal of the counter value output from the counter 24, and inputs the reciprocal and the (xk) output from the ALU2. The integrated value is input to one input terminal of the ALU2. Is what you enter.

Next, the operation of the chaotic neuron circuit according to the embodiment of the present invention will be described. First, the preprocessing circuit portion of the chaotic neuron circuit of this embodiment will be described. The input (ei, pi) and the output (bi, pi) from DQ6 are added by ALU1 and output to ALU3. Similarly, (fi, pi) and (di, pi) output from DQ5 are added by ALU2 and output to ALU4.

Then, in ALU3, the output from ALU1 and the output (ai, pi) from DQ5 are added (xk
) Is output, and similarly, the output from ALU2 and the output (ci, pi) from DQ6 are added by ALU4 to output (yk), and at the same time, (xk), (yk)
Is input to the CPU 21 of the post-processing circuit portion. In addition, (x
k) and (yk) are fed back to DQ5 and D6, delayed, and output to each ALU.

Next, the post-processing circuit portion of the chaotic neuron circuit of this embodiment will be described with reference to FIG.
The post-processing circuit portion is designed so that the entire circuit operates in negative logic. When the output (xk, yk) from the preprocessing circuit section is input, those output values are stored in the RAM.
22. The CPU 21 reads (xk) stored in the RAM 22 (only (xk) will be described for simplification of description) and outputs it to the interface circuit 23, and at the same time, outputs the accumulated loop number corresponding to (xk) as an interface. Output to the circuit 23.

The interface circuit 23, to which (xk) and the number of accumulated loops are input, sets (xk) to negative logic D0,
The counter 24 outputs negative logic D0 and (xk).
Then, the counter 24 outputs the input negative logic D0 to the one terminal of the ALU1 as the negative logic D1 and also counts the input integration loop number and outputs the counter value.

(Xk) as a negative logic D1 from the counter 24 is inputted to one input terminal of the ALU1.
The output (xk) from the ALU2 is input to the other input terminal, addition operation is performed, and the result is output.

Further, the output value from ALU1 is temporarily stored in PR26, and the output is output to one terminal of ALU2. Then, PR2 is connected to one input terminal of ALU2.
The value from 6 is input, and the integrating circuit 2 is input to the other input terminal.
The output from 8 is input, the integration operation is performed, and the result (xk) is output.

Further, the reciprocal of the counter value output from the counter 24 and (xk) output from the ALU2 are input to the integrating circuit 28, and the integrating circuit 28 performs a logical product operation. Input to the input terminal of.

Here, the post-processing circuit portion is (xk, yk)
The integrated loop number corresponding to the input of is output, the integrated loop number is counted by the counter 24, the reciprocal of the counter count is multiplied by (xk) by the integrating circuit 28, and the result is input to the ALU2, thereby realizing the cascade connection. A large fluctuation is generated by delaying the value for the length of time.

According to the chaotic neuron circuit according to the embodiment of the present invention, by using the integrating circuit 28 that is cascade-connected, it is possible to perform digital chaos without installing a special converting circuit for connection with an existing electronic circuit. There is an effect that it is possible to easily input and output signals.

[0039]

According to the present invention, since the chaotic neuron circuit is provided with the pre-processing circuit portion and the post-processing circuit portion capable of handling digital data, the conversion circuit can be connected to an existing electronic circuit. There is an effect that the installation is unnecessary and the circuit configuration can be simplified.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a preprocessing portion of a chaotic neuron circuit according to an embodiment of the present invention.

FIG. 2 is a configuration block diagram of a post-processing portion of the chaotic neuron circuit according to the embodiment of the present invention.

FIG. 3 is an explanatory diagram showing an outline of a cyclic circuit model of an iterative function system.

FIG. 4 is a configuration block diagram of a chaotic chip.

[Explanation of symbols]

1, 2, 3, 4, 25, 27 ... Adder, 5, 6 ... Flip-flop, 21 ... CPU, 22 ... RAM, 2
3 ... Interface circuit, 24 ... Counter, 26
… Pipeline register, 28… Integration circuit

Claims (1)

[Claims] 1. A first, a second, a third, and a fourth adder circuit, a first delay circuit for delaying the output from the third adder circuit, and a delay circuit for delaying the output from the fourth delay circuit. And an output from the second delay circuit is input to the first adder circuit from the outside, and a second delay circuit is input to the second adder circuit from the outside (fi , pi) and the output from the first delay circuit are input, and the outputs from the first adder circuit and the first delay circuit are input to the third adder circuit, and the fourth adder circuit is input. The circuit has the second
And a preprocessing circuit portion to which the output from the second delay circuit is input, fifth and sixth adder circuits, and a third delay circuit that delays the output from the fifth adder circuit. , Storage means for storing the output (xk, yk) from the preprocessing circuit portion, control means for controlling input / output to and from the storage means, and outputting an integrated loop number, and counting the integrated loop number. A counter for outputting a counter count; and an integrating circuit for multiplying the output from the sixth adder circuit by the reciprocal of the counter count, and the fifth adder circuit has an output from the control means and the And a post-processing circuit portion to which the output from the third delay circuit and the output from the integrating circuit are input to the sixth adder circuit. Characteristic chaos Ron circuit.