JPH09128258A - Resynchronization resetting processing method for computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need to initialize a cache in a resynchronization resetting processing when a CPU part which has recovered from a fault is incorporated again. SOLUTION: When a system is restarted up, CPU parts 100 and 110 of both systems A and B inhibit, for example, the ways 1 of caches 103 and 113 to be used and enable ways 0 to be used, thereby starting synchronous operation. Then if, for example, the CPU part 110 gets out of order and recovers and an IPL processing is executed by temporarily resetting the CPUs 100 and 110 so as to incorporate it in the system again and perform the synchronous operation, the way use inhibition of the caches 103 and 113 is inverted into enable the ways to be used, and the synchronous operation is restarted. Here, the ways 1 are inhibited from being used so far, so the initialization is secured and they need not be initialized on purpose.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system in which a plurality of CPU units operate in synchronization with each other.
The present invention relates to speeding up of resynchronization reset processing for resuming synchronous operation by incorporating a CPU unit once separated from the system due to a failure into the system again.

[0002]

2. Description of the Related Art One CPU can be operated by synchronously operating (dual operation) the same processing by a plurality of CPU sections.
Even if a part fails, it will remain after the disconnection C
It is possible to continue online business by the PU unit, and is widely applied to fault tolerant computers.

In this type of computer system, repair / replacement of a faulty CPU portion is carried out during online work by hot line replacement or the like. Then, the CPU, which has been repaired, is powered on by the system,
A processor, a cache, and a memory used as a main memory (hereinafter, abbreviated as MS) are diagnosed and initialized. This processing is generally performed by a part of the IPL processing program stored in the ROM of each CPU unit. When the diagnosis / initialization process is completed normally, the CPU section notifies other CPU sections that the preparation for the installation is completed, and enters the stand-by status for the installation. On the other hand, another CP that detected this
Department U uses this CPU while continuing online operations.
The process of incorporating the unit into the system again, that is, the resynchronization reset process is executed.

The resynchronization reset process is a process for synchronizing the CPU unit to be incorporated with another CPU unit that continues the online business etc. and restoring the dual operation. Here, in order for a plurality of CPU units to execute the same processing in synchronization, it is necessary that all the CPU units always execute the instruction of the same address. For this reason, it is necessary that the caches of all CPU parts and the contents of MS all match. However, especially in the cache, since the contents of the entry dynamically change, there is a CPU unit waiting for the diagnosis / initialization to be completed and to be installed in the system again.
In the CPU unit that continues online business, the internal state of the cache is completely different. The caches of all the CPUs need to be initialized in order to match them and restore synchronous operation again.

Generally, in the resynchronization reset process, when the CPU unit performing an online operation or the like detects that the CPU unit to be incorporated is ready to be incorporated, the ongoing process information (register, other information) is saved, and the system A method of once issuing a reset to all the CPU units via the inter-controller is widely used. When all the CPU units are reset, each processor executes the IPL process. As a result, all CP
Since the U unit starts executing the IPL process in the ROM, the instruction execution is synchronized.

In the prior art, in this IPL processing,
After diagnosing / initializing the processor, the cache was subsequently diagnosed / initialized. As a result, the caches of all CPU parts will be initialized.
The contents of all entries match. Here, each processor switches to the cache use state.
After that, restore the saved ongoing processing information,
Resume the suspended online business.

[0007]

In the above-mentioned prior art, by issuing a resynchronization reset to all CPU units, it is possible to surely synchronize the instruction execution with the cache state. Is
Since it is executed while fetching the instruction directly from the ROM, it takes processing time. Particularly in recent years, as the capacity of caches has increased, the time required for cache diagnosis / initialization has increased accordingly.

In order to restore the faulty CPU unit, it is possible to suspend the online work etc., issue a reset to all CPUs, and have each processor execute the IPL processing.
It is very effective in guaranteeing synchronous operation. But,
If this resynchronization reset processing period is not set as short as possible, it is obvious that interruption of processing adversely affects online business.

It is an object of the present invention to provide a method for eliminating the cache diagnosis / initialization during the resynchronization reset process in the re-installation operation of the CPU part of the fault tolerant computer by the dual operation of the processor having the cache.

[0010]

According to the first aspect of the present invention, when all the cache ways of each CPU are initialized when the system is started up, a specific cache way is disabled and a synchronous operation is started. After that, when a failure occurs in a certain CPU unit and repair is completed and the CPU unit is re-installed in the system, when all CPUs are reset once and the synchronous operation is restored, the use prohibition of the cache way is reversed. Then, the cache way, which has been disabled until then, can be enabled and the synchronous operation can be restarted. Since this cache way remains initialized, it is not necessary to perform diagnosis / initialization during the resynchronization reset process.

According to the second aspect of the present invention, when the system is started up, after all cache ways of each CPU are initialized, all cache ways are enabled and synchronous operation is started. Then, a failure occurs in a certain CPU,
At the preparatory stage when the repair is completed and the CPU unit is re-installed in the system, the CPU unit in the process of other processing disables the specific cache way and continues the process, and in between the processes. The specific cache way is periodically initialized by a predetermined number of entries. Then, in the CPU unit in the process, when all the initialization of the specific cache way is completed, all the CPU units are reset once, and the prohibition of use of the cache way is reversed in the resynchronization reset process, The specific cache way whose initialization has been completed is enabled and the synchronous operation is restarted. After this synchronous operation is restarted, the newly disabled cache ways are periodically initialized by a predetermined number of entries between synchronization processes, and when all the cache ways have been initialized, all cache ways are restarted. Enable to continue synchronous operation. As a result, the cache entries of all ways can be used while avoiding interruption of online business as much as possible.

[0012]

1 shows an example of the configuration of a computer system to which the present invention is applied. Here, the CPU section is duplicated with 100 and 110, and these two CPU sections 1
It is assumed that 00 and 110 have a dual configuration in which the same processing is synchronously executed. For convenience of explanation, 100 is A system C
The PU unit 110 will be referred to as the B system CPU unit. 12
Reference numeral 0 denotes an inter-system control unit, which manages / monitors whether the CPU units 100 and 110 execute the same processing in synchronization with each other, and in what state the mutual CPU units are.

Since the configurations of the A system and the B system are symmetrical, each component will be described by using the A system CPU section 100. Reference numeral 101 is a processor, and the cache control unit 10
The cache 103 is connected via 2. In this embodiment, the cache 103 has a 2-way set associative cache configuration in which 104 and 105 are each way (0 way, 1 way). Reference numeral 106 denotes a memory (MS) used by the processor 101 as a main memory, 10
A ROM 7 stores an IPL processing program.

FIG. 2 shows an internal configuration of the cache control unit 102. 201 is a program executed by the processor 101.
4, 105 is a control register for setting whether to use / inhibit, and 202 is a cache entry hit / miss hit and MS according to the setting of the control register 201.
The control circuit 106 reads out instructions and data from 106 and writes data. The internal configuration of the cache control unit 112 is exactly the same.

Next, the operation of each embodiment of the present invention will be described by taking the configuration of FIGS. 1 and 2 as an example.

<Embodiment 1> This corresponds to the invention of claim 1. FIG. 3 shows a flowchart of the IPL processing of this embodiment, and FIG. 4 shows a flowchart of the resynchronization reset processing. The program for the IPL processing in FIG. 3 is ROM1.
07 and 117, they are activated at power-on of the entire system at system startup, at power-on for re-installation of the CPU unit after failure recovery, and at resynchronization reset processing. In addition, the program for the resynchronization reset process in FIG.
16 and is activated periodically from the task switching process of the OS.

First, the operation from the start-up of the system to the start of the IPL processing by the CPU units 100 and 110 of the A and B systems to the start of online business will be described.

When the power of the entire system is turned on, the CPU units 100 of both A / B systems are passed through the inter-system control unit 120.
A reset is issued to 110. As a result, first, the process 301 of FIG. 3 is executed, and the processors 101 and 11
1 is individually diagnosed and initialized. Next, process 3
In 02, it is determined whether or not this reset is caused by the resynchronization reset issuance. Since it is reset by power-on of the entire system now, in process 303, the cache 103,
All 113 ways (104 and 105 and 114 and 11
The entry 5) is diagnosed / initialized, and in step 304, the MS 106/116 is diagnosed / initialized. Next, in process 305, it is determined whether the entire system is started up. In this case, since the condition is satisfied, the process 310 is executed and the control registers 2 of the cache control units 102 and 112 are executed.
In 01, only the cache entry of the predetermined way is set to be prohibited. Here, both A / B CPUs
It is assumed that both units 100 and 110 disable the way 1 cache entry. Next, in process 311, the operating system (OS) is loaded and other processes are executed, and the IPL process at system startup is completed.

As a result, each CPU unit 10 of both A / B system
0 and 110 start online business and execute the same processing synchronously. During this time, the caches 103 and 113
Since only the entry of way 0 is used under the control of the cache control units 102 and 112, the entry of way 1 remains diagnosed and initialized.

Next, after a failure occurs in one of the CPU parts and the failure is recovered, the re-synchronization reset process is executed from the time when the re-installation of the CPU part is started until the dual operation is restored. Will be explained.

When a failure occurs in the CPU section of one system, the inter-system control section 120 disconnects the CPU section in which the failure has occurred and reports the occurrence of the failure to the CPU section of the system which continues the online business. Here, for convenience of explanation, a B CPU
It is assumed that a failure has occurred in the unit 110 and the inter-system control unit 120 has disconnected this.

The CPU section 1 of the B system, such as by hot line replacement
When the repair of 10 is completed, the system console or the like issues a power-on to the B system CPU unit 110, which is also notified to the A system CPU unit 100 through the intersystem control unit 120. Up to this point, the general operation of fault / recovery processing of a fault tolerant computer has been described.

When the power-on is issued to the B system CPU section 110, the CPU section 110 starts the IPL processing of FIG. As a result, first, in process 301, the processor 1
11 is diagnosed and initialized. In the next process 302, it is determined that the resynchronization reset is not performed because the power is turned on after the failure recovery, and the processes 303 and 304 are executed. At this stage, the cache 113 of the B system CPU unit 110 is initialized again with all entries of ways 0 and 1. next,
In process 305, since it is determined that the system is not powered on due to system startup, process 306 is executed. In this process 306, the diagnosis / initialization of the CPU section 110 is completed, and the completion of the installation preparation is confirmed by the inter-system control section 1
Notify the A system CPU unit 100 via 20. After the completion of installation preparation is notified, the B system CPU unit 110 performs processing 307.
Then, it waits for the re-installation by the re-synchronization reset. The inter-system control unit 120 manages the state of the entire system and individual CPU units with a status register or the like, and in the processes 302 and 305, for example, by looking at the status register or the like, Resynchronization reset and system startup can be easily determined.

On the other hand, after the power-on issuance to the B system CPU unit 110, the A system CPU unit 100 periodically executes the operation of FIG. 4 by the task switching process of the OS while continuing the online work.

In FIG. 4, a process 400 is a process for judging the completion of installation preparation of another system CPU unit notified via the intersystem control unit 120. The determination is not established until the B system CPU unit 110 executes the process 306 of FIG.
In this case, the A system CPU unit 100 does not go to the processing 411,
Return to online business etc. When the determination in process 400 is established, the processor 101 of the A system CPU unit 100 saves the ongoing process information in process 411, and then, in process 412, a resynchronization reset is sent to the intersystem control unit 120. Emit. As a result, the inter-system control unit 120 causes the A / B system C
A reset is issued to the PU units 100 and 110 at the same time.

Each CPU unit 100, 110 that has been reset
Simultaneously enters execution of the IPL process of FIG. in this case,
After diagnosing and initializing the processor 101 in the process 301, the CPU units 100 and 110 determine in the process 302 that the IPL process is started by the resynchronization reset.
08 is executed. It should be noted that the processor 111 of the B system CPU unit 110 uses the IP for re-installation after the failure recovery.
Since the diagnosis / initialization is performed in the L process, the process 301 is an empty execution. The process 308 is performed by the cache control unit 102,
This is a process of reversing and resetting the use prohibition of the cache way set in the control register 201 of 112.
As a result, in the A system CPU unit 100, the way 1 of the cache 103 has been prohibited until then, but now the way 0 is set to be prohibited. Since this is reflected in the status register of the inter-system control unit 120, at this time, the B system CPU unit 110 refers to the status register to make the way 1 of the cache 113 symmetrical to the A system.
Will be set as prohibited. Next, processing 309
In step 413, the A system CPU unit 110 restores the processing information saved in step 411 and returns to the online operation. Also, B
The system CPU unit 110 also takes in the processing information saved by the A system CPU unit 110 and returns to the online work. Although omitted in FIG. 1, the processing information save destination is A / B.
Either the external storage device or the main memory may be used as long as it can be commonly accessed by both systems.
The information saved in 00 can also be taken in by the B system CPU unit 110.

In this way, the CPU unit 1 for both the A / B system
00 and 110 will again execute the same processing in synchronization, and both caches 103 and 113 will
The entry of way 1, which is guaranteed to be diagnosed and initialized, will be used. Therefore, it is possible to eliminate the need for cache diagnosis and initialization, which has been conventionally required in the resynchronization reset process.

Note that the way 0 of the cache 103 in the A system CPU unit 100, which has been prohibited from use in the process 308 of FIG. 3, is gradually diagnosed / initialized while continuing online work in preparation for the subsequent resynchronization reset. Just turn it into something. At this time, from the viewpoint of synchronization processing, the B system CPU unit 11
0 performs the same process, but the way 0 of the cache 113 of the B system CPU unit 110 has been initialized in the process 303 of FIG. 3, and therefore the process of the B system CPU unit 110 is temporarily executed (empty). Run).

<Embodiment 2> This corresponds to the invention of claim 2. In the first embodiment, the cache 103,
Since the way 0 or the way 1 of 113 is always set to be prohibited, it means that only half the capacity of the entire cache is always used. This is unsuitable for computer systems that emphasize performance. In the second embodiment, normally, the entire cache capacity can be used, and the way 0 or the way 1 is temporarily provided only before and after the CPU unit is re-installed.
Is prohibited.

FIG. 5 is a flowchart of the IPL process of this embodiment, and FIG. 6 is a flowchart of the resynchronization reset process.
Further, FIG. 7 shows a flowchart of the recovery processing of the prohibited specific cache way.

The IPL processing program shown in FIG. 5 is similar to that shown in FIG. 3, at the time of power-on of the entire system at the time of system startup, at the time of power-on for re-installation of the CPU unit after recovery from a failure, and resynchronization reset issue. Each time, it is activated. The difference between the two is that in this embodiment, all the ways of the cache are made available at the time of system startup, and therefore the processing 310 of FIG. 3 is not present in FIG.

The program for the resynchronization reset process in FIG. 6 and the program for the cache way recovery process in FIG. 7 are periodically activated from the task switching process of the OS. Here, the difference between FIG. 4 and FIG. 6 is that in FIG.
That is, a step of prohibiting the use of the specific cache way only when the re-installation process of the CPU unit is executed is set to 0. As will be described later, the cache way recovery process of FIG. 7 is periodically activated on condition that this process 620 has been completed.

First, the operation from the start-up of the system to the start of IPL processing by the CPU units 100 and 110 of both the A / B system and the start of online work will be described.

When the power of the entire system is turned on, the CPU units 100 of both A / B systems are passed through the inter-system control unit 120.
A reset is issued to 110. The operation in this case is basically the same as that of the first embodiment.
10 is processing 501 → 502 → 503 → of FIG. 5, respectively.
By executing 504 → 505 → 510, the online business is started. However, in the IPL processing of FIG.
Since the process 310 of FIG. 3 is not executed, the CPU units 100 and 110 of both the A and B systems have the caches 103 and 113.
Performs online operations using both ways 0 and 1.

Next, after a failure occurs in one of the CPU parts and the failure is recovered, the resynchronization reset is executed from the time when the re-installation of the CPU part is started, and the operation until the dual operation is restored. explain. Again, the B system CPU section 1
Assume that 10 has failed and has been disconnected from the system.

The B system CPU 110 can be replaced by hot line replacement.
When the repair is completed, the system console or the like issues a power-on to the B system CPU section 110. By this power-on issuance, the B system CPU section 110 causes the processes 501 → 502 → 503 → 504 → 505 → 506 → of FIG.
507 is executed. This is exactly the same as in the first embodiment. In this way, when the diagnosis / initialization of each unit is completed, the B system CPU unit 110 notifies the A system CPU unit 100 of the preparation for installation (process 506) and waits for the resynchronization reset issuance (process 507). ).

On the other hand, after the power-on issuance to the B system CPU unit 110, the A system CPU unit 100 periodically executes the operation of FIG. 6 while continuing the online business. First,
In process 600, it is determined whether the B system CPU unit 110 is ready for installation. The B system CPU unit 110 performs processing 506.
The determination of the process 600 is unsatisfied until the process is executed, and in this case, the A system CPU unit 100 returns to the online work as it is. When the determination in processing 600 is established, the A system CP
The U unit 100 executes the process 620, and the cache 103
The use prohibition of the specific way is set in the control register 201 in the cache control unit 102. Here, it is assumed that the entry of the way 0 of the cache 103 is set to be prohibited.

At this stage, the processing of FIG. 6 is temporarily interrupted, and the A system CPU section 100 uses the way 1 of the cache 103 to continue online work, while the task switching of the OS causes the processing of FIG. To execute.

In step 701 of FIG. 7, diagnosis and initialization of the cache way which is set to be prohibited in step 620 of FIG. 6 are executed for an appropriate number of entries. here,
The way 0 of the cache 103 is diagnosed and initialized by a predetermined number of entries. The number of entries may be set so as not to give overhead to the online business. Next, at decision 702, it is decided whether the diagnosis and initialization of the cache way have been completed. If it has not been completed, the process returns to the execution of the online work as it is, and then the process 701 is executed again by the task switching of the OS. As a result, the entry of the way 0 of the cache 103, which is prohibited in the process 620 of FIG. 6, is initialized little by little while continuing the online business. When the initialization of all the entries of the way 0 of the cache 103 is completed in processing 702, the A system CPU unit 100
Turns on the end flag in process 703. Next, in decision 704, it is determined whether or not the resynchronization reset is performed.
At this stage, since the dual operation has not been restored by issuing the resynchronization reset, the determination is NO.
Therefore, the process of FIG. 7 is once ended.

After the processing of FIG. 7 is completed, the A system CPU section 100 returns to the processing of FIG. 6 by the task switching of the OS, saves the processing information being processed in processing 611, and then executes processing 612.
Then, the resynchronization reset is issued to the inter-system control unit 120.

The inter-system control unit 120 is a system A CPU unit 100.
When the re-synchronization reset is issued, the end flag ON is confirmed, and the reset is issued simultaneously to the CPU units 100 and 110 of both the A / B system. Each CPU unit 100, 1 that has been reset
At the same time, 10 starts execution of the IPL process of FIG. In this case, the CPU units 100 and 110 process 501 → 502.
→ 508 → 509 is executed. Thereby, the processing 508
In the A system CPU section 100, the process 620 of FIG.
Although the way 0 of the cache 103 is prohibited, the way 1 of the cache 103 is set to be prohibited in the future. At this time, the B system CPU unit 110 also sets the way 1 of the cache 113, which is symmetrical to the A system, to be prohibited by referring to the status register of the intersystem control unit 120.

Next, in step 509, the process returns to step 613 in FIG. 6, and the A / B system CPU units 100 and 110
In the processing 613, the saved processing information is restored to return to the online business. At this time, the CPU units 100 and 110 of both the A / B system temporarily store the caches 103 and 1 for the time being.
Only way 0 out of 13 will be used to restart the online business. Here, A system cash way 0
, The diagnosis / initialization is guaranteed by the processes 701 to 703 of FIG. 7. Also, B system cash way 0
Has been diagnosed and initialized in the process 503 of FIG.

Next, CPU units 100 and 11 for both A and B systems
An operation will be described in which 0 uses only a part of the ways of the caches 103 and 113 and then restarts the online business, and then makes all the ways of the caches 103 and 113 available again.

After the resynchronization reset process is completed, the dual operation is restored, and the CPU units 100 and 11 of the respective A / B systems are restored.
0 executes the processing of FIG. 7 periodically between online tasks by switching the OS task. Here, when restarting the online business, the cache 10 of each A / B system
Ways 1 to 3 and 3 are prohibited. The entries of the way 0 of the caches 103 and 113 are simultaneously initialized little by little in the processing 701. It should be noted that the B-system cache 113 performs the processing 503 of FIG.
Since it has already been diagnosed and initialized, the B system CPU unit 11
In the processing 701 of 0, only temporary diagnosis / initialization (empty processing) is executed. That is, the B-system CPU unit 110 executes FIG. 7 simply for synchronization with the A-system CPU unit 100. In the processes 702 and 703, the caches 103 and 11
When the initialization of the way 0 of 3 is completed, the determination 704 is satisfied, and thus the processing 705 is executed. A / in process 705
The cache 10 is again stored in the control registers 201 of both systems.
Set permission to use 3, 113 ways 0. As a result, the CPU units 100 and 110 of the respective A / B systems start using all the ways of the caches 103 and 113.

[0045]

According to the first aspect of the invention, since the cache way whose use is prohibited remains in the initialized state, the IPL by the resynchronization reset for restoring the dual operation is performed.
Since the cache does not need to be initialized in the processing, the interruption time of online business etc. can be dramatically shortened.

According to the second aspect of the invention, as for the cache capacity of the processor, the capacity to be used is reduced only when the CPU section is re-installed, so that the system performance is improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of a computer system targeted by the present invention.

FIG. 2 is an internal configuration diagram of a cache control unit in FIG.

FIG. 3 is a flowchart of an IPL process according to the first embodiment of this invention.

FIG. 4 is a flowchart of a resynchronization reset process according to the first embodiment of this invention.

FIG. 5 is a flowchart of IPL processing according to the second embodiment of this invention.

FIG. 6 is a flowchart of resynchronization reset processing according to the second embodiment of this invention.

FIG. 7 is a flowchart of a cache way use permission process according to the second embodiment of this invention.

[Explanation of symbols]

 101, 111 Processor 102, 112 Cache control unit 103, 113 Cache 104, 114 Cache way 0 105, 115 Cache way 1 106, 116 Main memory 107, 117 ROM 120 for storing IPL processing Inter-system control unit

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Haruhiko Ohashi 1-13-2 Fukuzumi, Koto-ku, Tokyo Within Hitachi East Service Engineering Co., Ltd. (72) Inventor Mutsuhiro Yokoyama 1 Horiyamashita, Hadano, Kanagawa Stock Company Ritu Computer Electronics

Claims (2)

[Claims] 1. In a computer system in which a plurality of CPU units each having a cache execute the same processing in synchronization, a CPU unit separated from the system due to a failure or the like is re-installed in the system to restore synchronous operation. This is a synchronous reset processing method. At system startup, after initializing all cache ways of each CPU, disable a specific cache way, start synchronous operation, and re-install a certain CPU part in the system. For all CP
When U is reset and synchronous operation is restored, the use prohibition of the cache way is reversed, and the cache way that has been disabled and initialized so far can be used to restart the synchronous operation. Resynchronization reset processing method. 2. In a computer system in which a plurality of CPU units each having a cache execute the same processing in synchronization, a CPU unit separated from the system due to a failure or the like is re-installed in the system to restore synchronous operation. A method of synchronous reset processing, in which at the time of system startup, all cache ways of each CPU are enabled to start synchronous operation, and a CPU that is being processed in the preparation stage when a certain CPU unit is re-installed in the system The unit disables a specific cache way and continues the process, and periodically initializes the specific cache way by a predetermined number of entries between the processes, and the CPU unit in process processes the specific cache way. When the initialization of all ways is completed, all CPUs are temporarily reset to prevent the use of the cache way. Turn around,
After the initialization is completed, the specific cache way is enabled to restart the synchronous operation, and after the synchronous operation is restarted, the cache way that has been newly prohibited is periodically re-registered by a predetermined number of entries between processings. A resynchronization reset processing method characterized by initializing and reusing all cache ways when the initialization of all the cache ways is completed.