JPH09127919A - Active matrix type display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of address signal lines of a decoder circuit, reduce the occupancy area of a driving circuit, and reduce the cross talk between lines by selectively driving the signal lines of a matrix via the combination of multi-phase clock signals and the decoder circuit. SOLUTION: Four-phase clocks are divided into eight-phase clocks by a frequency dividing circuit 101 and fed to a decoder 103. The reference clock signal and the clock signal phase-shifted from it by 180 deg. are fed to a synchronization counter circuit 102, these clock signals are frequency-divided, and multiple signals are outputted. These signals are fed to a decoder 103 to select signal lines. The outputs of the decoder 103 are the logical products of the eight-phase clock signals and the outputs of the synchronization counter 102, and the signal lines connected to the outputs are selected when they are all turned on. An increase of the occupancy area caused by an increase of the number of lines is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type display device, and more particularly to an active matrix type display device incorporating a drive circuit.

[0002]

2. Description of the Related Art An active matrix display device is:
As shown in FIG. 2, pixels are arranged at each intersection of the matrix, and switching elements are provided in all the pixels, and the pixel information is controlled by turning on / off the switching elements. Liquid crystal is used as a display medium of such a display device. In the present invention, a three-terminal element, that is, a thin film transistor having a gate, a source, and a drain is used as the switching element.

A row in the matrix means that a scanning line (gate line) arranged in parallel to the row is connected to a gate electrode of a thin film transistor in the row, and a column is parallel to the row. The arranged signal line (source line) is connected to the source (or drain) electrode of the thin film transistor in the column. Further, a circuit for driving a scanning line is referred to as a scanning line driving circuit, and a circuit for driving a signal line is referred to as a signal line driving circuit. The thin film transistor is called a TFT.

FIG. 3 shows a first conventional example of an active matrix type liquid crystal display device. Here, 302 is
Amorphous TFT active matrix, 30
Reference numerals 1 and 303 are single crystal silicon drive circuit ICs.
The active matrix type liquid crystal display device of this example is a TFT
Using amorphous silicon, the scanning line drive circuit and the signal line drive circuit are composed of a single crystal integrated circuit, and are mounted around the glass substrate using tabs (see FIG. 3).
(A)) or COG (chip on glass) technology (FIG. 3B).

[0005] Such a liquid crystal display device has the following problems. One of the problems is that the signal lines and scanning lines of the active matrix are connected via tabs or bonding wires, which may cause reliability problems. For example, when the display device is a VGA (video graphic array), the number of signal lines is 1920 and the number of scanning lines is 480, and the number tends to increase year by year as the resolution increases. Further, in the case of making a viewfinder used for a video camera or a projector using liquid crystal, it is necessary to make the display device compact, which is a disadvantage in the space of the liquid crystal display device using the tab.

As an active matrix type liquid crystal display device that solves these problems, a device having TFTs made of polysilicon has been developed. An example is shown in FIG. As shown in this example, the signal line driving circuit 401 and the scanning line driving circuit 402 are formed simultaneously with the pixel TFTs on the glass substrate by using polysilicon TFTs. A polysilicon TFT is formed by a high temperature polysilicon process in which elements are formed on a quartz substrate by using a process of 1000 ° C. or higher.
There is a low temperature polysilicon process in which elements are formed on a glass substrate using a process of 00 degrees or less. Polysilicon T
FT has an amorphous TFT mobility of 0.5 cm2 /
It is about Vsec, but its mobility is 30 cm.
It can be set to 2 / Vsec or more, and can be operated with a signal of several MHz.

A drive circuit for driving the active matrix type liquid crystal display device has a digital system and an analog system.
However, since the number of circuit elements in the digital system is significantly larger than that in the analog system, the analog system is generally used in the drive circuit using polysilicon. There are two types of circuit configurations of the scanning line drive circuit and the signal line drive circuit, one using a shift register and the other using a decoder. First, a drive circuit using a shift register will be described. FIG. 5 shows a block diagram of the shift register.
As the shift register, a combination of a clocked inverter and an inverter to form a D-type flip-flop (hereinafter referred to as DFF) is often used. FIG. 6 shows an example of the DFF. Here, FIG. 6A shows the circuit configuration of the DFF, FIGS. 6B and 6D show the circuit configuration of the clocked inverter which is a component of the DFF, and FIGS. 6C and 6E.
Is the circuit configuration of the inverter, which is a component of the DFF. Also, not only those that use clocked inverters, but also those that use transmission gates.

Shift register, inverter type buffer,
A signal line driving circuit configured by combining transmission gates (hereinafter, TM gates) will be described with reference to FIG. A start pulse (SP) and clocks (CL, / CL) are input to the first stage of the shift register. FIG. 7 shows the block diagram (a) and the timing chart (b).
Is shown. 7A to 7F show waveforms at points A to F in FIG. 7A, and t1 to t8 represent time. Further, the periods t1 to t8 are 1/2 of the cycle of the clock pulse.
The start pulse changes from high to low in the period t1. At that time, since the clocked inverter 701 performs an inverter operation, the reverse phase of the waveform of the start pulse is A.
Appears in Further, the reverse phase appears in B.

In the period t2, the clock inverter 701 becomes inoperative, and the clock inverter 702
Operates as an inverter. As a result, in A, the last state of the period t1 is held and becomes low. Obviously, B shows the opposite phase of A, but this is the same as the last state of t1 and is high. Also, at t2, the clocked inverter 703 is in the operating state, and C is B
The low phase of B and the high phase of B of the same phase appear in D.

Next, in the period t3, the clocked inverters 701, 704, 705 are in the operating state and the clocked inverters 702, 703, 706 are in the inoperative state. At this time, B becomes low similarly to the input start pulse, D becomes high maintaining the last state of the period t2, and F becomes in phase with D, and thus becomes high. Next, in the period t4, the clocked inverters 701 and 70 are
4, 705 are inactive, and clocked inverters 702, 703, 706 are active. This causes B and D to go low and F to go high. In this way, the shift register using the DFF operates as shown in FIG. 5, and the signals are sequentially transferred.

The signals of the outputs B, D and F of the respective stages are inverter type buffers 710, 711, 712, 713 and 714.
It is transmitted to the TM gates 719, 720 and 721 via 715, 716, 717 and 718. The inverter type buffer is used to drive a large-sized TM gate transistor, and usually has a size ratio of about 3 times for each stage of the buffer. When the TM gate is turned on, the video signal line and the signal line in the matrix are short-circuited, and the video signal is written in the signal line. Since the signal line has a liquid crystal capacitance with the counter substrate inside the matrix, the written signal is held for the time until the next writing. When the capacitance between the liquid crystal and the liquid crystal is small, it is held by connecting a thin film capacitor.

As described above, the maximum operating frequency of the shift register is several MHz in the case of the polysilicon TFT drive circuit.
It is. However, in the case of VGA, since the reference clock frequency is 25 MHz, the signal cannot be used as it is. Also, XGA and EWS, which are higher standards of VGA, have higher frequencies, such as 50 MHz and 100 MH.
Of course, the polysilicon TFT drive circuit using the frequency of z cannot directly support these. Therefore, one of the following methods is usually taken to deal with it.

First, as the first method, as shown in FIG. 8, sampling switches 801, 802, 808, sampling capacitors 809, 810, 816, a buffer amplifier 81 are provided.
It is to attach a sampling circuit composed of 7, 818 and 824 to the outside. That is, the input video signal is sampled and held at high speed, time-divided, and then parallelized. FIG. 9 shows a timing chart when signals are taken in the case of VGA and countermeasures are taken. In the case of VGA, the video signal is a signal that changes in units of 40 nsec, which is shown in FIG. This signal is shown in FIGS.
Sampling is performed using the sampling signal shown in. As a result, signals such as those shown in FIGS.
By performing the above processing, the frequency could be reduced to 1/8. This method has an advantage that the number of stages of shift registers in the signal line drive circuit is reduced to 1/8, but on the other hand, an external sample and hold circuit is indispensable, which increases the external load.

The second method leaves the video signal untouched,
This is a method in which the internal shift register is divided into four, and the phases of the clocks supplied to the respective shift registers are shifted by ¼ for driving, and sampling is performed. in this case,
While it has the advantage of not requiring a sample and hold externally, it has the disadvantage of complicating the internal drive circuit. This is shown in FIG. In any case, the sampling time is 320 nsec.

Next, the scanning line drive circuit will be described.
The scanning line driving circuit is different from the signal line driving circuit in that the driving frequency is as low as 1/500 to 1/1000, and its output is passed through an inverter type buffer circuit.
Drive the scan line. The driving here is a binary output driving of high or low without using the TM gate unlike the signal line driving circuit. FIG. 11 shows its block diagram and timing. In FIG. 11, 1101 to 1106 are clocked inverters, 1107 to 1109 are inverters,
Reference numerals 1110 to 1118 denote inverter type buffers, and 111
9 to 1121 indicate NAND. Here, the clock frequency is about 16 KHz in the case of VGA. The operation of the shift register is similar to that of the shift register of the signal line driver circuit.

A drive circuit using a decoder will be described. Although the decoder circuit is logically composed of an AND circuit, a NAND and an inverter or a NAND and a NO are usually used because a NAND is easier to manufacture in manufacturing a semiconductor device.
Use R in combination. FIG. 12 shows an example in which the decoder is used in the signal line drive circuit. 1201 in FIG.
˜1203 are ANDs, 1204˜1212 are inverter type buffers, and 1213˜1215 are sampling analog SWs. The decoder circuit operates according to the input address signal to drive the necessary TM gate. Although not described here, the same applies to the case of being used for the scanning line driving circuit.

[0017]

The shift register system and the decoder system as described above have the following problems. In the shift register method, input pulses are sequentially transferred with a clock, so if an element failure occurs in a stage in the middle of the drive circuit, all the subsequent stages will be in operation failure, and it is easy to reduce the yield rate of the display device.
There is also a problem that the circuit configuration becomes complicated even when the drive circuit is made redundant.

The decoder system does not have the problem of the shift register, but has another problem as described below. As described above, a driving circuit using a polysilicon TFT has a problem in frequency response, and thus it is necessary to divide or use a multiphase clock. In the case of the decoder method,
As with the shift register, although there is a problem in that the number of externally attached devices increases with respect to division, it is possible, but it was difficult to realize multiphase clocking. For example, although there are 640 VGA signal lines, 10-bit address data is required if these are used without polyphase. Since two wirings are required for driving one bit for driving the decoder circuit, 20 wirings are required. On the other hand, if data is sampled in eight phases, 80 bits per phase and 7-bit address are required. That is, the total of 640 lines requires 56 times more data, which is 8 times as large as that of the 640 lines, which is 5 times or more as compared with the case where 8-phase sampling is not performed.
The number of wires is 112. This requires a large wiring area on the substrate, and has a problem in that crosstalk between the wirings and wiring delays due to mutual load capacitance occur.

[0019]

According to a first aspect of the present invention, in an active matrix type liquid crystal display device having a drive circuit for driving a signal line for supplying a display signal to pixels arranged in a matrix, the drive circuit is A dividing circuit for dividing and outputting the input multiphase clock signal, a synchronous counter circuit for dividing a part of the multiphase clock signal and outputting the divided input signal, and the dividing circuit The circuit and the output of the synchronous counter circuit are respectively input, and a decoder circuit for selecting a desired signal line based on these outputs is provided.

According to a second aspect of the present invention, the multiphase clock signal is passed through a level shift circuit for converting the amplitude,
It is inputted to each of the frequency dividing circuit and the synchronous counter circuit.

In the third aspect, the frequency dividing circuit or the synchronous counter circuit is composed of a thin film transistor.

Further, in the present invention, the frequency dividing circuit or the synchronous counter circuit is composed of a single crystal transistor.

According to a fifth aspect of the present invention, in the active matrix type liquid crystal display device having a drive circuit for driving a signal line for supplying a display signal to pixels arranged in a matrix, the drive circuit is input. A frequency dividing circuit for dividing and outputting a multiphase clock signal, a part of the multiphase clock signal is input, a synchronous counter circuit for dividing and outputting the input signal, and a division circuit A decoder circuit and a gate circuit that selectively supplies the outputs of the frequency dividing circuit and the synchronous counter circuit to each of the divided partial circuits. A desired signal line is selected based on the outputs of the frequency circuit and the synchronous counter circuit.

According to a sixth aspect of the present invention, the multi-phase clock signal is passed through a level shift circuit for converting the amplitude,
It is inputted to each of the frequency dividing circuit and the synchronous counter circuit.

In the seventh aspect, the frequency dividing circuit or the synchronous counter circuit is composed of thin film transistors.

In the eighth aspect, the frequency dividing circuit or the synchronous counter circuit is composed of a single crystal transistor.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION According to the present invention, a driving circuit divides a multi-phase clock signal input to a liquid crystal display device and outputs it, and a part of the multi-phase clock signal is input. It is composed of a synchronous counter circuit for dividing and outputting a signal and a decoder circuit for inputting the outputs of the frequency dividing circuit and the synchronous counter circuit and selecting a desired signal line based on these outputs.

As described above, the number of address signal lines of the decoder circuit can be reduced by selectively driving the matrix signal lines by combining the multi-phase clock signal and the decoder circuit.

For this reason, it is possible to reduce the area occupied by the drive circuit and the crosstalk between the lines, and it is possible to realize a higher quality display device.

[0030]

Embodiments of the present invention will be described below.
FIG. 1 is a block diagram of a drive circuit using the present invention.
In this example, a case where the present invention is applied to a VGA signal line drive circuit will be described. First, the sampling time is 320
The input clock signal is 3.125 MHz.
z four-phase clock signal. A timing chart of the input signal is shown in FIG. In FIG. 13, A is a reference clock, and B, C, and D are signals delayed by 40 nsec. These clocks are input to the frequency dividing circuit 101 that divides the frequency by two. Frequency divider circuit 1 used here
It is desirable that 01 has the same circuit configuration as that of the synchronous counter 102 described later, and that the delay due to the circuit is matched.

The input 4-phase clock is converted into an 8-phase clock signal of 1.563 MHz by the frequency dividing circuit 101 and is input to the decoder 103. The number of outputs is 16 depending on whether the signal polarity is positive or negative. These signals are changed from E to L. Further, the reference clock signal A and the clock signal whose phase is shifted by 180 degrees from the reference clock signal A are the synchronous counter circuit 1 of FIG.
02 is input. Here, those clock signals are divided into 781 KHz, 391 KHz, 195 KHz,
It outputs signals of 98 KHz, 49 KHz and 24 KHz. These signals are input to the decoder 103 to select a signal line. 6 frequencies here, 320 ns
ec with and without delay, plus / minus of polarity 2
There are 4 outputs. The AND of these is M,
N. The output of the decoder 103 is ANDed with the 8-phase clock signal and the output of the synchronous counter 102, and when all of them are turned on, the signal line connected to the output is selected. It is shown from O to V.

At this time, the address lines connected to the decoder 103 are 16 8-phase clock lines and the synchronous counter 102.
There are a total of 40 outputs of 24. Although this value is larger than that of the one that does not use the multi-phase clock, it can be reduced to about one-third that of the simple one.
As a result, it is possible to prevent an increase in occupied area due to an increase in the number of wires, a deterioration in signal content due to crosstalk between wires, and an increase in power consumption due to an increase in wire capacitance.

Next, FIG. 14 shows a second embodiment. In this example, the decoder circuit is divided into multiple groups,
Moreover, after the output of the frequency dividing circuit 1401, the gate circuit 140
3, 1404 are provided to selectively supply the clock to each group. Also, the gate circuits 1403, 1
404 is controlled by a synchronous counter circuit 1402,
In this example, AND of clock and control signal from counter
Has taken. By selectively supplying the high-frequency clock signal to the decoder groups 1405 and 1406 in this manner, it becomes possible to prevent unnecessary power. Other operations are the same as those in the first embodiment.

Next, FIG. 15 shows a third embodiment. In this example, a level shift circuit 1504 is attached to the inputs of the frequency dividing circuit 1501 and the synchronous counter circuit 1502 to perform amplitude conversion. This is because the threshold voltage of polysilicon is higher than that of single crystal when a circuit is constructed.
When the external signal is, for example, 5V, it is necessary to convert it to a voltage of 10V or higher. However, since the input part is loaded with the capacitance such as the input pin and the protection element, the power consumption in that part increases when inputting after external conversion. Therefore, in the present invention, the level shift circuit 1504 is incorporated to suppress power consumption in the input section. FIG. 16 shows an example of the level shift circuit. Here, in FIG. 15, the level shift circuit is added to the drive circuit of FIG. 1, but a similar level shift circuit may be added to the drive circuit of FIG. Other operations are the same as those in the first embodiment.

In the first and second embodiments, the frequency dividing circuit,
The synchronous counter circuit may be formed of polysilicon on a glass substrate, or a single crystal IC may be used. Hereinafter, a method for manufacturing a substrate of a liquid crystal display device using an active matrix circuit in this embodiment will be described.

The manufacturing process for obtaining the monolithic active matrix circuit of this embodiment will be described below with reference to FIG. This step is of a low temperature polysilicon process. The left side of FIG. 7 shows the manufacturing process of the TFT of the driving circuit, and the right side thereof shows the manufacturing process of the TFT of the active matrix circuit. First, as a base oxide film (1702) having a thickness of 1000 to 3000 on a glass substrate (1701).
A silicon oxide film of A was formed. As a method for forming this silicon oxide film, a sputtering method in an oxygen atmosphere or plasma CV is used.
The D method may be used.

After that, an amorphous silicon film of 300 to 1500 is formed by a plasma CVD method or an LPCVD method.
A, preferably 500-1000A. Then, thermal annealing was performed at a temperature of 500 ° C. or higher, preferably 500 to 600 ° C. to crystallize the silicon film or enhance the crystallinity. After crystallization by thermal annealing, optical (laser etc.) annealing may be performed to further enhance crystallization. Further, at the time of crystallization by thermal annealing, an element (catalyst element) that promotes crystallization of silicon such as nickel may be added as described in JP-A-6-244103 and 6-244104.

Next, the silicon film is etched to form the active layers (1703) (for P-channel TFT) and (1704) (for N-channel TFT) of the TFT of the island-shaped drive circuit and the TFT (pixel of the matrix circuit). TFT active layer (17)
05) was formed. Further, a gate insulating film of silicon oxide having a thickness of 500 to 2000 A was formed by a sputtering method in an oxygen atmosphere. As a method of forming the gate insulating film,
A plasma CVD method may be used. When the silicon oxide film is formed by the plasma CVD method, it is preferable to use dinitrogen monoxide (N2 O) or oxygen (O2) and monsilane (SiH4) as the source gas.

After that, aluminum having a thickness of 2000 to 6000 A was formed on the entire surface of the substrate by the sputtering method. Here, aluminum may contain silicon, scandium, palladium, or the like in order to prevent hillocks from being generated by a subsequent thermal process. Then, the gate electrode (170
7, 1708, 1709) are formed. (Fig. 17
(A)) Next, this aluminum is anodized. The surface of aluminum becomes aluminum oxide (1710, 1711, 1712) by anodic oxidation and has an effect as an insulator. (FIG. 17B)

Next, a photoresist mask (1713) covering the active layer of the P-channel TFT is formed. Then, phosphorus is injected by using an ion doping method with phosphine as a doping gas. The dose amount is 1 x 1012
It is 5 × 10 13 atoms / cm 2. As a result of this, strong N-type regions (source, drain) (1714, 1715)
Is formed. (FIG. 17C) Next, a photoresist mask (1716) covering the active layer of the N-channel TFT and the active layer of the pixel TFT is formed. Then, boron is implanted again by ion doping using diborane (B2 H6) as a doping gas. The dose amount is 5 × 10 14 to 8 × 10 15 atoms / cm 2. As a result of this, a P-type region (1717) is formed. By the above doping, a strong N type region (source, drain) (1714, 1715) and a strong P type region (source, drain) (1717) are formed.
(Fig. 17 (D))

Then, thermal annealing was performed at 450 to 850 for 0.5 to 3 hours to recover the damage caused by the doping, activate the doping impurities, and recover the crystallinity of silicon. After that, a silicon oxide film having a thickness of 3000 to 6000 A was formed as an interlayer insulator (1718) on the entire surface by a plasma CVD method. This may be a silicon nitride film or a multilayer film of a silicon oxide film and a silicon nitride film. Then, the interlayer insulator (1718) was etched by a wet etching method or a dry etching method to form contact holes in the source / drain.

Then, a thickness of 2000 is obtained by the sputtering method.
An aluminum film of 6000 A or a multilayer film of titanium and aluminum is formed. Etching this,
Peripheral circuit electrodes / wiring (1719, 1720, 172)
1) and electrode / wiring of pixel TFT (1722, 172)
3) was formed. (FIG. 17 (E)) Furthermore, plasma C
A silicon nitride film (1724) having a thickness of 1000 to 3000 A was formed as a passivation film by the VD method, and this was etched to form a contact hole reaching the electrode (1723) of the pixel TFT. Finally, the ITO (indium tin oxide) film having a thickness of 500 to 1500 A formed by the sputtering method is etched to form the pixel electrode (172
5) was formed. In this way, the peripheral drive circuit and the active matrix circuit could be integrally formed. (Fig. 17
(F))

[0043]

As described above, in the liquid crystal display device of the present invention, the signal lines of the matrix are selectively driven by combining the multi-phase clock signal and the decoder circuit.
It is possible to reduce the number of address signal lines in the decoder circuit, which reduces the occupied area of the drive circuit and the crosstalk between lines, enabling the realization of higher quality display devices. Has the effect of becoming.

[Brief description of the drawings]

FIG. 1 is a first embodiment of the present invention.

FIG. 2 is an example of an active matrix using a TFT.

FIG. 3 is a conventional example of an active matrix using an amorphous silicon TFT.

FIG. 4 is a conventional example of an active matrix using a polysilicon TFT.

FIG. 5 is a configuration diagram of a shift register.

FIG. 6 is a DFF, clocked inverter, and inverter circuit diagram.

FIG. 7 shows a case where a shift register is used.

FIG. 8 is an external sampling circuit.

FIG. 9 is a timing chart of an external sampling circuit.

FIG. 10 is a timing chart of a 4-phase clock system.

11A and 11B are a block diagram and a timing chart of a scan line driver circuit.

FIG. 12 is a block diagram of a decoder system signal line drive circuit.

FIG. 13 is a timing chart of the first embodiment of the present invention.

FIG. 14 is a block diagram of a second embodiment according to the present invention.

FIG. 15 is a block diagram of a third embodiment of the present invention.

FIG. 16 is an example of a level shift circuit.

FIG. 17 is an example of a manufacturing process of the present invention.

[Explanation of symbols]

101 Frequency divider circuit 102 Synchronous counter circuit 103 Decoder 301 Single crystal silicon drive circuit IC 302 Amorphous TFT active matrix 303 Single crystal silicon drive circuit IC chip 401 Signal line drive circuit 402 Scan line drive circuit 707-709 Inverter 701-706 Clocked inverter 710-718 Inverter type buffer 719-721 Sampling analog S
W 801, 802, 808 Sampling SW 809, 810, 816 Sampling capacity 817, 818, 824 Buffer amplifier 1107 to 1109 Inverter 1101 to 1106 Clocked inverter 1119 to 1121 NAND 1111 to 1118 Inverter type buffer 1201 to 1203 AND 1204 to 1212 Inverter Type buffer 1213-1215 Sampling analog S
W 1401 Frequency divider circuit 1402 Synchronous counter circuit 1403, 1404 Gate circuit 1405, 1406 Decoder group 1501 Frequency divider circuit 1502 Synchronous counter circuit 1503 Decoder 1504 Level shift circuit 1701 Glass substrate 1702 Underlying silicon oxide film 1703 to 1705 Silicon active layer 1706 Gate insulation Films 1707 to 1709 Al gate terminals 1710 to 1712 Anodized films 1713 and 1716 Photoresists 1714 and 1715 Strong N-type regions (source,
Drain 1717 Strong P-type region (source,
Drain) 1718, 1724 Interlayer insulating film 1719-1723 Al electrode 1725 Pixel transparent electrode

Front page continuation (72) Inventor Jun Koyama 398 Hase, Atsugi City, Kanagawa Prefecture, Semiconducting Energy Laboratory Co., Ltd.

Claims (8)

[Claims] 1. An active matrix display device having a drive circuit for driving a signal line for supplying a display signal to pixels arranged in a matrix, wherein the drive circuit divides an input multiphase clock signal. A frequency dividing circuit for dividing and outputting, a synchronous counter circuit for receiving a part of the multiphase clock signal and dividing and outputting the input signal, and an output of the frequency dividing circuit and the synchronous counter circuit, respectively. An active matrix type display device having a decoder circuit for selecting a desired signal line on the basis of these outputs which are input. 2. The active matrix type display according to claim 1, wherein the multi-phase clock signals are respectively input to the frequency dividing circuit and the synchronous counter circuit via a level shift circuit for converting amplitude. apparatus. 3. The frequency dividing circuit or the synchronous counter circuit,
The active matrix display device according to claim 1, wherein the active matrix display device comprises a thin film transistor. 4. The active matrix type display device according to claim 1, wherein the frequency dividing circuit or the synchronous counter circuit is composed of a single crystal transistor. 5. An active matrix display device having a drive circuit for driving a signal line for supplying a display signal to pixels arranged in a matrix, wherein the drive circuit divides an input multiphase clock signal. A frequency dividing circuit for dividing and outputting, a synchronous counter circuit for receiving a part of the multi-phase clock signal, dividing and outputting the input signal, and a decoder circuit divided into a plurality of partial circuits, A gate circuit that selectively supplies the outputs of the frequency dividing circuit and the synchronous counter circuit to each of the divided partial circuits is provided, and the partial circuit selectively supplies the frequency dividing circuit and the synchronous counter circuit. An active matrix type display device characterized in that a desired signal line is selected based on the output of the. 6. The active matrix type display according to claim 5, wherein the multi-phase clock signal is input to each of the frequency dividing circuit and the synchronous counter circuit via a level shift circuit for converting amplitude. apparatus. 7. The frequency dividing circuit or the synchronous counter circuit,
The active matrix type display device according to claim 5, wherein the active matrix type display device comprises a thin film transistor. 8. The frequency dividing circuit or the synchronous counter circuit,
The active matrix type display device according to claim 5, wherein the display device is composed of a single crystal transistor.