JPH09127913A - Display device and peripheral device thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a lightweight large-screen display device easy to assemble and disassemble and capable of being assembled on a curved surface by forming unit picture elements of a screen with LEDs emitting three primary colors: red, green, and blue, and contained in the same resin. SOLUTION: This display device is provided with the first red luminescent LED 1001, the second green luminescent LED 1002, and the third blue luminescent LED 1003, and all LEDs are connected to a control circuit 1004. A radio signal receiving antenna 1005 is connected to the control circuit 1004. A Vdd terminal 1006 and a GND terminal 1007 are connected to the outside of a package for the whole picture elements. The unit picture elements are formed with the LEDs emitting three primary colors: red (R), green (G), and blue (B), respectively and contained in the same resin, and each picture element is made independent and can be simply replaced for maintenance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device using LEDs. The present invention relates to a configuration and a manufacturing method for improving the performance and realizing a large screen of these display devices.

[0002]

2. Description of the Related Art Conventionally, a cathode ray tube has been used as a display device in such a field. FIG. 9 shows an outline drawing of a cathode ray tube type display device.

[0003]

A conventional display device using a cathode ray tube has a structure as shown in FIG.
There are the following problems. With the cathode ray tube method, the screen size can only be increased to about 40 inches. In addition, as the size of the cathode ray tube increases, the thickness and weight of the cathode ray tube also increase. As for assembly and installation, it is almost impossible to divide, move, and assemble at the installation site because it is almost a single body. Further, the cathode ray tube has no degree of freedom in the curved surface of the screen and has only a convex surface, and cannot have a free flat surface such as a concave surface type or a flat surface.

[0004]

In order to solve the above-mentioned problems, the present invention takes the following means. As a first means, a unit pixel having LEDs that respectively emit the three primary colors of red (R), blue (B), and green (G) in the same resin.

As a second means, the LED chip has a radio antenna. In addition, it is possible to use a common antenna for the entire display device without holding it in the chip. As a third means, it has a circuit for controlling light emission of three types of LEDs in the LED chip.

As a fourth means, a semiconductor circuit chip having a control circuit such as a radio RF, an ID check, a signal decoder, and an ID storage memory is provided in the control circuit.
As a fifth means, the semiconductor circuit chip sets a wide bandwidth so that the frequency band received by the antenna in the LED chip can be received by several kinds of frequencies.

As a sixth means, one LED chip forms one pixel. As a seventh means, LEDs
The chip has unevenness on the side surface, and the shape of the unevenness is the same in the package. As an eighth means, a side surface of the package has a Vdd terminal and a GND terminal.

As a ninth means, there is provided an ID address setting device for recognizing the address of the LED chip having the arranged random address ID. As a tenth means, the ID address setting device has a CCD as an image receiving portion, an image recognition and reference signal generating portion.

As an eleventh means, it has a display controller for sending a display signal to each pixel by radio waves. As a twelfth means, the display controller uses input signals (NTSC, M
USE, analog RGB signals, etc.), an input signal processing circuit, a decoder, an output signal generating circuit, an IDvs address correspondence memory circuit, an RF circuit, and a wireless antenna.

As a thirteenth means, in addition to the first means, the stem surface of the unit pixel is black, the panel wall structure is black, and the panel wall opening angle is 45 ° or less. is there. As a fourteenth means, it has an analog RGB signal input terminal and an NTSC signal input terminal.
A circuit block for converting an NTSC signal into an RGB signal is provided following the SC input terminal, and following the analog RGB input terminal and the circuit block for converting the NTSC signal into an RGB signal,
It has a signal discriminating automatic switcher circuit block section composed of a plurality of analog multiplexers, a vertical synchronizing signal separation circuit, and a video signal switch circuit, and a multi-sync PLL circuit block section following the signal discriminating automatic switcher circuit block section. And a white balance adjusting section, a plurality of channels of analog demultiplexer circuit section, and a plurality of channels of sample hold & row driver circuit section, following the signal identification automatic switching circuit block and the multi-sync PLL circuit block section. An LED display drive unit section including a LINE decoder circuit section and a column driver circuit section is provided, and R, which is connected to the row driver and the column driver,
The display unit has a configuration in which a plurality of pixels having LED chips of three primary colors of G and B in the same resin are arranged.

As a fifteenth means, a plurality of N-channel type M in which the sample hold & row driver circuits are arranged is provided.
It is composed of OS transistors. Here, the gate-source capacitance of the N-channel type MOS transistor is set to 200 PF or more, and the Vgs · Ids characteristics of each of the MOS transistors are within ± 10% of variation.

As a sixteenth means, in addition to the fourteenth means, a frame buffer circuit block section is provided between the signal identification automatic switcher block section and the LED display drive unit section.
In addition, the frame buffer circuit block unit includes R, G,
Flash with resolution of 8 bits or more for each B
A / D converter, a frame buffer following the A / D converter, and an E ² PRO following the frame buffer
The configuration is such that a correction value storage unit for M is provided, a comparison and correction value writing circuit unit is provided subsequently to the storage unit, and a display information input terminal is provided subsequently.

As a seventeenth means, in addition to the fourteenth means, a plurality of partial display device sections are assembled to form one whole display device (display). Here, the partial display device section is responsible for a divided part of the entire image, and the multi-sync PLL circuit block in the circuit of the partial display section is the screen. There is a means for inputting division information according to division, a means for storing the input information is provided, and the division information acts on the PLL circuit, and the circuit generates a partial scan and a partial scan generation multi-sync PL.
The L block unit is configured.

As an eighteenth means, in addition to the fourteenth means, a signal transmitter including a modulator, a transmission circuit and an antenna is provided in the preceding stage of the input signal, and an antenna is provided in the display device section. The configuration has a receiving circuit and a demodulator. As a nineteenth means, in addition to the fourteenth means, a pulse width modulation circuit section is provided between the display section of the display device circuit section and the frame buffer section. Here, each R of each unit pixel of the display unit
The GB LED is configured to have a constant current element in series.

As a twentieth means, in addition to the fourteenth means, the PLL circuit of the multi-sync PLL block section has a double loop structure. By taking the above means, the following effects can be obtained. By taking the first to third means, the LED can output all colors.

By taking the second to fourth means, it is possible to make the LED emit light wirelessly from a distance. 6th, 7th
By adopting the above means, a large flat screen can be obtained by simply combining the concave and convex portions of the package. By adopting the sixth and seventh means, it becomes possible to arrange them on a curved surface. By adopting the sixth and seventh means, the weight can be reduced regardless of the size of the screen and the thickness.
By adopting the sixth and seventh means, it is possible to easily disassemble, so that it is easy to move, assemble and install.

By adopting the eighth means, it is possible to connect Vdd (power supply) and GND simply by arranging the packages. By taking the ninth and tenth means, the IDs of the randomly arranged chips (one pixel) and the CCD camera can correspond to the read addresses on the screen.
By taking measures 11 and 12, NTSC, MUS
Data can be sent to each pixel using input signals of E, RGB, analog RGB, etc. as wireless signals.

By adopting the ninth to twelfth means, the correspondence between the ID and the address of each pixel can be stored in the memory of the display controller by connecting the ID address setter and the display controller. By generating an output signal based on this data, it is possible to accurately display an image on a large screen.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an example of the configuration of one pixel according to the first embodiment of the present invention. First red-emitting LED 1001
And a second green light emitting LED 1002 and a third timbre light emitting LED 1003.
Connected to 4. Further, a radio signal receiving antenna 1005 is connected to the control circuit. The entire pixel has a Vdd terminal 1006 and a GND terminal 1007, which can be connected to the outside of the package.

FIG. 2 shows an example of the configuration of the semiconductor circuit of the control circuit according to the first embodiment of the present invention. The RF 2001 receives a signal from the antenna 1005 which receives an external signal (radio wave). The received signal is checked by the ID stored in the ID memory 2002. Only the signal that matches the ID is converted into a signal by the signal decoder 2003, and the signal is sent to the timer circuit 2004 and the driver circuit 2005.
The timer circuit 2004 and the driver circuit 2005 are wired to the LED, and any LE can be transmitted by a signal sent from the timer circuit 2004 or the driver circuit 2005.
D emits light. Color, brightness, and tone adjustment are adjusted by this signal. Also, the entire control circuit is connected to Vdd terminal 1006 and GND.
It has a terminal 1007.

FIG. 3A is an example of an outline drawing of one pixel according to the first embodiment of the present invention. One pixel is a convex portion 3001, 300
2, two concave portions 3003 and 3004 are provided, and the convex portion 3
001 and 3002 and recesses 3003 and 3004 have the same shape. One convex portion 3001 and concave portion 3004 have a Vdd electrode portion 3005, and the remaining convex portion 3002 and concave portion have a 3003 GND electrode portion 3006. The surface of the package 3007 has a display portion 3008, and an LED 3009 is mounted in the display portion. As shown in FIG. 3B, the LED 3009 is GN on the back surface of the display portion 3008.
Connect to the D terminal, wire 30 from the surface of the display unit 3008
Wiring 3011 is connected to the signal line by 10 bonds. A milky white light scattering material is used for the display surface 3012. As shown in FIG. 3 (C), on the back surface 3013 of the package, I
A C package 3014 and an antenna 3015 are mounted, the antenna 3015 is connected to the IC package 3014, and the LED 3009 of the display surface area 3012 is connected to the IC package 3014. Desirably, the entire package is waterproofed.

FIG. 4 is an external partial view of a large screen showing the assembled state of the first embodiment of the present invention. Package 40
01 concave portions 3001 and 3002 and convex portions 3003 and 300
Build in a large screen by incorporating 4. Vertical 300-900 pieces,
The screen size can be increased to about 400 to 1200 horizontally.

Further, the Vdd terminal 4002 and the GND terminal 4
003, which is continuously connected to each pixel. FIG.
(A), (B) is a schematic circuit diagram showing the connection of the screen of the first embodiment of the present invention. The connection of the Vdd terminal 5001, the GND terminal 5002, and each pixel 5003 is shown.

FIG. 6 is an example of an outline drawing of the display controller of the first embodiment of the present invention. Input terminal 60 for input signal
01 and an antenna 6 for transmitting a display signal to each pixel
002. FIG. 7 is an example of an outline drawing of the ID address setting device of the first embodiment of the present invention. There is an image receiving unit 7001 with a CCD camera, and there is a code 7002 for sending data to the display controller.

FIG. 8 shows an example of the configuration of the display controller and the ID address setting device of the first embodiment of the present invention. The display controller 8001 first processes an input signal 8002 by an input signal processing circuit 8003, and then a decoder 8004.
The output signal is generated at. At this time, the data stored in the memory 8005 corresponding to the ID address is combined with the output signal. Finally, through the RF circuit 8006, the antenna 800
The display signal is sent from 7 to each pixel. The ID address setter 8008 receives the ID signal 801 from the decoder 8004.
Image recognition 8 with camera (CCD) 8009
The data corresponding to the 010 address is displayed and the data is displayed in the ID address correspondence memory 8 of the display controller 8001.
Send to 005. By performing this operation once for one screen, all correspondences between IDs and addresses can be taken.

FIG. 10 shows a display device according to the second embodiment of the present invention.
It is a circuit block diagram. Analog R
Has a GB signal input terminal 10001 and NTSC signal input
The terminal 10010 is provided, and the NTSC input terminal is followed by N
Circuit block 100 for converting a TSC signal into an RGB signal
09, the analog RGB input terminal and the NTSC
Following the circuit block that converts to RGB, multiple analog
GUX MUX (MPX) 1008 and vertical sync signal
Separate circuit (Vsync, Sep) 10012 and video signal
It consists of a switch circuit (VIDEO SW) 10013.
A signal identification automatic switcher circuit block unit 10014,
Following the signal identification automatic switching circuit block,
PLL (Phase Lo) for sync (multi-sync)
ck Loop) circuit block unit 10019,
Signal identification automatic switching circuit block and the multi-sync
White balance adjustment after the PLL circuit block for
Alignment section 10002 and 30^ch(Channel) analog demulti
Plexer circuit units 10015 and 30^chSample hold &
Row driver circuit unit 10016 and 4LINE to 10L
INE decoder (converts 4-bit data into data for 10 columns
Circuit unit 10020 and column driver (sink driver)
I / B, sync driver) circuit unit 10018
Includes ED display drive unit section 10003
Then, R, G, which are connected to the row driver and the column driver,
B3 primary color LED chip in the same resin
A display unit (display unit) 1001 having a number of arrangements
It has 7. Where 10011 is Sync
(Synchronous) signal line 10021 is a horizontal (H) address (A
address) 4-bit signal line, 1002
2 is a vertical address (V Address) 4-bit signal
Line 10023 is a horizontal synchronization (Hsync) signal line, 10
024 is a vertical cycle (Vsync) signal line, V_R1, V _R2,
V_R3Is white balance adjustment resistor, 1007 is video
The amplifier circuit is shown.

Here, for the sake of simplicity, the number of pixels is 10 ×.
Since the display of 10 = 100 pixels is shown as an example, the column driver has 10 lines and the row driver has 10 × 3 (R,
G, B) = 30 lines (30 channels, channels), but of course it is better to increase or decrease according to the required display quality (resolution), but the basic configuration of the circuit shown in this embodiment Does not change.

FIG. 11 is a circuit connection diagram of each pixel of the display section (display section) of the display device according to the second embodiment of the present invention.
11 is a circuit diagram of the actual contents of the display unit 10017 in FIG. Reference numeral 11001 indicates a unit pixel symbol, and the connector unit 11002 is a connection unit between the row driver 10016 and the column driver 10018.

FIG. 12A is a plan view of a display panel in which each unit pixel 12001 of the display unit of the second embodiment of the present invention is arranged. FIG.
It is AA 'sectional drawing of (a). FIG. 13 shows a unit pixel 13001 of the display unit of the display device according to the second embodiment of the present invention.
2 is a connection diagram of the LED chip of FIG. One R (red) LED chip and one B (blue) LED chip are used, and two G (green) LED chips are used in series and incorporated in the same resin.

FIG. 14 is a sectional view of a unit pixel of the display section of the display device according to the second embodiment of the present invention. LED chips of each three primary colors (R, G, B) are the same transparent resin 1400
3 (semi-transparent, milky white or the like may be used to scatter light: diffusing agent), and the black stem surface material 14
It is fixed to the stem (base) 14005 via 006. The panel wall structure 14004 is also black, and the opening angle 14001 is 45 ° or less. Thus, by making the surface of the stem and the surface of the panel wall structure black, the dark color can be displayed darkly. Further, by setting the opening angle to 45 ° or less, the dependence of the brightness on the viewing angle is reduced.

15 to 21 are detailed circuit diagrams showing the contents of the LED display drive unit portion of the display device according to the second embodiment of the present invention. In FIG. 16, 15001 is 11002.
Is a connector part connected to. In FIG. 20, white balance is performed by the variable resistors (volumes) V _R1 , V _{R3, and} V _R5 of the white balance adjusting unit 10002. FIG.
30 ^ch analog demultiplexer unit 10015 of 9 and sample hold & row driver unit 1001 of FIGS.
Horizontal driving unit consisting of 6 performs an operation for driving the LED with a pulse of 5 [mu] _sec from the analog multiplexer holds the sample and hold & row driver section 10016 is 14 times longer. Since the crest value of the pulse given here is analog driving (not duty driving) that determines brightness and the like, the gradation is stepless in principle (capacity of 10 bits or more) in principle, and the sample hold time. ^Is 14 times, which is a sufficiently long time for 10 ^{ch of the} column drive, and static drive is performed. Therefore, unlike the dot-sequential scanning, the structure without the frame buffer does not cause deterioration in display quality such as a decrease in brightness and the appearance of scanning synchronization unevenness. If the number of pixels increases, the hold time may be lengthened. Number of column lines x 1.
It should be 4 times or more.

The column driver, which is the vertical driving unit, is dynamic driving, but when the number of pixels is increased or when this unit takes charge of a divided portion of the entire screen as will be described later, a decrease in brightness is scanned. If it is desired to prevent the unevenness from being visible, the column driver may have a sample-hold circuit, and may be statically driven, although the figure is the same as that of the horizontal driving unit. The hold time is set according to the number of pixels and the number of divisions. Then, a completely static operation is performed, and for example, the scanning synchronization unevenness that is visible when a TV screen is photographed by a TV camera is completely eliminated, and a very high quality screen can be obtained. In this embodiment, when the horizontal direction is static drive and the vertical direction is dynamic as shown in FIGS.
The drive current value of the LED is 80-100 mA per unit pixel at the peak (R: G: B = 3: in the ratio of RGB).
Although it is set to 7: 3), the current value is 1/10 of that on average because the column side is 10 ch dynamic. If the number of pixels is increased as it is and there is a concern about a decrease in brightness, the peak current value setting may be increased. In that case, if the column side is still dynamic, the average current will not increase. In terms of bodily sensation, this setting does not give a strange feeling up to about 100 x 100 pixels. On the other hand, as mentioned above, when static drive is performed on both sides, the average current will increase to a tremendous value, but since it is static this time, the perceived brightness will greatly increase, so conversely the peak current should be lowered. It will be. In any case, it is important to make settings according to the number of pixels, the number of divisions, the usage environment (outdoor or indoor, etc.) and the perceived brightness. In any case, what is new in the present invention in the LED display drive unit is that static display having a sample hold is provided at least in the horizontal direction in a display using RGB three-primary-color LEDs as pixels. Is an analog value (not a duty).

22 and 23 show a multi-sync PLL (Phase Lock Lo) of the display device according to the second embodiment of the present invention.
(op) It is a detailed circuit diagram showing the contents of the block part. As can be seen from the circuit, the original oscillation frequency before frequency division that locks the vertical synchronizing signal that is input is 1500 Hz, and the original oscillation frequency before frequency division that locks the horizontal synchronization signal that is input is 600 kHz. The input video signal is locked and then taken out by the presettable counter (the taken-out original vibration portion is taken out). By doing this, it is possible to synchronize any video signal with a synchronization signal (multi-sync specification) and display it on the display. With this configuration, it is possible to operate in the range of vertical 55 to 150 Hz and horizontal 12 k to 60 kHz. In this multi-sync, the P
The point is to have an LL circuit and keep the original vibration at 10 times or more the maximum frequency of the assumed input signal.

24 and 25 are detailed circuit diagrams showing the contents of the signal identification automatic switching unit block portion of the display device according to the second embodiment of the present invention. In this configuration, the NTSC signal is prioritized. 26 and 27 are detailed circuit diagrams showing the contents of a circuit block for converting an NTSC signal into an RGB signal in the display device according to the second embodiment of the present invention.

As described above, by adopting the circuit configuration and the configuration of the display section as in this embodiment, it is possible to realize a display device of high performance and low cost which has never been achieved. FIG. 28A is a circuit diagram showing a sample hold & row driver section of the display device of the third embodiment of the present invention. Second
In the case of the display device described in the embodiment, the sample hold & row driver circuit is 10016 in FIGS.
As shown in FIG. 5, the LED has an operational amplifier, an NPN transistor, and an emitter follower drive of the LED via a series resistor for feedback, but this embodiment is improved.

The analog demultiplexer 100 of FIG.
Analog demultiplexer similar to 15 (R, G, B)
The output from 19001 is an arrayed N-channel MOS
IC composed of transistors (transistor array)
Hit the gate (G) of each transistor, and the output from the sword (S) is the series resistance Rs (19002).
The LED 19003 is driven (source follower) via (this may be omitted). D in the figure
Indicates a drain. In other words, sample hold function and LE
The N-channel MOS transistor fulfills both of the D drive functions.

What is important here is that the N-channel MO
The parasitic capacitance between the gate (G) and the source (S) of the S transistor [FIG. 28 (b), 19005] is 200 PF or more. The required capacity may be secured by the structure of the gate insulating film, or the junction capacity of a diode or an off type MOS transistor for electrostatic breakdown may be used. Further, each Vgs · Ids of the arranged N-channel type MOS transistors is
It can be mentioned that the characteristics (characteristics such as voltage dependency of drain current at gate, drivability, K value, gm, etc.) must be within ± 10%.

FIG. 28B is a symbol diagram showing a unit MOS transistor of the MOS transistor array IC in the sample hold & row driver section of the display device according to the third embodiment of the present invention. As described above, the MOS of this embodiment
By using the transistor array IC for the sample hold & row driver section, it is possible to realize a display device having a small, simple and low cost LED display drive unit section.

FIG. 29 is a block diagram of a circuit portion showing a display device according to the fourth embodiment of the present invention. In addition to the circuit of the display device described in the second embodiment, a frame buffer circuit block unit 20001 is provided between the signal identification automatic switching unit block unit 10014 and the LED display drive unit unit 10003. is there.
This frame buffer circuit block unit 20001 has R,
It has an 8-bit flash A / D converter 20003 for each of G and B, a frame buffer 20002 following the A / D converter, and a D / A converter 2004 following the frame buffer, A correction value storage unit (E ² PROM) 2005 is provided following the frame buffer, and a comparison and correction value writing circuit unit 200 is provided subsequent to the storage unit.
06, followed by a display information input terminal 20007 to which an NTSC signal (in this case, an RGB decoder circuit section is also required) or an RGB signal is input. When the number of pixels in the display unit increases or the number of screen divisions (described later) increases, there is a concern that the brightness decrease and the scanning synchronization unevenness may be visible as described above.
In addition to that, in the pixel at the end opposite to the end of the display portion, there is a concern that a difference in series resistance due to the length of the wiring may appear as a difference in brightness.

However, according to the present embodiment, as described in the first embodiment, the main body is now recognized and displayed by photographing the display with, for example, a CCD camera and inputting it (from the input terminal 20007). If there is a difference, calculate a value to correct it, give the correction value once to the frame buffer and compare the display again. If OK, the correction value storage unit (E ² PROM) Stored in 20005 (the comparison and correction value writing circuit 20006),
After that, until the display information is input again, the operation is continued with the correction value that was OK. By doing so, the above concern is eliminated.

30 (a) and 30 (b) are schematic plan views of the display section showing the display device of the fifth embodiment of the present invention. The display portion of the display device as described in the second to fourth embodiments corresponds to a portion A (21002) in the drawing.
For example, nine such parts are collected to form the entire display (display unit) 21001.

In FIG. 30B, the part B (21004) is 1
A total of 00 pieces constitutes the entire display portion 21003. FIG. 31 is a block diagram of a circuit portion showing a display device of the fifth embodiment of the present invention. The feature of this embodiment is that a plurality of display units are assembled to form one display (display) as described above. The part and the display part of the part are in charge of the divided part of the entire image. So far, the second to fourth embodiments
Among the circuits described up to the embodiment, the multi-sync PL
The L circuit block is configured as shown in FIG.

That is, in addition to the above-described configuration, it has an input section 22002 which is a section for inputting division information (such as coordinates) corresponding to the screen division, and a division area corresponding to the information which acts on the PLL circuit. Address setting means (Dip S
This means that there are provided a plurality of display devices each having a partial scan generation multi-sync PLL block section 22001 having a storage means (such as W or E ² PROM) 22003.

The split screen method itself may have existed in the past, but since the original image signal was divided into parts and parts were given, there were multiple circuits and synchronization deviations occurred between parts and parts. However, the divided portion, and the divided portion have the partial scan generation multi-sync PLL circuit block, so that N is given to the entire screen.
A single image signal such as TSC is improved, and further, there is no fear of synchronization deviation, and a high-quality display device can be realized. Now, for example, assuming that each partial display device has unit pixels at a pitch of 10 mm in the vertical direction × the horizontal direction = 24 pixels × 32 pixels (dots), the total size of 72 cm × 96 cm is 9 divisions as shown in FIG. 72 × 9
The display has a resolution of 6 dots. This is NTSC or V
GA full-grade display is difficult, but it can be said to be sufficient for outdoor advertisement display and timekeeping display on the stadium. On the other hand, similarly, if the same size is divided into 100 parts as shown in FIG. 30B, the total size is 240 cm × 320 cm, which is 240 × 320.
The dot resolution is displayed. This is NTSC
Is enough, and if it is VGA (personal computer level) grade, the number of divisions should be increased a little more.
This makes it very suitable for display in halls and meetinghouses.
In other words, the relay display of the TV screen in the indoor hall, the seminar,
It can be said that it is suitable for display instead of OHP and slides at lectures. In the method in which the LED chip of RGB three primary colors of the present invention enclosed in the same resin is used as a unit pixel, the cost per pixel unit is inevitably inferior to the cathode ray tube, the liquid crystal, or the PDP (plasma) system. There is no point in attempting to increase the resolution per area. On the other hand, in a super-large screen display such as Astrovision ^TM in a baseball field, each unit pixel is a cold cathode ray tube or a cathode ray tube, and the pitch per unit pixel is as large as several cm to several tens of meters. Luminance is also required, and the unit pixel area of the system of the present invention is 1 for the LED chip.
It is less than mm square, and even if it is spread with a light diffusion material, it is several cm
Is the limit.

Since a plurality of unit pixels are provided for each unit pixel, the cost is not comparable to that of a cold cathode tube or a cathode ray tube. Therefore, the pitch of the unit pixel of the present invention is in the range of 5 mm to 20 mm, and the number of dots is at most 10 × 10
The above-mentioned methods and applications (small size, low resolution advertisement display, timekeeping display, large size, high resolution hall, etc.) in which one unit division panel is configured with 0 dots and the size and resolution are determined by combining them TV display) is the most suitable. Another advantage of the present invention is that it has the above-mentioned divided area address setting function, so that even in the panel (display device) used for a certain timekeeping display, when the event ends, the area setting is changed to make it larger and higher. It can be used for resolution. Since it is divided, it is easy to install and remove and carry.

It is advantageous to prevent the occurrence of jitter by further forming the PLL circuit into a double loop structure. In that case, it is more effective when the number of pixels is increased or the number of divisions is increased. 32 is a block diagram of a circuit portion showing a display device of a sixth embodiment of the present invention. In addition to the display device circuits described in the second to fifth embodiments, the input signal 23002, that is, NTSC,
Modulator 2 in front of R, G, B, Vsync, Hsync
3010 and transmission circuit (TX circuit) 23006 and CH1
A signal transmitter 23001 consisting of three channels of CH3 (this is necessary) and an antenna 23004 is interposed, and is included in the display device portion 23003 to include an antenna 2300.
7, a receiving circuit (RX circuit) 23008, and a demodulator 2300
9 is adopted. In short, whatever the input signal is, it will fly to the display device of the present invention by radio waves. As a radio wave, carrier 100M ~
At around 400 MHz and a band around 6 MHz, FM modulation would be suitable. In terms of electric power, it is convenient to use a weak area because it has a high degree of freedom. Weakness will suffice without the need for remote operation. In consideration of noise resistance, the SS (spread spectrum) method may be used. In short, for example, the display near the ceiling of a hall does not have to have many kinds of signal values.
It means that only the power line should come. Fifth
It is most effective in the case of the division method as described in the embodiment (in other words, this method is the most realized and effective in the present invention). This is because it is not necessary to have a signal line for each panel. This is because even if the number of divisions is large, only one wave is required (though RGB may require three channels 23005).

FIG. 33 is a block diagram of a circuit portion showing a display device of the seventh embodiment of the present invention. This is an example in which the PWM circuit unit 24002 (pulse width modulation circuit unit) is provided between the display unit 10017 and the frame buffer unit 24001 of the display device circuit described so far in the second to sixth embodiments.

FIG. 34A shows the PWM of the seventh embodiment of the present invention.
It is a figure which shows a wave pattern. FIG. 34B is an equivalent circuit showing a unit pixel of the display device of the seventh embodiment of the present invention. In the present invention, the LED driving has been described so far as analog driving (not duty driving), but this is an example of duty driving, that is, PWM driving. The PWM drive (pulse width modulation) is to change the brightness with the drive pulse width W as shown in FIG. In the case of this method, unlike the analog driving, a correction coefficient called a crest fighter in the luminance vs. pulse width characteristic had to be provided in the frame buffer and corrected while driving. In addition, when trying to correct the difference in series resistance between pixels on the display surface, it is necessary to have correction data depending on the position, which makes the control very complicated. Therefore, in the present invention, the analog drive has been described so far. However, in each pixel, as shown in FIG.
With the configuration in which a constant current element is inserted in series with 2, the correction due to the difference in series resistance between the pixels on the display surface becomes unnecessary, and the PWM driving has become practical. This is because the constant current element causes a constant current to flow in a certain range regardless of the applied voltage.

[0049]

As described above, the display device using the LED and the peripheral device can realize a large-screen display device which is lightweight, easy to disassemble and assemble, and can be assembled even on a curved surface. In addition, since each pixel is independent, maintenance is very simple, just replacing the pixel.
The present invention is also effectively applied to landscape lighting, station platforms, sidewalks, and gravel lighting in parking lots, etc. The image is clear even in a magnetic field because it is not electron beam scanning unlike the conventional cathode ray tube. The radio waves may be transmitted (scanned) with ID data and display data at a plurality of frequencies, or may be encoded by TDMA or CDMA system and transmitted to further multiplex, resulting in higher scanning speed and easy HDTV compatibility. Become. Each pixel has a PIN diode having a sensitivity to infrared rays and a signal processing circuit thereof instead of the receiving antenna, and it is more convenient for the signal transmission unit to send data by infrared rays instead of radio waves.
In this case, the influence of other electric and magnetic fields can be completely eliminated.
Of course, the fact that the scanning speed is increased by multiplexing is
It is also effective in the case of radio waves. Red on the emitting side of each pixel,
In addition to the green and blue LEDs, put the infrared light emitting diode,
It is also convenient to superimpose it on an ordinary image to display other image data (subtitles, subliminal effects, harmful bird and beast elimination), and to use for highly parallel optical communication. It is also convenient to use for car taillights, etc.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a configuration example of one pixel according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a configuration example of a semiconductor circuit of the control circuit according to the first exemplary embodiment of the present invention.

FIG. 3 is an explanatory diagram showing an example of a one-pixel outline drawing of the first embodiment of the present invention.

FIG. 4 is a partial external view showing how the first embodiment of the present invention is assembled.

FIG. 5 is a schematic circuit diagram showing a connection state of the first embodiment of the present invention.

FIG. 6 is an example of an outline drawing of the display controller according to the first embodiment of the present invention.

FIG. 7 is an example of an outline drawing of an ID address setting device according to the first embodiment of the present invention.

FIG. 8 is a display controller and ID according to the first embodiment of the present invention.
It is explanatory drawing which shows the structural example of an address setting device.

FIG. 9 is an external view of a conventional CRT type display device.

FIG. 10 is a circuit block diagram showing a display device of a second embodiment of the present invention.

FIG. 11 is a circuit connection diagram of each pixel of the display section (display section) of the display device according to the second example of the present invention.

FIG. 12 is a plan view of a display panel in which unit pixels 12001 of a display unit of a display device according to a second exemplary embodiment of the present invention are arranged.

FIG. 13 is a wiring diagram of an LED chip of a unit pixel 13001 of a display unit of a display device according to a second exemplary embodiment of the present invention.

FIG. 14 is a cross-sectional view of a unit pixel of a display unit of a display device according to a second exemplary embodiment of the present invention.

FIG. 15 is a detailed circuit diagram showing the contents of the LED display drive unit portion of the display device according to the second embodiment of the present invention.

FIG. 16 is a detailed circuit diagram showing the contents of the LED display drive unit section of the display device of the second embodiment of the present invention.

FIG. 17 is a detailed circuit diagram showing the contents of the LED display drive unit portion of the display device according to the second embodiment of the present invention.

FIG. 18 is a detailed circuit diagram showing the contents of the LED display drive unit portion of the display device according to the second embodiment of the present invention.

FIG. 19 is a detailed circuit diagram showing the contents of the LED display drive unit portion of the display device according to the second embodiment of the present invention.

FIG. 20 is a detailed circuit diagram showing the contents of the LED display drive unit portion of the display device according to the second embodiment of the present invention.

FIG. 21 is a detailed circuit diagram showing the contents of the LED display drive unit section of the display device of the second embodiment of the present invention.

FIG. 22 is a detailed circuit diagram showing the contents of a PLL (Phase Lock Loop) block unit for Malsync of the display device according to the second embodiment of the present invention.

FIG. 23 is a detailed circuit diagram showing the contents of a PLL (Phase Lock Loop) block portion for a malsync in the display device in the second embodiment of the present invention.

FIG. 24 is a detailed circuit diagram showing the contents of the signal identification automatic switcher block section of the display device of the second embodiment of the present invention.

FIG. 25 is a detailed circuit diagram showing the contents of the signal identification automatic switcher block section of the display device of the second embodiment of the present invention.

FIG. 26 is a detailed circuit diagram showing the contents of a circuit block for converting an NTSC signal and an RGB signal in the display device of the second embodiment of the present invention.

FIG. 27 is a detailed circuit diagram showing the contents of a circuit block for converting an NTSC signal and an RGB signal in the display device according to the second example of the present invention.

FIG. 28 is a circuit diagram showing a sample hold & row driver section of a display device according to a third example of the present invention.

FIG. 29 is a block diagram of a part of a circuit diagram showing a display device of a fourth embodiment of the present invention.

FIG. 30 is a schematic plan view of a display unit showing a display device of a fifth embodiment of the present invention.

FIG. 31 is a block diagram of a circuit portion showing a display device of a fifth embodiment of the present invention.

FIG. 32 is a block diagram of a circuit portion showing a display device of a sixth embodiment of the present invention.

FIG. 33 is a block diagram of a circuit portion showing a display device of a seventh embodiment of the present invention.

34 (a) and 34 (b) are PWs of a seventh embodiment of the present invention.
It is a figure which shows the M waveform and the equivalent circuit showing the unit pixel of a display apparatus.

[Explanation of reference numerals] 1001 red light emitting LED 1002 green light emitting LED 1003 blue light emitting LED 1004 control circuit 1005 antenna

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshie Ozaki 1-6-19-207 Takaban, Meguro-ku, Tokyo (72) Inventor Toshiaki Narukawa 2-41-8-203 Unoki, Ota-ku, Tokyo (72) ) Inventor Tsutomu Ota 40-1-12-405 Honshiki, Makishima-cho, Uji-shi, Kyoto (72) Inventor Yogo Tanabe 503 Greeneheim Kishine Park B101, Kishine-cho, Kohoku-ku, Yokohama-shi, Kanagawa Prefecture

Claims (24)

[Claims] 1. A display device using LEDs, each of which emits three primary colors, red, green, and blue.
Which is included in the same resin to form one pixel of a screen. 2. A radio antenna is provided on the periphery of the chip or on the back surface of the chip to control the light emission of three-color LEDs of each chip by an external signal to display in color. Display device. 3. RF around the chip or on the back surface of the chip
And ID check, signal decoder and EPR for ID memory
3. The display device according to claim 1, further comprising a control circuit including an OM. 4. The chip, the control circuit, and the antenna are
The display device according to claim 3, wherein the display device is packaged in a package having a convex portion and a concave portion on a side surface. 5. The display device according to claim 4, wherein each of the packages has a Vdd terminal and a GND terminal at two locations on a side surface of the package. 6. The display device according to claim 4, wherein the recesses and the protrusions of the package are combined by arranging the packages vertically and horizontally to form a large screen. 7. The packages are arranged vertically and horizontally so that the Vdd terminal is Vdd between adjacent packages.
The display device according to claim 4, wherein the terminal has a structure capable of being connected to the GND terminal, respectively. 8. A peripheral device of a display device having a display controller for transmitting an image signal to each pixel of the display device formed by a vertically and horizontally arranged package through an antenna. 9. The display device according to claim 8, wherein the display controller processes an image signal from the outside, converts the image signal into an output signal, and sends the signal from the antenna by radio waves through a PF circuit. Peripherals. 10. The display controller has an ID address correspondence memory for storing the correspondence between the ID of each pixel randomly arranged and the address in the entire screen, whereby an accurate signal is sent to each pixel. 9. The peripheral device for a display device according to claim 8, wherein the peripheral device is adapted to be capable. 11. The display device according to claim 1, further comprising an ID address setting device for associating an ID of each pixel arranged at random with an address in the entire screen. 12. The ID address setter is connected to a display controller, a signal is sent from the display controller to each pixel, and an image by a pixel emitted according to the signal is recognized by a CCD camera, and a screen is displayed. 9. The peripheral device for a display device according to claim 8, wherein an address in the whole is calculated. 13. The address determined by the ID address setter is sent as a signal to the display controller and stored in a memory corresponding to an ID address in the display controller. Peripheral device for display device. 14. The surface of the stem of the unit pixel is black,
The panel wall structure is black, and the panel wall opening accuracy is 45.
The display device according to claim 1, wherein the display device has a temperature of not more than °. 15. The display device according to claim 1, wherein an array pitch interval between the arrayed unit pixels is a distance between 5 mm and 20 mm. 16. An analog RGB signal input terminal is provided,
An NTSC signal input terminal, a circuit block for converting the NTSC signal into an RGB signal following the NTSC input terminal, and a plurality of analogs following the RGB input terminal and the circuit block for converting the NTSC into RGB. A signal discriminating automatic switcher circuit block section comprising a multiplexer, a vertical cycle signal separating circuit, and a video signal switch circuit, and a multi-sync PLL circuit block section following the signal discriminating automatic switcher circuit block section; Following the signal identification automatic switching circuit block and the multi-sync PLL circuit block section, a white balance adjusting section, a plurality of channels of analog demultiplexer circuit section, a plurality of channels of sample and hold & row driver circuit section, and a LINE decoder circuit section LED display drive unit including a column driver circuit unit And a display unit having a plurality of unit pixels arranged in the same resin and having LED chips of R, G, and B3 primary colors connected to the row driver circuit unit and the column driver circuit unit. Display device. 17. The N-channel type MO transistor comprising a plurality of N-channel type MOS transistors in which the sample hold & row driver circuit section is arranged.
17. The display device according to claim 16, wherein the S-transistor has a gate-source capacitance of 200 PF or more, and the Vgs · Ids characteristics of each of the N-channel MOS transistors are within a variation range of ± 10%. . 18. A frame buffer circuit block portion is provided between the signal identification automatic switcher block portion and the LED display drive unit portion, and the frame buffer circuit block portion is provided for each of R, G and B. The flash A / D converter having a resolution of 8 bits or more is provided, the A / D converter is followed by a frame buffer, and the frame buffer is followed by a correction value storage section by an E ² PROM. 17. The display device according to claim 16, further comprising a comparison and correction value writing circuit unit following the value storage unit, and a display information input terminal following the value storage unit. 19. A multi-sync PLL circuit block in a circuit of each of the display devices is characterized by comprising a plurality of the display devices, each display device displaying a divided portion of an entire image. It has means for inputting division information such as coordinates according to the screen division, and means for storing the input information, the division information acting on the PLL circuit,
17. The display device according to claim 16, wherein the LL circuit constitutes a partial scan generation multi-sync PLL block unit for generating a partial scan. 20. A signal transmitter comprising a modulator, a transmission circuit, and an antenna in a stage preceding the input signal, and the display device section has an antenna, a reception circuit, and a demodulator. Item 16. A display device according to item 16. 21. An LED for RGB of each unit pixel of the display unit, comprising a frame buffer, and a pulse width modulation circuit unit between the display unit of the display device and the frame buffer. 16. The display device according to claim 16, wherein the constant current element has a constant current element in series. 22. The display device according to claim 16, wherein the PLL circuit of the multi-sync PLL block unit has a double loop configuration. 23. The display device according to claim 19, wherein the PLL circuit of the PLL block unit for multi-sync has a double loop configuration. 24. A plurality of N-channel type MOS transistors arranged in the same semiconductor substrate, wherein the N-channel type MOS transistor has a gate-source capacitance of 200.
A semiconductor device having a PF or more and having a Vgs · Ids characteristic of each N-channel MOS transistor within a variation range of ± 10% or less.