JPH09127205A - Measuring method for access time - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a measuring method in which the accuracy of an access time measurement is enhanced. SOLUTION: On the basis of the difference between the timing of a clock signal CK0 at a time when the clock signal CK0 is delayed in a very small time unit and when a target signal state is latched by an SM latch circuit 11 and the timing of a clock signal CK1 at a time when the clock signal CK1 is delayed in a very small time unit and when a target signal state is latched by an SM latch circuit 12, the difference in an electric length between conductive lines L1, L3 at the outside of an LSI 15 is found regarding the clock signals CL0, CK1. When the difference in the electric length is corrected, an error in an access time measurement due to the difference in the electric length is reduced, and the accuracy of the access time of an SRAM part 13 is enhanced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for measuring an access time of a semiconductor memory device, for example, a technique effectively applied to an access time measurement of a static random access memory (SRAM).

[0002]

2. Description of the Related Art SRAM as an example of a semiconductor memory device
Includes a memory cell array in which a plurality of static memory cells are arranged in a matrix. Select terminals of the static memory cells are connected to word lines in each row direction, and data input / output terminals of the memory cells are connected to complementary data lines in each column direction. Each complementary data line is
It is commonly connected to the complementary common data line via a column switch circuit including a plurality of switches coupled to the complementary data line in a one-to-one relationship. The address signal input from the outside is transmitted to the row decoder and the column decoder.
The word line is driven to the selection level based on the decode output of the row decoder, and the column selection switch is turned on based on the decode output of the column decoder, thereby writing data to a specific memory cell or writing memory cell data. It is possible to read.

An example of a document describing SRAM is Japanese Patent Publication No. 57-21795.

[0004]

The access time of SRAM can be measured by using a device called an LSI tester (hereinafter, simply referred to as "tester") for enabling various LSI tests. The tester has a function of generating a power supply voltage necessary for the operation of the LSI, a clock signal, and various control signals, and is connected to an external terminal of the SRAM to be tested through a predetermined cable. , Enables various operation tests of the SRAM. The access time can be measured by detecting the phase difference between the clock signals supplied to the address signal latch and the output latch in the SRAM.

The accuracy of the phase difference between the clock signals supplied from the tester to the tested SRAM is ± 300 ps.
The SR is about 3 ns access time.
It can be included in the design margin in the AM access time measurement. However, if the access time is shortened to about 1 ns due to the faster operation of the SRAM, the measurement error of the access time becomes large, and the accuracy of the clock signal phase difference cannot be ignored.

An object of the present invention is to provide a technique for improving the accuracy of access time measurement.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, as a first means, a memory section (13) whose access time is to be measured, and a first latch circuit () capable of latching an address signal input to the memory section in synchronization with a first clock signal ( 11), a second latch circuit (14) capable of latching output data from the memory unit in synchronization with a second clock signal, and a third latch circuit capable of latching the address signal in synchronization with the second clock signal. When a semiconductor integrated circuit is formed including the latch circuit (12), a difference in electrical length in a conductive path outside the semiconductor integrated circuit for each of the first clock signal and the second clock signal is calculated. Then, this difference in electrical length is corrected.

Further, in a specific aspect, a memory section (13) whose access time is to be measured, and a first latch circuit capable of latching an address signal input to the memory section in synchronization with a first clock signal. (11), a second latch circuit (14) capable of latching output data from the memory unit in synchronization with a second clock signal, and a first latch circuit capable of latching the address signal in synchronization with the second clock signal. When a semiconductor integrated circuit including the 3 latch circuit (12) is formed, the phase of the second clock signal supplied from the outside is changed so that the data corresponding to the address signal latched by the first latch is generated. When measuring the access time of the memory unit based on the phase difference between the first clock signal and the second clock signal when latched by the second latch circuit , Changing the phase of the first clock signal and changing the phase of the second clock signal and the timing of the first clock signal when the target signal state is latched by the first latch circuit to change the target signal state. Due to the difference from the timing of the second clock signal when latched by the third latch circuit, the electricity in the conductive path outside the semiconductor integrated circuit for each of the first clock signal and the second clock signal is calculated. The difference in length is obtained and this electrical length difference is corrected.

As a second means, a memory section (13) whose access time is to be measured and a first latch circuit (51) capable of latching an address signal input to the memory section in synchronization with a clock signal. A second latch circuit (52) capable of latching output data from the memory unit in synchronization with the clock signal, and a third latch circuit (5) capable of latching the address signal in synchronization with the clock signal.
3) and a semiconductor integrated circuit is formed, the pulse width of the clock signal supplied from the outside is changed, and the pulse width of the clock signal when the latch data in the third latch circuit is switched. Based on the above, when measuring the access time of the memory unit, the phase is changed while the pulse width of the clock signal when the latch data in the second latch circuit is switched is fixed, The time difference between the output logic change timing of the latch circuit and the output logic change timing of the third latch circuit is obtained as the access time of the memory section.

Further, as a specific mode, the memory unit (13) whose access time is to be measured, and the first SM which can latch the address signal input to the memory unit in synchronization with the rising timing of the clock signal. A latch circuit (51), a D-latch circuit (52) capable of latching output data from the memory section in synchronization with the falling timing of the clock signal, and the address in synchronization with the falling timing of the clock signal. When a semiconductor integrated circuit is formed including a second SM latch (53) capable of latching a signal, the pulse width of the clock signal supplied from the outside is changed to switch the latch data in the D latch circuit. Based on the pulse width of the clock signal at the time, when measuring the access time of the memory unit,
When the latched data in the D latch circuit is switched, the phase of the clock signal is changed while the pulse width of the clock signal is fixed, and the first S signal is output at the rising timing of the clock.
The first timing when the output logic of the M latch circuit is changed and the second timing when the clock falls.
The time difference from the second timing when the output logic of the latch circuit is changed is obtained as the access time of the memory section.

According to the above-mentioned first means, the difference between the electric lengths of the first clock signal and the second clock signal in the conductive path outside the semiconductor integrated circuit is obtained, and the electric length is calculated. By compensating for the difference, the access time measurement error due to the electrical length difference is reduced, which achieves improved access time accuracy.

According to the above-mentioned second means, the phase is changed while the pulse width of the clock signal when the latch data in the second latch circuit is switched is fixed, and the output of the first latch circuit is changed. Logic change timing and the second
The time difference from the output logic change timing of the latch circuit,
When the access time of the RAM section is obtained, the pulse width of the clock signal can be measured regardless of the electrical length of the conductive path, which improves the accuracy of the access time.

[0015]

1 shows an access time measuring circuit to which a method according to an embodiment of the present invention is applied.

LSI 15 whose access time is to be measured
Although not particularly limited, it is an SRAM, and is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. The LSI 15 has an SRAM section 13 which is an example of a memory section. Although not shown, the SRAM section 13 includes static type memory cells. Select terminals of the static type memory cells are coupled to word lines in each row direction, and data input / output terminals of the memory cells are complementary data in each column direction. Combined with lines. Each complementary data line is commonly connected to the complementary common data line via a column switch circuit including a plurality of switches that are coupled to the complementary data line in a one-to-one relationship. The address signal input from the outside is transmitted to the row decoder and the column decoder. The word line is driven to the selection level based on the decode output of the row decoder, and the column selection switch is turned on based on the decode output of the column decoder, thereby writing data to a specific memory cell or writing memory cell data. It is possible to read.
Although not shown, the chip select signal CS * (* means low active or signal inversion) and the write enable signal W are externally applied control signals.
There is E *. Chip selection is performed by asserting the chip select signal CS * at a low level, and when the write enable signal WE * is asserted at a low level in such a selected state, data to the memory cell is written. Writing is enabled.

The SRAM section 13 is configured to be able to output data having a multi-bit configuration by inputting an address having a multi-bit configuration. In FIG. 1, for convenience of description of access time measurement, input of a 1-bit address signal. Indicates that 1-bit data is read.
The input address from the address terminal T2 is input to the SRAM section 13 via an SM (slave master (sometimes referred to as master / slave)) latch 11. Then, the output data from the SRAM section 13 can be output to the outside through the SM latch 14 arranged at the subsequent stage and the data terminal T5. The SM latch 11 latches the input address in synchronization with the clock signal CK0 input via the clock terminal T1. Further, the SM latch 14 latches the output data from the SRAM section 13 in synchronization with the clock signal CK1 input via the clock terminal T3. The access time of the LSI 15, which will be described in detail later, can be measured by detecting the phase difference between the clock signals CK0 and CK1 when the data corresponding to the output address of the SM latch 11 is latched in the SM latch 14. . In such a measuring method, in order to improve the accuracy of the phase difference between the clock signals CK0 and CK1, in this embodiment, the phase difference is corrected, and in order to obtain the phase difference correction data, S
An M latch 12 is provided. This SM latch 12
Latches the input address signal in synchronization with the clock signal CK1 input via the clock terminal T3. SM
The scan system outputs of the latches 11 and 12 can be externally output via the scan system output terminal T4 provided in the LSI 15.

The LSI 15 whose access time is to be measured
Are electrically coupled to the tester 10. This electrical connection is achieved by connecting an external terminal of the LSI 15 to an LSI socket (not shown) provided in the tester 10, and various conductive paths are formed between the tester 10 and the external terminal of the LSI 15. It In FIG. 1, the conductive paths indicated by L1 to L5 are representatively shown. The conductive path L1 serves as a transmission path for the clock signal CK0 and is coupled to the clock signal input terminal T1 of the LSI 15. The conductive path L2 serves as an address signal transmission path and is coupled to the address terminal T2 of the LSI 15. The conductive path L3 serves as a transmission path for the clock signal CK1 and is coupled to the clock terminal T3 of the LSI 15. The conductive path L4 is used as a transmission path for scan system output data, and
15 scan system output terminals T4. Conductive path L
5 is a data transmission path, and the data terminal T5 of the LSI 15
Is combined with

FIG. 2 shows the functional blocks of the tester 10.

As shown in FIG. 2, the tester 10 is not particularly limited, but the control and data processing unit 21 and the power supply unit 2 are included.
2, voltage measuring means 23, current measuring means 24, clock signal generating means 26, address generating means 27, and logic determining means 28.

The power supply unit 22 has a function of generating an operating power supply voltage of the LSI to be tested, and the operating power supply voltage of the LSI 15 is generated by the power supply unit 22. The voltage measuring unit 23 and the current measuring means 24 are each a test target L.
It has the function of measuring the voltage between the main terminals of SI and the current between the main terminals. The clock signal generating means 26 generates a clock signal supplied to the test target LSI. In this embodiment, the clock signal CK supplied to the LSI 15
0 and CK1 are generated by the clock signal generating means 26. The address generating means 27 has a function of generating an address signal supplied to the test target LSI. In this embodiment, the address signal supplied to the LSI 15 is generated. The logic determining means 28 has a function of determining the output logic from the test target LSI. In this embodiment, the LSI 1
5, the logic of the data transmitted via the scan system output terminal T4 and the data terminal T5 is determined. The control and data processing means 21 has a function of controlling the operation of each part of the tester 10 and a processing function of a measurement or determination result.

Next, the measurement of the access time of the LSI 15 will be described. In this embodiment, data for correcting the phase difference between the clock signals CK0 and CK1 is collected before the access time measurement, and the data correction based on the data is used to improve the accuracy of the access time measurement.

FIG. 3 shows the timing for collecting the clock signal correction data.

In the LSI 15, the transmission system of the clock signals CK0 and CK1 is assumed to have equal length wiring, and there is no skew there.

In collecting the clock signal correction data, the logic of the output signal from the scan system output terminal T4 is judged by the logic judging means 28 of the tester 21.

First, the timing at which the address output from the tester 10 rises from low level to high level is fixed. For convenience, the low level of the address is set to the address A, and the high level of the address is set to the address B. Due to the electrical length of the conductive path L2 formed between the tester 10 and the LSI 15, the address output from the tester 10 is delayed as indicated by the arrow 31 and input to the LSI 15.

Clock signal C output from the tester 10
With respect to K0 as well, the clock signal CK0 output from the tester 10 is delayed as indicated by the arrow 33 and input to the LSI 15 due to the electrical length of the conductive path L1 formed between the tester 10 and the LSI 15. Clock signal C
K0 is input to the SM latch 11, and the SM latch 11 latches the address signal in synchronization with the rising timing thereof. The clock signal CK0 is delayed by the tester 10 in the direction indicated by the arrow 32 in minute time units. At first, the address A is latched by the SM latch 11, but by delaying the rising timing of the clock signal CK0 in the direction shown by the arrow 32, the address B will be latched eventually. The rising timing of the clock signal CK0 when the latch address changes from A to B is determined, and the timing is set to t0.

As with the clock signal CK0, the clock signal CK1 is also delayed by a minute time unit to determine the timing of the clock signal CK1 when the latch address of the SM latch 12 changes from A to B,
The timing is t1.

The electrical lengths in the conductive paths between the tester 10 and the LSI 15 for the clock signals CK0 and CK1 are Δt0 and Δt1, respectively. At this time, since the timings at which the address B can be latched by the SM latches 11 and 12 are the same, t0 + Δt0 = t1 + Δt1 ... That is, the difference Δ in electrical length between the conductive paths L1 and L3.
t is the clock signals CK0 and CK1 in the tester 10.
Is equal to the phase difference of Δt = Δt0−Δt1 = t1−t0. Although the phase difference Δt is generated between the clock signals CK0 and CK1 due to the difference in the electrical lengths of the conductive paths L1 and L3, the phase difference Δt is ignored and the access time is measured. The more you have,
The access time measurement error increases. Therefore, in this embodiment, the phase difference Δt is used as correction data to correct the access time measurement value as described below to improve the accuracy of the access time measurement.

FIG. 4 shows the timing for measuring the access time.

First, a predetermined test pattern is written in the SRAM section 13. The test pattern is performed by the tester 10, and the test pattern information is stored in the tester 10 and used as an expected value in the logic judgment described later.

The rising timing of the address signal and the rising timing of the clock signal CK0 are fixed. The rising timing of the clock signal CK0 in that case is indicated by t00.

Further, the SM latch 11 causes the address A
Is adjusted so that the rising timing of the clock signal CK1 is adjusted.

Next, the SR corresponding to the address B
The clock signal C output from the tester 10 until the output data from the M unit 13 is latched by the SM latch 14.
K1 rise timing little by little, for example 50 ps
Delay each. That is, each time the rising timing of the clock signal CK1 is delayed, the logic determination means 28 determines the output logic of the SM latch 14. The SM latch 14 initially latches the output data corresponding to the address A, but due to the delay of the clock signal CK1, the output data corresponding to the address B will be latched. Therefore, in the logic determination means 28,
Whether the output logic of the SM latch 14 matches the expected value,
That is, the data corresponding to the address B is the SM latch 14
It is judged whether or not it is latched by. When it is determined in this determination that the output logic of the SM latch 14 matches the expected value, the delay of the clock signal CK1 is ended. The latched data of the SM latch 14 is
The timing at which the address corresponding to the address A is changed to the address corresponding to the address B is indicated by t11.

Basically, the access time of the SRAM section 13 is obtained by t11-t00. However, as described above, since the electrical lengths of the conductive paths L1 and L3 are actually different and the accuracy of the phase difference between the clock signals CK0 and CK1 is reduced, the above t11-t00 is corrected by the correction previously obtained. Correct with data Δt. That is, the SRAM unit 13
The access time T of T is set to T = t11-t00 + Δt ... By thus taking the correction data Δt into consideration, the access time of the SRAM 13 can be accurately measured.

According to the above embodiment, the following operational effects can be obtained.

The clock signal CK0 is delayed by a minute time unit, and the timing of the clock signal CK0 when the target signal state is latched by the SM latch circuit 11 and the clock signal CK1 are delayed by a minute time to obtain the target signal state. The clock signal C when latched by the SM latch circuit 12
From the difference with the timing of K1, the clock signals CK0, C
By obtaining the difference between the electrical lengths of the conductive paths L1 and L3 outside the LSI 15 for each K1 and correcting the electrical length difference, the access time measurement error due to the electrical length difference can be reduced. Therefore, the SRAM unit 13
It is possible to improve the accuracy of the access time.

Next, another embodiment will be described.

FIG. 5 shows an access time measuring circuit to which the method of another embodiment of the present invention is applied.

The LSI 54 whose access time is to be measured
Although not particularly limited, it is an SRAM, and is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. LSI 54 is SRAM
It has a part 13. The SRAM section 13 has the same configuration as that shown in FIG. That is, the select terminal of the static memory cell is connected to the word line in each row direction, the data input / output terminal of the memory cell is connected to the complementary data line in each column direction, and each complementary data line is connected to the complementary data line. It is commonly connected to the complementary common data line through a column switch circuit including a plurality of switches connected in a one-to-one manner. The address signal input from the outside is
It is transmitted to the row decoder and the column decoder. The word line is driven to the selection level based on the decode output of the row decoder, and the column selection switch is turned on based on the decode output of the column decoder, thereby writing data to a specific memory cell or writing memory cell data. It is possible to read.

The SRAM section 13 is configured to be capable of outputting data of a multi-bit configuration by inputting an address of a multi-bit configuration. However, for convenience of explanation of the access time measurement, the 1-bit address signal is input to the SRAM section 13. The data is shown as being read. The input address from the address terminal T6 is S via the SM latch 51.
The data is input to the RAM section 13. And
The output data from the SRAM section 13 includes a D-type latch (referred to as a D-latch) 52 arranged in a subsequent stage and a data terminal T.
It is possible to output externally via 8. The D-latch 52 is SR in synchronization with the falling timing of the clock signal CK1.
The output data from the AM unit 13 is latched. The SM latches 51 and 52 latch the input address in synchronization with the clock signal CK1 input via the clock terminal T7. However, the SM latch 51 latches the input address at the rising timing of the clock signal CK1, whereas the SM latch 53 latches the input address in synchronization with the falling timing of the clock signal CK1. D
The output signal of the latch 52 and the scan system output signal are transmitted to the tester 10 via the data terminal T8 and the scan system output terminal T9, respectively.

FIG. 6 shows the timing of access time measurement.

The address signal and the clock signal CK1 output from the tester 10 are delayed and input to the LSI 54 as shown by arrows 61 and 62, respectively. The input address is latched by the SM latch 51 in synchronization with the rising timing of the clock signal CK1, and the SRAM is synchronized with the falling timing of the clock signal CK1.
The output data of the unit 13 is latched in the D latch 52. At the timing shown in FIG. 6, the output data of the SRAM section 13 corresponding to the address B is latched by the D latch 52 at the falling timing of the clock signal CK1, but on the tester 10 side. When the pulse width of the clock signal CK1 is gradually narrowed,
The data corresponding to the address A will be latched instead of the data corresponding to the address B, which could be latched until then. By determining the logic of the output data of the D latch 52 by the logic determining means 28 of the tester 10, the timing at which the data held in the D latch 52 changes from that corresponding to the address B to that corresponding to the address A can be grasped. You can Therefore, when the pulse width of the clock signal CK1 is gradually narrowed as described above, the pulse width of the clock signal CK1 immediately before the data held in the D latch 52 changes to that corresponding to the address A is This corresponds to the access time of the SRAM unit 13. The pulse width of this clock signal CK1 can be accurately obtained by the following method.

FIG. 7 shows the timing for measuring the pulse width of the clock CK1.

With the width of the clock CK1 fixed, as shown by an arrow 71 in FIG.
The phase of K1 is changed. By determining the logic of the output signal from the scan system output terminal T9 (see FIG. 5) by the logic determining means 28 of the tester 10, the address signals latched in the SM latch 51 are changed from A to B at the rising timing of the clock CK1. The first timing for switching to is calculated.
Similarly, by changing the phase of the clock CK1, the address signal held in the SM latch 53 is switched from A to B at the falling timing of the clock CK1 (the rising timing as CK1 *). 2 Determine the timing. The time difference between the first timing and the second timing is the pulse width that the clock CK1 seeks. As described above, the phase of the clock CK1 is changed while the pulse width of the clock CK1 is fixed, and the switching timings of the address signals latched by the SM latches 51 and 52 are obtained.
Since it is possible to measure the width of the clock signal CK1 at the positions of 6 and T7, even if the electrical lengths of the conductive paths L6 and L7 between the tester 10 and the LSI 54 exist, the above is irrelevant regardless of the above. The pulse width of the clock CK1, that is,
The access time in the measurement circuit shown in FIG. 5 can be accurately obtained.

According to the above embodiment, the following operational effects can be obtained.

When the latched data in the D latch circuit 52 is switched, its phase is changed while the pulse width of the clock signal is fixed, and the output logic change timing of the SM latch circuit 51 and the SM latch circuit 53 are changed. By determining the time difference from the output logic change timing as the access time of the RAM section, the pulse width of the clock signal can be measured irrespective of the electrical length of the conductive path, thus improving the accuracy of the access time. Can be planned.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the scope of the invention. Yes.

For example, in the above-mentioned embodiment, for convenience of explanation of the access time measurement, 1-bit data is read by inputting a 1-bit address signal, but in reality, the input address to the SRAM is It has a multi-bit configuration, and the I / O of the SRAM section 14 often has a multi-bit configuration. In that case, SM
A plurality of latches 11, 12, 51, 53 are arranged corresponding to the bit configuration of the address, and a plurality of SM latches 14 and D latches 52 are arranged corresponding to the number of I / O configuration bits. It

Also, in a semiconductor integrated circuit in which a microcomputer and other functional modules are arranged in the LSI 15, the access time can be measured due to the presence of the SRAM 13. In addition, the SRAM unit 13
Instead of this, even when other semiconductor memory units such as a dynamic RAM unit are provided, the access time of the memory unit can be measured.

Further, in the embodiment shown in FIGS. 1 to 4, the correction data Δt is used to perform the correction according to the above equation, but instead of such correction, the correction data Δt is used. The phases of the clocks CK0 and CK1 themselves may be corrected.

In the above description, SRA, which is the field of application behind the invention made mainly by the present inventor, is the background.
The case where the present invention is applied to the measurement of the access time of the M section has been described, but the present invention is not limited to this and can be applied to the measurement of the access time of various semiconductor memories.

The present invention is applicable to at least a semiconductor integrated circuit.
It can be applied on condition that the AM part is included.

[0054]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the difference in electrical length between the first clock signal and the second clock signal in the conductive path outside the semiconductor integrated circuit is obtained, and the electrical length difference is corrected to obtain the electrical length difference. It is possible to reduce the error in access time measurement due to, and thereby improve the accuracy of access time.

Further, while the pulse width of the clock signal at the time of switching the latch data in the second latch circuit is fixed, its phase is changed to change the output logic of the first latch circuit and the second latch circuit. By obtaining the time difference from the change timing of the output logic of the circuit as the access time of the RAM section, the pulse width of the clock signal can be measured regardless of the electrical length of the conductive path, thus improving the accuracy of the access time. Can be planned.

[Brief description of the drawings]

FIG. 1 is a block diagram of an access time measuring circuit to which a method according to an embodiment of the present invention is applied.

FIG. 2 is a functional block diagram of a tester used in the access time measurement.

FIG. 3 is a timing diagram for collecting clock signal correction data used in the access time measurement.

FIG. 4 is a timing diagram for measuring the access time.

FIG. 5 is a block diagram of an access time measuring circuit to which a method according to another embodiment of the present invention is applied.

6 is a timing diagram of access time measurement in the circuit shown in FIG.

7 is a timing diagram for pulse width measurement in the circuit shown in FIG.

[Explanation of symbols]

 10 Tester 11, 12, 14, 51, 53 SM Latch 13 SRAM Section 15 Semiconductor Memory Device 21 Control and Data Processing Means 22 Power Supply Section 23 Voltage Measuring Means 24 Current Measuring Means 26 Clock Generating Means 27 Address Generating Means 28 Logic Judging Means 52 D latch

Claims (5)

[Claims] 1. A memory unit whose access time is to be measured, a first latch circuit capable of latching an address signal input to the memory unit in synchronization with a first clock signal, and output data from the memory unit. When a semiconductor integrated circuit is formed including a second latch circuit capable of latching the address signal in synchronization with the second clock signal and a third latch circuit capable of latching the address signal in synchronization with the second clock signal. ,
An access time measuring method for measuring an access time of the memory section in the semiconductor integrated circuit, comprising: electrically connecting a conductive path outside the semiconductor integrated circuit for each of the first clock signal and the second clock signal. An access time measuring method characterized by obtaining a difference in length and correcting the electrical length difference. 2. A memory unit whose access time is measured, a first latch circuit capable of latching an address signal input to the memory unit in synchronization with a first clock signal, and output data from the memory unit. When a semiconductor integrated circuit is formed including a second latch circuit capable of latching the address signal in synchronization with the second clock signal and a third latch circuit capable of latching the address signal in synchronization with the second clock signal. ,
The phase of the second clock signal supplied from the outside is changed, and when the data corresponding to the address signal latched in the first latch is latched in the second latch circuit, the first clock signal and the In an access time measuring method for measuring an access time of the memory unit based on a phase difference from a second clock signal, a phase of the first clock signal is changed and a target signal state is latched by the first latch circuit. From the difference between the timing of the first clock signal and the timing of the second clock signal when the phase of the second clock signal is changed and the target signal state is latched by the third latch circuit, A difference in electrical length in a conductive path outside the semiconductor integrated circuit is obtained for each of the first clock signal and the second clock signal. Then, an access time measuring method characterized by correcting this electrical length difference. 3. A memory unit whose access time is measured, a first latch circuit capable of latching an address signal input to the memory unit in synchronization with a clock signal, and output data from the memory unit. When a semiconductor integrated circuit is formed including a second latch circuit capable of latching in synchronization with a clock signal and a third latch circuit capable of latching the address signal in synchronization with the clock signal, it is supplied from the outside. In the access time measuring method, the pulse width of the clock signal is changed, and the access time of the memory unit is measured based on the pulse width of the clock signal when the latch data in the third latch circuit is switched, The phase is changed while the pulse width of the clock signal when the latch data in the second latch circuit is switched is fixed, 1 and the output logic of the change timing of the latch circuit, the third time difference between the output logic of the change timing of the latch circuit, the access time measuring method characterized by determining the access time of the memory unit. 4. A memory unit to be measured as an access time, and a first latchable address signal input to the memory unit in synchronization with a rising timing of a clock signal.
Slave / master latch circuit, D latch circuit capable of latching output data from the memory unit in synchronization with the falling timing of the clock signal, and latching of the address signal in synchronization with the falling timing of the clock signal When a semiconductor integrated circuit including the second SM latch is formed, the pulse width of the clock signal supplied from the outside is changed to change the clock signal when the latch data in the D latch circuit is switched. An access time measuring method for measuring an access time of the memory section based on a pulse width, the phase of the clock signal when the latched data in the D latch circuit is switched is fixed in phase. To change the output logic of the first slave / master latch circuit at the rising timing of the clock. Access characterized in that the time difference between the first timing when the clock is turned on and the second timing when the output logic of the second slave / master latch circuit is changed at the fall timing of the clock is obtained as the access time of the memory section. How to measure time. 5. A power supply for operating the semiconductor integrated circuit, the external terminal of the semiconductor integrated circuit being coupled to a tester,
5. The access time measuring method according to claim 1, wherein the supply of the clock signal and the logic determination of the output signal from the semiconductor integrated circuit are performed by the tester.