JPH09122966A - Solder paste, joining method using this solder paste and semiconductor device - Google Patents

Solder paste, joining method using this solder paste and semiconductor device

Info

Publication number
JPH09122966A
JPH09122966A JP7279193A JP27919395A JPH09122966A JP H09122966 A JPH09122966 A JP H09122966A JP 7279193 A JP7279193 A JP 7279193A JP 27919395 A JP27919395 A JP 27919395A JP H09122966 A JPH09122966 A JP H09122966A
Authority
JP
Japan
Prior art keywords
solder
solder paste
flux
flux component
powder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7279193A
Other languages
Japanese (ja)
Inventor
Mitsunori Ishizaki
光範 石崎
Tetsuo Sakata
哲夫 坂田
Tsuneo Hamaguchi
恒夫 濱口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7279193A priority Critical patent/JPH09122966A/en
Publication of JPH09122966A publication Critical patent/JPH09122966A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3485Applying solder paste, slurry or powder

Landscapes

  • Die Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To make it possible to decrease the void defects in a joint part by forming solder powder of which >=20wt.% has at least 90μm grain size and specifying the content of a flux component to >=6 to <=12wt.% of solder paste. SOLUTION: This solder paste is formed by mixing the solder powder and the flux component and >=20wt.% of the solder particles have at least 90μm grain size. The content of the flux component is specified to >=6 to <=12wt.%. The number of particles of the solder powder and the density of the solder paste decrease and the content of the flux component is low as well. Then, even if the printing quantity of the solder paste in joining increases, the amt. of the flux is sufficiently decreased and voids are decreased. The gaps among the particles of the solder powder increase and the discharge of the gases generated from the flux component is easy. The generation of air bubbles which are the cause for the voids is suppressed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】この発明は、半導体チップや
半導体装置基板等比較的接合面積の大きい部材を基材に
接合する際に用いられるソルダペーストに関するもので
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solder paste used for bonding a member having a relatively large bonding area such as a semiconductor chip or a semiconductor device substrate to a base material.

【0002】[0002]

【従来の技術】図3は、例えば学献社発行の「エレクト
ロニク・セラミクス」(1988年11月号)に記載さ
れている、セラミクスの絶縁基板を使用した高発熱・大
電流消費の半導体装置の構造を示す断面図である。図に
おいて、1はセラミクスから成る絶縁基板(以下、セラ
ミクス基板と称す)、2a,2bはセラミクス基板2の
表面および裏面に形成された金属層、3はセラミクス基
板1表面の所定領域の金属層2aに接合されてセラミク
ス基板1に搭載された発熱量の大きい半導体チップ、4
はセラミクス基板1裏面の金属層2bに接合されて半導
体チップ3で発生した熱を外部へ放熱させる熱伝導性の
良好な金属基板、5は半導体チップ3と金属層2aとを
電気的に接続するワイヤ、6a,6bはセラミクス基板
1の表面および裏面に形成された金属層2a,2bと、
それに接合された半導体チップ3および金属基板4との
間に形成された接合のためのはんだ層である。
2. Description of the Related Art FIG. 3 shows a semiconductor device of high heat generation and large current consumption, which uses an insulating substrate of ceramics, as described in, for example, "Electronic Ceramics" (November 1988) issued by Gakudonsha. It is a cross-sectional view showing the structure of. In the figure, 1 is an insulating substrate made of ceramics (hereinafter referred to as ceramics substrate), 2a and 2b are metal layers formed on the front and back surfaces of the ceramics substrate 2, and 3 is a metal layer 2a in a predetermined region on the surface of the ceramics substrate 1. A semiconductor chip with a large heat generation, which is bonded to the semiconductor chip and mounted on the ceramic substrate 1.
Is a metal substrate which is bonded to the metal layer 2b on the back surface of the ceramic substrate 1 and has good thermal conductivity for radiating the heat generated in the semiconductor chip 3 to the outside. 5 electrically connects the semiconductor chip 3 and the metal layer 2a. Wires 6a and 6b are metal layers 2a and 2b formed on the front and back surfaces of the ceramic substrate 1,
It is a solder layer for joining formed between the semiconductor chip 3 and the metal substrate 4 joined thereto.

【0003】以上のように構成された半導体装置におい
て、接合のためのはんだ層6a,6bには、はんだ粉末
にフラックス成分を混合して構成されたソルダペースト
が用いられる。はんだ層6aは表面および裏面に金属層
2a,2bが形成されたセラミクス基板1の表面に形成
された金属層2a上の所定領域に、スクリーン印刷によ
り上記ソルダペーストを供給してソルダペースト層7a
(図示せず)を形成した後、半導体チップ3をソルダペ
ースト層7aが形成された箇所に搭載し、加熱装置で熱
処理を施すことにより、ソルダペースト層7a中のはん
だ粉末を溶融させるとともにフラックス成分を外部に排
出させ、続いて冷却処理を施して溶融したはんだを凝固
させて形成する。また、はんだ層6bは金属基板4上の
所定領域に、スクリーン印刷により上記ソルダペースト
を供給してソルダペースト層7b(図示せず)を形成し
た後、セラミクス基板1をソルダペースト層7bが形成
された箇所に搭載し、加熱装置で熱処理を施すことによ
り、上記はんだ層6aと同様の過程で形成する。はんだ
層6a,6bの形成時に半導体装置外部に付着するフラ
ックスの固形成分の残渣(以下、フラックス残渣と称
す)は、洗浄液により除去する。なお、2つのはんだ層
6a,6bはそれぞれ個別に形成する場合も同時に形成
する場合もある。また、2つのはんだ層6a,6bに用
いられるソルダペーストは同一である場合も異なる場合
もある。
In the semiconductor device constructed as described above, the solder layers 6a and 6b for joining are made of a solder paste composed of a solder powder mixed with a flux component. The solder layer 6a is supplied with the above-mentioned solder paste by screen printing to a predetermined region on the metal layer 2a formed on the front surface of the ceramic substrate 1 having the metal layers 2a and 2b formed on the front and back surfaces thereof, and the solder paste layer 7a.
After forming (not shown), the semiconductor chip 3 is mounted on the place where the solder paste layer 7a is formed, and heat treatment is performed by a heating device to melt the solder powder in the solder paste layer 7a and to make a flux component. Is discharged to the outside, and subsequently, a cooling process is performed to solidify the molten solder to form the solder. Further, the solder layer 6b is formed on the metal substrate 4 in a predetermined area by screen printing to supply the solder paste to form a solder paste layer 7b (not shown), and then the ceramic substrate 1 is formed with the solder paste layer 7b. The solder layer 6a is formed in the same process as the above-mentioned solder layer 6a by mounting the solder layer 6a in a different place and performing heat treatment with a heating device. The residue of the solid component of the flux (hereinafter referred to as the flux residue) attached to the outside of the semiconductor device when the solder layers 6a and 6b are formed is removed by a cleaning liquid. The two solder layers 6a and 6b may be formed individually or simultaneously. The solder paste used for the two solder layers 6a and 6b may be the same or different.

【0004】ところで、上記のようなはんだ層6a,6
bによる接合に用いられる従来のソルダペーストは、例
えば株式会社日本スペリア社発行の「PRODUCTS
GUIDE ソルダリング部門」に記載されているよう
に、75μm以下の粒径分布を持つはんだ粉末に印刷性
とぬれ性を確保するために9〜15wt%の含有量でフ
ラックス成分を混合したものであった。
By the way, the above-mentioned solder layers 6a, 6
The conventional solder paste used for joining by b is, for example, "PRODUCTS" issued by Nippon Superior Co., Ltd.
As described in "GUIDE Soldering Department", it is a mixture of flux components with a content of 9 to 15 wt% in order to secure printability and wettability to solder powder having a particle size distribution of 75 μm or less. It was

【0005】[0005]

【発明が解決しようとする課題】上記のような従来のソ
ルダペーストを用いて接合を行う際、スクリーン印刷で
供給されたソルダペーストの表面には凹凸が存在するた
め、その上に部材を搭載すると、ソルダペースト表面と
部材との間には隙間が生じる。加熱を始めてフラックス
の固形成分の軟化点前後まで温度が上昇するとソルダペ
ーストの流動性が増し、毛細管現象によって上記隙間を
埋めるようにソルダペーストが流動し、ソルダペースト
と搭載部材との接触面積が増加していく。しかし、この
時上記の隙間に存在していた雰囲気の一部は閉じ込めら
れ、ソルダペーストと搭載部材との間に無数の気泡が形
成される。時間が経過し温度が上昇すると、上記気泡の
一部はソルダペースト中を移動し外部に排出されて消失
するが、一部は気泡内部に閉じ込められた雰囲気の膨張
によって周囲のソルダペーストを押し退けて大きさを増
し、ソルダペーストの表裏面を貫通する気泡を形成す
る。さらに温度が上昇してソルダペースト中のフラック
ス成分の溶剤が活発に気化し始めると、気化した気体の
一部がソルダペースト中に閉じ込められて気泡が形成さ
れ、このような気泡は急激な加熱を行うと顕著に発生す
る。
When joining is performed using the conventional solder paste as described above, since the surface of the solder paste supplied by screen printing has irregularities, if a member is mounted on it A gap is formed between the surface of the solder paste and the member. When heating starts and the temperature rises to around the softening point of the solid component of the flux, the fluidity of the solder paste increases, and the solder paste flows to fill the above gap due to the capillary phenomenon, increasing the contact area between the solder paste and the mounting member. I will do it. However, at this time, a part of the atmosphere existing in the above-mentioned gap is confined, and innumerable bubbles are formed between the solder paste and the mounting member. When time passes and the temperature rises, some of the bubbles move in the solder paste and are discharged to the outside to disappear, but some of them are pushed away by the surrounding solder paste due to the expansion of the atmosphere trapped inside the bubbles. The size of the solder paste is increased to form bubbles that penetrate the front and back surfaces of the solder paste. When the temperature further rises and the solvent of the flux component in the solder paste begins to vaporize actively, some of the vaporized gas is trapped in the solder paste and bubbles are formed. It occurs remarkably when done.

【0006】以上のように形成された気泡にはフラック
スの固形成分やフラックス成分から発生する気体が選択
的に閉じ込められ、このような気泡の形成された箇所の
一部は、はんだ粉末が溶融しても溶融はんだと被接合部
材との接触を妨げて不ぬれを生じさせ、はんだ凝固後に
ボイドと呼ばれる接合欠陥を形成した。このようなフラ
ックス成分の残留に起因するボイドは、接合面積が大き
い部材の場合、ソルダペーストの印刷量も大きく接合部
のフラックス量も多量となるため、発生しやすくなる。
ボイド不良は接合部の面積の10%以上を占めることも
あり、特に上述したような大電流半導体装置において
は、はんだ層6a,6bに多数のボイドが形成される
と、半導体チップ3と金属基板4との間の熱の流路が狭
まって放熱能力が著しく低下し、半導体装置の信頼性が
劣化してしまう問題があった。
In the bubbles formed as described above, the solid components of the flux and the gas generated from the flux components are selectively confined, and the solder powder is melted at a part of the places where such bubbles are formed. Even so, the contact between the molten solder and the members to be joined was impeded to cause non-wetting, and a joint defect called a void was formed after solidification of the solder. In the case of a member having a large bonding area, such voids due to the residual flux components are likely to occur because the printing amount of the solder paste is large and the flux amount of the bonding portion is large.
The void defect may occupy 10% or more of the area of the joint portion. Especially, in the large current semiconductor device as described above, when a large number of voids are formed in the solder layers 6a and 6b, the semiconductor chip 3 and the metal substrate are not formed. There is a problem that the heat flow path between the semiconductor device and the device 4 is narrowed, the heat dissipation capability is significantly reduced, and the reliability of the semiconductor device is deteriorated.

【0007】上記のようなボイド不良を低減するため
に、上述した大電流半導体装置の接合工程において、は
んだ溶融後の冷却過程で、はんだが凝固する前にスクラ
ブ工程が従来から行われている。このスクラブ工程は、
人手によって半導体チップ3あるいはセラミクス基板1
に振動を加え、ボイド内部の気体や固形成分を外部に排
出させ、はんだ層6a,6bのボイド不良を低減させる
工程である。しかしながら、このようなスクラブ工程は
作業者の熟練度等により効果の差が大きく信頼性に問題
があるとともに、工程数の増加による生産性の低下や人
件費による製造コストの増加等の問題があった。また、
特に加熱、接合中の雰囲気を制御したい場合には、気密
性維持のためにスクラブ工程が行えないという問題もあ
った。
In order to reduce the void defects as described above, a scrubbing step has been conventionally performed before the solder solidifies in the cooling step after the melting of the solder in the above-mentioned joining step of the high-current semiconductor device. This scrubbing process
The semiconductor chip 3 or the ceramics substrate 1 is manually
In this step, the gas and solid components inside the voids are discharged to the outside to reduce the void defects in the solder layers 6a and 6b. However, such a scrubbing process has a large effect difference depending on the degree of skill of the operator and there is a problem in reliability, and there are problems such as a decrease in productivity due to an increase in the number of processes and an increase in manufacturing cost due to personnel costs. It was Also,
Especially when it is desired to control the atmosphere during heating and bonding, there is also a problem that the scrubbing process cannot be performed to maintain airtightness.

【0008】この発明は、以上のような問題点を解消す
るためになされたものであって、接合部のボイド不良を
安定的に低減できる信頼性の高いソルダペーストを得る
とともに、高発熱、大電流消費の半導体装置の放熱性を
向上させて信頼性の向上を図ることを目的とする。
The present invention has been made in order to solve the above problems, and provides a highly reliable solder paste which can stably reduce void defects in the joint portion, and also has high heat generation and large heat generation. It is an object of the present invention to improve the heat dissipation of a semiconductor device which consumes current and to improve the reliability.

【0009】[0009]

【課題を解決するための手段】この発明の請求項1に係
わるソルダペーストは、はんだ粉末とフラックス成分と
を混合したものであって、上記はんだ粉末のはんだ粒子
の20wt%以上が少なくとも90μmの粒径を有し、
しかも上記フラックス成分の含有量が6wt%以上、1
2wt%以下であるものである。
A solder paste according to claim 1 of the present invention is a mixture of a solder powder and a flux component, and 20 wt% or more of the solder particles of the solder powder have a particle size of at least 90 μm. Has a diameter
Moreover, the content of the above-mentioned flux component is 6 wt% or more, 1
It is 2 wt% or less.

【0010】この発明の請求項2に係わる接合方法は、
請求項1記載のソルダペーストをスクリーン印刷により
第1の被接合部材に供給し、その上に第2の被接合部材
を搭載した後、熱処理を施すことによって、上記ソルダ
ペースト中のはんだ粉末を溶融させるとともに、フラッ
クス成分を外部に排出させ、その後冷却処理を施して溶
融はんだを凝固させて、はんだ層による接合を形成する
ものである。
A joining method according to claim 2 of the present invention is
The solder paste in the solder paste is melted by supplying the solder paste according to claim 1 to a first member to be joined by screen printing, mounting a second member to be joined thereon, and then performing heat treatment. At the same time, the flux component is discharged to the outside, and then the cooling process is performed to solidify the molten solder to form a joint by the solder layer.

【0011】この発明の請求項3に係わる接合方法は、
請求項2において、冷却処理を施して溶融はんだを凝固
させた後、被接合部材およびはんだ層の外側に付着した
フラックスの固形成分の残渣を洗浄液を用いて除去する
ものである。
The joining method according to claim 3 of the present invention is
In the second aspect of the present invention, after the cooling process is performed to solidify the molten solder, the residue of the solid component of the flux adhered to the outside of the member to be joined and the solder layer is removed by using a cleaning liquid.

【0012】この発明の請求項4に係わる半導体装置
は、金属基板と、この金属基板上に搭載された表裏面に
金属層が形成された絶縁基板と、この絶縁基板上に搭載
された半導体チップとを有し、上記金属基板と上記絶縁
基板との接合部、および上記絶縁基板と上記半導体チッ
プとの接合部の一方または双方を請求項1記載のソルダ
ペーストを用いて形成したものである。
According to a fourth aspect of the present invention, there is provided a semiconductor device, a metal substrate, an insulating substrate having metal layers formed on the front and back surfaces of the metal substrate, and a semiconductor chip mounted on the insulating substrate. And a joint between the metal substrate and the insulating substrate and a joint between the insulating substrate and the semiconductor chip are formed by using the solder paste according to claim 1.

【0013】[0013]

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

実施の形態1.以下、この発明の実施の形態1について
説明する。組成がSn27/Sb3/Pb70でいろい
ろな粒径を持つ球形のはんだ粉末を目開きが63μmの
メッシュでふるいにかけ、網目を通過したはんだ粉末を
取出して粒径分布が63μm以下のはんだ粉末を用意し
た。同様に目開きが150μmのメッシュでふるいにか
け、網目を通過したものをさらに目開き90μmのメッ
シュでふるいにかけ、網目を通過しなかったはんだ粉末
を取り出し、粒径分布が90〜150μmのはんだ粉末
を用意した。
Embodiment 1 FIG. Hereinafter, Embodiment 1 of the present invention will be described. Spherical solder powder having a composition of Sn27 / Sb3 / Pb70 and various particle sizes was sieved through a mesh having a mesh size of 63 μm, and the solder powder passing through the mesh was taken out to prepare a solder powder having a particle size distribution of 63 μm or less. . Similarly, it is sieved with a mesh having a mesh size of 150 μm, and the powder that has passed through the mesh is further sieved with a mesh having a mesh size of 90 μm. I prepared.

【0014】次に、上記粒径63μm以下のはんだ粉末
に上記粒径90〜150μmのはんだ粉末を混合比率を
変えて添加したはんだ粉末に塩素含有量が0.20wt
%のフラックス成分を8wt%混合して数種類のソルダ
ペーストを作成した。このとき上記粒径90〜150μ
mのはんだ粉末の混合比率は、この発明の例として20
wt%、30wt%、40wt%および50wt%と
し、比較例として0wt%および10wt%とした。
Next, the chlorine content of 0.20 wt.% Is added to the solder powder having the particle diameter of 63 μm or less and the solder powder having the particle diameter of 90 to 150 μm added at different mixing ratios.
% Flux component was mixed at 8 wt% to prepare several kinds of solder paste. At this time, the particle size is 90 to 150 μ
The mixing ratio of the solder powder of m is 20 as an example of the present invention.
wt%, 30 wt%, 40 wt% and 50 wt%, and 0 wt% and 10 wt% as comparative examples.

【0015】幅45mm、長さ91mm、厚さ3mmの
銅板の表面にニッケルめっきを施した金属基板4上に、
作成した上記ソルダペーストをスクリーン印刷により供
給して幅38mm、長さ60mm、厚さ0.4mmのソ
ルダペースト層7bを形成した。次に、表面に厚さ0.
3mmの銅/ニッケルの金属層2aによる配線パターン
が形成され、裏面に幅38mm、長さ60mm、厚さ
0.3mmの銅/ニッケルの金属層2bが形成された、
幅39mm、長さ61mm、厚さ1mmのセラミクス基
板1を用意し、このセラミクス基板1を上記ソルダペー
スト層7bが形成された金属基板4上に重ね合わせる。
その後、炉内を窒素で満たして酸素濃度を100ppm
としたリフロー炉で250℃以上(最高温度275℃)
で3分間保持して、ソルダペースト中のはんだ粉末を溶
融させ、スクラブ工程を行わずに冷却し、はんだ層6b
を凝固させて接合を行った。
On a metal substrate 4 having a nickel plate on the surface of a copper plate having a width of 45 mm, a length of 91 mm and a thickness of 3 mm,
The prepared solder paste was supplied by screen printing to form a solder paste layer 7b having a width of 38 mm, a length of 60 mm and a thickness of 0.4 mm. Next, a thickness of 0.
A wiring pattern was formed by a 3 mm copper / nickel metal layer 2a, and a copper / nickel metal layer 2b having a width of 38 mm, a length of 60 mm and a thickness of 0.3 mm was formed on the back surface.
A ceramic substrate 1 having a width of 39 mm, a length of 61 mm, and a thickness of 1 mm is prepared, and the ceramic substrate 1 is superposed on the metal substrate 4 on which the solder paste layer 7b is formed.
After that, the furnace is filled with nitrogen so that the oxygen concentration is 100 ppm.
250 ℃ or more in the reflow furnace (maximum temperature 275 ℃)
Hold for 3 minutes to melt the solder powder in the solder paste and cool without performing a scrubbing process to obtain the solder layer 6b.
Was solidified and joined.

【0016】以上のように作成した試料の接合部を超音
波顕微鏡で観察し、接合面に存在するボイドの面積率
(以下、ボイド率と称す)を測定し、結果を図1に示
す。図1に示すように、フラックス成分の含有量8wt
%のソルダペーストでは、90μm以上の粒径のはんだ
粉末の混合比率が、比較例である0wt%および10w
t%の時は、ボイド率が最大で5%を越えるが、この発
明の例である20wt%以上(20wt%、30wt
%、40wt%および50wt%)の時は、ボイド率が
最大でも3%以下となり、ボイド不良が低減できた。
The joint portion of the sample prepared as described above is observed with an ultrasonic microscope, and the area ratio of voids present on the joint surface (hereinafter referred to as the void ratio) is measured. The results are shown in FIG. As shown in FIG. 1, the content of the flux component is 8 wt.
% Solder paste, the mixing ratio of solder powder having a particle size of 90 μm or more is 0 wt% and 10 w, which are comparative examples.
At t%, the void ratio exceeds 5% at the maximum, but it is 20 wt% or more (20 wt%, 30 wt%) which is an example of the present invention.
%, 40 wt% and 50 wt%), the void ratio was 3% or less at the maximum, and void defects could be reduced.

【0017】ところで、従来のソルダペーストは、上述
したように75μm以下の粒径分布を持つはんだ粉末に
9〜15wt%の含有量でフラックス成分を混合したも
のであった。フラックス成分の残留に起因するボイドの
発生を低減させるため、はんだ粉末の粒径をそのままに
してフラックス成分の含有量を低減させてみると、例え
ばフラックス成分の含有量が8wt%のソルダペースト
で接合を行うと、接合部のフラクッス量は十分に低減さ
れず大きな効果が得られなかった。さらにフラックス成
分の含有量が7wt%のソルダペーストでは、はんだ粉
末の表面酸化膜が十分に除去されず、ぬれ不良に起因し
て逆にボイドが増加してしまった。
By the way, the conventional solder paste is a solder powder having a particle size distribution of 75 μm or less and a flux component mixed in a content of 9 to 15 wt%, as described above. In order to reduce the generation of voids due to the residual flux component, the particle size of the solder powder is left unchanged and the content of the flux component is reduced. For example, solder paste containing 8 wt% of the flux component is used for bonding. However, the flux amount at the joint was not sufficiently reduced, and a large effect was not obtained. Further, with the solder paste containing 7 wt% of the flux component, the surface oxide film of the solder powder was not sufficiently removed, and voids increased due to poor wetting.

【0018】この発明による上記実施の形態1では90
μm以上の粒径のはんだ粉末の混合比率を20wt%以
上と大粒径のはんだ粉末を用い、フラックス成分の含有
量も8wt%と従来のものより低くした。なお、ソルダ
ペーストの印刷性の点から、はんだ粉末の最大粒径は印
刷マスクの厚さの1/2程度以下が望ましく、上記実施
の形態1においても、はんだ粉末の粒径分布は90〜1
50μmに設定した。
In the above-described first embodiment according to the present invention, 90
The mixing ratio of the solder powder having a particle diameter of μm or more was 20 wt% or more, the solder powder having a large particle diameter was used, and the content of the flux component was 8 wt%, which was lower than the conventional one. From the viewpoint of the printability of the solder paste, it is desirable that the maximum particle size of the solder powder be about ½ or less of the thickness of the print mask. Also in the first embodiment, the particle size distribution of the solder powder is 90 to 1
It was set to 50 μm.

【0019】このように大粒径のはんだ粉末を用いるこ
とにより、はんだ粉末の粒子数も減少しソルダペースト
の密度も減少する。その上フラックス成分の含有量が8
wt%と低いため、ソルダペーストの単位体積当たりの
フラックス量を大きく低減することができる。このた
め、接合面積が大きい部材の接合において、ソルダペー
ストの印刷量が多くなっても接合部のフラックス量が十
分低減できるため、フラックス成分の残留に起因するボ
イドが低減できる。なお、接合部のフラックス量を低減
しても、はんだ粉末の粒径が大きいため接合部の全はん
だ粉末の表面積も低減され、はんだ粉末の表面酸化膜は
十分除去可能となる。またさらに、はんだ粉末が大粒径
のため、はんだ粉末間の隙間が大きくなり、接合部に巻
き込まれた雰囲気やフラックス成分から発生する気体が
外部へ排出され易くなり、ボイドの原因となる気泡の発
生を抑制することができる。また、フラックスの固形成
分の外部に排出されやすくなる。このような相乗作用に
よりボイドの発生を著しく低減することが可能になり、
図1に示す結果を得た。また、90μm以上の粒径のは
んだ粉末の混合比率が20wt%に満たない場合は、上
記のような作用、効果が十分に得られないことが、比較
例により判明した。
By using the large-diameter solder powder in this way, the number of particles of the solder powder is reduced and the density of the solder paste is also reduced. In addition, the content of flux component is 8
Since it is as low as wt%, the flux amount per unit volume of the solder paste can be greatly reduced. For this reason, in joining members having a large joining area, the flux amount at the joining portion can be sufficiently reduced even when the printing amount of the solder paste is large, and thus voids due to the residual flux components can be reduced. Even if the amount of flux at the joint is reduced, the surface area of the entire solder powder at the joint is reduced because the particle size of the solder powder is large, and the surface oxide film of the solder powder can be sufficiently removed. Furthermore, since the solder powder has a large particle size, the gap between the solder powders becomes large, and the gas generated from the atmosphere entrained in the joint and the flux component is easily discharged to the outside, which may cause voids. Occurrence can be suppressed. In addition, the solid components of the flux are easily discharged to the outside. By such a synergistic effect, it becomes possible to significantly reduce the occurrence of voids,
The results shown in FIG. 1 were obtained. In addition, it was found from a comparative example that when the mixing ratio of the solder powder having a particle diameter of 90 μm or more is less than 20 wt%, the above-described action and effect cannot be sufficiently obtained.

【0020】実施の形態2.次に、この発明の実施の形
態2について説明する。組成がSn27/Sb3/Pb
70で粒径分布が63μm以下のはんだ粉末に、粒径分
布が90〜150μmのはんだ粉末を20wt%混合
し、塩素含有量が0.20wt%のフラックス成分を含
有量を変えて混合して、数種類のソルダペーストを作成
した。このとき、フラックス成分の含有量は、この発明
の例として6wt%、8wt%および12wt%とし、
比較例として13wt%および15wt%とした。上記
実施の形態1と同様に、金属基板4に作成した上記ソル
ダペーストから成るソルダペースト層7bを形成し、表
裏面に金属層2a,2bが形成されたセラミクス基板1
を重ね合わせた後、熱処理を施してソルダペースト中の
はんだ粉末を溶融させ、その後冷却してはんだ層6bを
凝固させて接合を行った。
Embodiment 2 Next, a second embodiment of the present invention will be described. Composition is Sn27 / Sb3 / Pb
70 wt% of the solder powder having a particle size distribution of 63 μm or less is mixed with 20 wt% of a solder powder having a particle size distribution of 90 to 150 μm, and a flux component having a chlorine content of 0.20 wt% is mixed and mixed. I made several kinds of solder paste. At this time, the content of the flux component is 6 wt%, 8 wt% and 12 wt% as an example of the present invention,
As comparative examples, 13 wt% and 15 wt% were used. Similar to the first embodiment, the ceramic substrate 1 in which the solder paste layer 7b made of the above-mentioned solder paste formed on the metal substrate 4 is formed and the metal layers 2a and 2b are formed on the front and back surfaces are formed.
After superposing, the solder powder in the solder paste was melted by heat treatment, and then cooled to solidify the solder layer 6b for joining.

【0021】以上のように作成した試料の接合部を超音
波顕微鏡で観察して接合面のボイド率を測定し、結果を
図2に示す。図2に示すように、粒径90μm以上のは
んだ粉末が20wt%混合したソルダペーストでは、フ
ラックス成分の含有量が、比較例である13wt%およ
び15wt%の時はボイド率が最大で4〜5wt%程度
となるが、この発明例である6wt%〜12wt%(6
wt%、8wt%および12wt%)の時は、ボイド率
が最大でも3%程度となり、ボイド不良が低減できた。
なお、フラックス成分の含有量が6wt%に満たない
と、印刷性が著しく低下しソルダペーストとして機能し
ないものであった。
The joint portion of the sample prepared as described above is observed with an ultrasonic microscope to measure the void ratio of the joint surface, and the result is shown in FIG. As shown in FIG. 2, in the solder paste in which 20 wt% of solder powder having a particle diameter of 90 μm or more is mixed, when the content of the flux component is 13 wt% and 15 wt% which are comparative examples, the maximum void ratio is 4 to 5 wt. %, But it is 6 wt% to 12 wt% (6
wt%, 8 wt% and 12 wt%), the void ratio was about 3% at maximum, and void defects could be reduced.
When the content of the flux component was less than 6 wt%, the printability was remarkably reduced and the solder paste did not function.

【0022】この実施の形態2においても、上記実施の
形態1と同様に、ソルダペースト中のフラックス成分の
含有量が6〜12wt%と低いうえに大粒径のはんだ粉
末を用いたために、ソルダペーストの単位体積当たりの
フラックス量を大きく低減できて接合部のフラックス量
が十分低減できる。また、はんだ粉末が大粒径のため接
合部に巻き込まれた雰囲気、フラックス成分から発生す
る気体、フラックスの固形成分が外部に排出されやす
く、これらのことによりボイドの発生を著しく低減する
ことが可能になり、図2に示す結果を得た。また、フラ
ックス成分の含有量が12wt%を越えると、接合部の
フラックス量の低減が十分ではなくフラックス成分の残
留に起因するボイドの発生が抑制できないことが、比較
例により判明した。
Also in the second embodiment, as in the first embodiment, the content of the flux component in the solder paste is as low as 6 to 12 wt% and the solder powder having a large particle size is used. The amount of flux per unit volume of paste can be greatly reduced, and the amount of flux at the joint can be sufficiently reduced. Also, since the solder powder has a large particle size, the atmosphere caught in the joint, the gas generated from the flux component, and the solid component of the flux are easily discharged to the outside, which can significantly reduce the occurrence of voids. Then, the results shown in FIG. 2 were obtained. Further, it was found from the comparative example that when the content of the flux component exceeds 12 wt%, the reduction of the flux amount at the joint is not sufficient and the generation of voids due to the residual flux component cannot be suppressed.

【0023】実施の形態3.次に、この発明の実施の形
態3について説明する。組成がSn63/Pb37でい
ろいろな粒径を持つ球形のはんだ粉末を目開きが106
μmのメッシュでふるいにかけ、網目を通過したものを
さらに目開き90μmのメッシュでふるいにかけ、網目
を通過したものをさらに目開き45μmのメッシュでふ
るいにかけた。次に、粒径45〜90μmのはんだ粉末
と粒径90〜106μmのはんだ粉末を、粒径90〜1
06μmのものが40wt%となるように混合し、塩素
含有量が0.20wt%のフラックス成分を8wt%混
合してこの発明の例であるソルダペーストAを作成し
た。また、粒径45μm以下のはんだ粉末に塩素含有量
が0.20wt%のフラックス成分を14wt%混合し
て、比較例として従来技術におけるソルダペーストBを
作成した。
Embodiment 3 FIG. Next, a third embodiment of the invention will be described. The composition is Sn63 / Pb37 and spherical solder powder with various grain sizes has a mesh of 106
It was sifted with a mesh having a mesh size of .mu.m, passed through the mesh, further sieved with a mesh having a mesh size of 90 .mu.m, and passed through the mesh with a mesh having a mesh size of 45 .mu.m. Next, the solder powder having a particle size of 45 to 90 μm and the solder powder having a particle size of 90 to 106 μm are mixed with a particle size of 90 to 1
The solder paste A, which is an example of the present invention, was prepared by mixing so as to have a content of 06 μm so as to be 40 wt%, and mixing 8 wt% of a flux component having a chlorine content of 0.20 wt%. Further, 14 wt% of a flux component having a chlorine content of 0.20 wt% was mixed with a solder powder having a particle diameter of 45 μm or less to prepare a solder paste B in the related art as a comparative example.

【0024】上記実施の形態1で作成した試料(セラミ
クス基板1を金属基板4上に接合したもの)のうち、粒
径90〜150μmのはんだ粉末の混合比率を40wt
%としたソルダペースト、すなわち、粒径63μm以下
のはんだ粉末に粒径90〜150μmのはんだ粉末を4
0wt%混合し、塩素含有量が0.20wt%のフラッ
クス成分を8wt%混合して作成したソルダペーストを
用いたものを、この発明例に用いる試料Aとする。同様
に粒径90〜150μmのはんだ粉末の混合比率を0w
t%としたソルダペースト、すなわち粒径63μm以下
のはんだ粉末に塩素含有量が0.20wt%のフラック
ス成分を8wt%混合して作成したソルダペーストを用
いたものを、比較例に用いる試料Bとする。
In the sample prepared in the first embodiment (ceramics substrate 1 bonded to metal substrate 4), the mixing ratio of solder powder having a particle size of 90 to 150 μm is 40 wt.
% Of the solder paste, that is, solder powder having a particle size of 63 μm or less and solder powder having a particle size of 90 to 150 μm.
Sample A used in this invention example is a solder paste prepared by mixing 0 wt% and 8 wt% of a flux component having a chlorine content of 0.20 wt%. Similarly, the mixing ratio of the solder powder having a particle size of 90 to 150 μm is 0 w.
Sample B used in the comparative example is a solder paste having t%, that is, a solder paste prepared by mixing 8 wt% of a flux component having a chlorine content of 0.20 wt% with a solder powder having a particle diameter of 63 μm or less. To do.

【0025】次に、試料A、Bのセラミクス基板1表面
の金属層2a上の所定領域に、ソルダペーストA、Bを
それぞれスクリーン印刷により供給して幅6.1mm、
長さ6.1mm、厚さ0.2mmのソルダペースト層7
aを形成した。このときソルダペーストAは試料Aに、
ソルダペーストBは試料Bに用いる。次に、ソルダペー
スト層7aが形成された試料A、Bのそれぞれに、幅
6.1mm、長さ6.1mm、厚さ0.25mmの半導
体チップとしてのトランジスタチップ3を6個搭載し、
その後、炉内を窒素で満たして酸素濃度を100ppm
としたリフロー炉で200℃以上(最高温度235℃)
で2分間保持して、ソルダペーストA、B中のはんだ粉
末を溶融させ、スクラブ工程を行わずに冷却し、はんだ
層6aを凝固させて接合を行った。これにより大電流・
高発熱の半導体装置を形成した。この後、上記半導体装
置外部に付着したフラックス残渣を洗浄液により除去し
た。
Next, solder pastes A and B were respectively screen-printed to predetermined regions on the metal layer 2a on the surface of the ceramics substrate 1 of the samples A and B, and the width was 6.1 mm.
Solder paste layer 7 having a length of 6.1 mm and a thickness of 0.2 mm
a was formed. At this time, the solder paste A is the sample A,
The solder paste B is used for the sample B. Next, on each of the samples A and B on which the solder paste layer 7a was formed, six transistor chips 3 as a semiconductor chip having a width of 6.1 mm, a length of 6.1 mm and a thickness of 0.25 mm were mounted,
After that, the furnace is filled with nitrogen so that the oxygen concentration is 100 ppm.
200 ℃ or more in the reflow furnace (maximum temperature 235 ℃)
Was held for 2 minutes to melt the solder powder in the solder pastes A and B, and to cool without performing the scrubbing process to solidify the solder layer 6a for joining. This results in a large current
A semiconductor device with high heat generation was formed. After that, the flux residue attached to the outside of the semiconductor device was removed by a cleaning liquid.

【0026】以上のように作成した2種類の半導体装置
について、それぞれトランジスタチップ3とセラミクス
基板1との接合部を超音波顕微鏡で観察し、接合面のボ
イド率を測定した。さらに、放熱性能を調べるため、ト
ランジスタチップ3とセラミクス基板1表面の金属層2
aをワイヤ5で接続し(図3参照)、その後トランジス
タチップ3のコレクタ・ベース間に50Vの電圧を印加
し、コレクタ・エミッタ間に1Aの電流を10秒間流し
てトランジスタチップ3を発熱させ、トランジスタ特性
を測定して発熱によるトランジスタチップ3の破壊率を
調べた。それぞれの結果を表1に示す。
With respect to the two types of semiconductor devices produced as described above, the joint portion between the transistor chip 3 and the ceramics substrate 1 was observed with an ultrasonic microscope, and the void ratio of the joint surface was measured. Further, in order to examine the heat dissipation performance, the metal layer 2 on the surface of the transistor chip 3 and the ceramic substrate 1 is examined.
a is connected by a wire 5 (see FIG. 3), then a voltage of 50 V is applied between the collector and the base of the transistor chip 3, and a current of 1 A is applied between the collector and the emitter for 10 seconds to heat the transistor chip 3. The transistor characteristics were measured to examine the destruction rate of the transistor chip 3 due to heat generation. Table 1 shows the results.

【0027】[0027]

【表1】 [Table 1]

【0028】表1に示すように、試料Aとソルダペース
トAとを用いて作成したこの発明の例である半導体装置
は、ボイド率も1%以下で、発熱によるトランジスタチ
ップ3の破壊も無く、試料BとソルダペーストBとを用
いて作成した比較例と比べ信頼性が著しく向上したもの
である。なお、試料Aにおいて、金属基板4とセラミク
ス基板1との接合におけるボイド率も1%以下(図1参
照)であり、このようにボイドの発生が低減されれば、
トランジスタチップ3と金属基板4との間の熱の流路が
狭められることなく、放熱能力が向上し、信頼性の高い
半導体装置が得られる。また、ソルダペーストAは、フ
ラックス成分が十分に低減されているため、接合完了後
に半導体装置外部に付着するフラックス残渣も低減で
き、それによってこのフラックス残渣を洗浄する洗浄液
の長寿命化を図ることができた。
As shown in Table 1, the semiconductor device, which is an example of the present invention prepared by using the sample A and the solder paste A, has a void ratio of 1% or less, and the transistor chip 3 is not destroyed by heat generation. The reliability is remarkably improved as compared with the comparative example prepared using the sample B and the solder paste B. In Sample A, the void ratio in the bonding between the metal substrate 4 and the ceramics substrate 1 is also 1% or less (see FIG. 1), and if the generation of voids is reduced in this way,
The heat flow path between the transistor chip 3 and the metal substrate 4 is not narrowed, the heat dissipation capability is improved, and a highly reliable semiconductor device can be obtained. Further, since the solder paste A has a sufficiently reduced flux component, it is possible to reduce the flux residue attached to the outside of the semiconductor device after the joining is completed, thereby extending the life of the cleaning liquid for cleaning the flux residue. did it.

【0029】[0029]

【発明の効果】以上のようにこの発明によると、ソルダ
ペーストのはんだ粉末の20wt%以上が少なくとも9
0μmの粒径を有し、フラックス成分の含有量を6wt
%以上、12wt%以下としたため、ソルダペーストの
印刷性、ぬれ性を損なうことなく、このソルダペースト
を用いた接合部のボイド不良を安定して低減することが
できる。また、このような効果を生産性の低下や製造コ
ストの増加等を招くことなく容易に得ることができる。
これにより、比較的接合面積の大きい部材の接合の信頼
性を容易に格段と向上できる。
As described above, according to the present invention, 20 wt% or more of the solder powder of the solder paste is at least 9%.
It has a particle size of 0 μm and contains 6 wt% of flux component.
% Or more and 12 wt% or less, it is possible to stably reduce void defects in the joint portion using the solder paste without impairing the printability and wettability of the solder paste. Further, such an effect can be easily obtained without lowering productivity and increasing manufacturing cost.
As a result, the reliability of the joining of the members having a relatively large joining area can be significantly improved.

【0030】また、この発明によると、上記ソルダペー
ストをスクリーン印刷により供給し、その上に被接合部
材を搭載した後、熱処理によりソルダペースト中のはん
だ粉末を溶融させるとともにフラックス成分を外部へ排
出させ、その後冷却処理により溶融はんだを凝固させて
接合を行うため、上記効果が確実に得られる。
Further, according to the present invention, the solder paste is supplied by screen printing, and after the members to be joined are mounted thereon, the solder powder in the solder paste is melted and the flux component is discharged to the outside by heat treatment. After that, since the molten solder is solidified by the cooling treatment and the joining is performed, the above-mentioned effect is surely obtained.

【0031】また、この発明によると、上記ソルダペー
ストによる接合を行った後、洗浄液を用いてフラックス
残渣を除去するため、フラックス残渣が低減でき、洗浄
液の長寿命化が図れる。
Further, according to the present invention, since the flux residue is removed by using the cleaning liquid after the bonding with the solder paste, the flux residue can be reduced and the life of the cleaning liquid can be extended.

【0032】また、この発明によると、金属基板と絶縁
基板との接合部および上記絶縁基板と半導体チップとの
接合部を、上記ソルダペーストを用いて形成したため、
接合部のボイド不良が低減できて半導体装置の放熱能力
が向上し、信頼性の高い半導体装置が得られる。特に大
電流・高発熱の半導体装置において大きな効果が得られ
る。
Further, according to the present invention, since the joint between the metal substrate and the insulating substrate and the joint between the insulating substrate and the semiconductor chip are formed by using the solder paste,
A void defect in the joint can be reduced, the heat dissipation capability of the semiconductor device is improved, and a highly reliable semiconductor device can be obtained. In particular, a great effect can be obtained in a semiconductor device with large current and high heat generation.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 この発明の実施の形態1における効果を説明
する図である。
FIG. 1 is a diagram illustrating an effect in a first embodiment of the present invention.

【図2】 この発明の実施の形態2における効果を説明
する図である。
FIG. 2 is a diagram for explaining effects in the second embodiment of the present invention.

【図3】 半導体装置の構造を示す断面図である。FIG. 3 is a cross-sectional view showing the structure of a semiconductor device.

【符号の説明】[Explanation of symbols]

1 絶縁基板、2a,2b 金属層、3 半導体チッ
プ、4 金属基板、6a,6b はんだ層。
1 insulating substrate, 2a, 2b metal layer, 3 semiconductor chip, 4 metal substrate, 6a, 6b solder layer.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 はんだ粉末とフラックス成分とを混合し
たソルダペーストにおいて、上記はんだ粉末のはんだ粒
子の20wt%以上が少なくとも90μmの粒径を有
し、しかも上記フラックス成分の含有量が6wt%以
上、12wt%以下であることを特徴とするソルダペー
スト。
1. In a solder paste in which a solder powder and a flux component are mixed, 20 wt% or more of the solder particles of the solder powder have a particle size of at least 90 μm, and the content of the flux component is 6 wt% or more, Solder paste characterized by being 12 wt% or less.
【請求項2】 請求項1記載のソルダペーストをスクリ
ーン印刷により第1の被接合部材に供給し、その上に第
2の被接合部材を搭載した後、熱処理を施すことによっ
て、上記ソルダペースト中のはんだ粉末を溶融させると
ともに、フラックス成分を外部に排出させ、その後冷却
処理を施して溶融はんだを凝固させて、はんだ層による
接合を形成することを特徴とする接合方法。
2. The solder paste according to claim 1 is supplied to a first member to be joined by screen printing, and a second member to be joined is mounted on the first member to be joined, followed by heat treatment. The method of joining according to claim 1, wherein the solder powder is melted, the flux component is discharged to the outside, and then a cooling treatment is performed to solidify the molten solder to form a joint by a solder layer.
【請求項3】 冷却処理を施して溶融はんだを凝固させ
た後、被接合部材およびはんだ層の外側に付着したフラ
ックスの固形成分の残渣を洗浄液を用いて除去すること
を特徴とする請求項2記載の接合方法。
3. The solidified residue of the flux adhered to the outside of the members to be joined and the solder layer is removed using a cleaning liquid after the molten solder is solidified by cooling. The joining method described.
【請求項4】 金属基板と、この金属基板上に搭載され
た、表裏面に金属層が形成された絶縁基板と、この絶縁
基板上に搭載された半導体チップとを有し、上記金属基
板と上記絶縁基板との接合部、および上記絶縁基板と上
記半導体チップとの接合部の一方または双方を請求項1
記載のソルダペーストを用いて形成したことを特徴とす
る半導体装置。
4. A metal substrate, an insulating substrate mounted on the metal substrate, having metal layers formed on front and back surfaces, and a semiconductor chip mounted on the insulating substrate. One or both of the joint between the insulating substrate and the joint between the insulating substrate and the semiconductor chip.
A semiconductor device formed using the described solder paste.
JP7279193A 1995-10-26 1995-10-26 Solder paste, joining method using this solder paste and semiconductor device Pending JPH09122966A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7279193A JPH09122966A (en) 1995-10-26 1995-10-26 Solder paste, joining method using this solder paste and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7279193A JPH09122966A (en) 1995-10-26 1995-10-26 Solder paste, joining method using this solder paste and semiconductor device

Publications (1)

Publication Number Publication Date
JPH09122966A true JPH09122966A (en) 1997-05-13

Family

ID=17607738

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7279193A Pending JPH09122966A (en) 1995-10-26 1995-10-26 Solder paste, joining method using this solder paste and semiconductor device

Country Status (1)

Country Link
JP (1) JPH09122966A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009158816A (en) * 2007-12-27 2009-07-16 Rohm Co Ltd Semiconductor apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009158816A (en) * 2007-12-27 2009-07-16 Rohm Co Ltd Semiconductor apparatus

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