JPH09119971A - Signal processing method for gps receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal processing method for GPS receiver with a simple configuration, less power consumption, and high-sensitivity characteristics where the configuration of an analog circuit can be simplified since the frequency of the middle frequency signal which can be inputted by a logic circuit is low and a high-frequency intermediate frequency signal can be inputted to the logic circuit. SOLUTION: A frequency conversion circuit consisting of a local oscillator 23, a mixer 6, and a filter 24 and a sampling circuit to a logic signal consisting of a comparator 9 and a latch 25 are provided, the frequency of an intermediate frequency signal to be sampled is set to a frequency which is higher than Nyquist frequency which is equivalent to the half of the sampling frequency, an interference constituent with the intermediate frequency signal generated by sampling is set to a reception signal by the succeeding processing. Therefore, a high-frequency intermediate frequency signal can be sampled with a period which is equivalent to before, thus easily suppressing an image signal by a filter 3 and achieving a signal processing circuit for constituting a high- sensitivity receiver without increasing the scale and the power consumption of a logic circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a GPS (Global Positioning System) for receiving a navigation satellite signal and measuring the position.
GPS receivers, such as NAVSTAR satellites operated by the United States and GLONASS satellites operated by the Russian Republic, measure the phase of spread spectrum signals and measure the time indicated by the satellite signals to determine the position. In the above, the present invention relates to a signal processing method for accurately measuring a received satellite signal with a simple processing circuit.

[0002]

2. Description of the Related Art In recent years, GPS receivers have been widely used as position sensors for car navigation systems, navigation devices for ships, and navigation devices for aircraft.

A signal processing method of the conventional GPS receiver disclosed in Japanese Patent Laid-Open No. 63-015182 will be described below. FIG. 4 shows a conventional GPS using the NAVSTAR satellite.
It is a block block diagram which shows the signal processing method in a receiver. In FIG. 4, 1 is a plurality of GPS satellites (3 in the example in the figure).
2) an antenna for receiving a GPS satellite signal (L1) having a carrier frequency of 1.57542 GHz, 3 a filter for filtering the satellite signal, 4 an amplifier for amplifying the satellite signal, 5 an intermediate frequency signal for the amplified satellite signal Local oscillation signal for frequency conversion to
A local oscillator that outputs 1.571328 GHz, 6 is a mixer that mixes this local oscillation signal with a satellite signal, and 7 is frequency converted
This is a filter for filtering the intermediate frequency signal of 4.092 MHz, and the local oscillator 5, mixer 6 and filter 7 constitute a frequency conversion circuit.

Reference numeral 8 denotes an amplifier for amplifying the intermediate frequency signal,
Reference numeral 9 is a comparator for binarizing the intermediate frequency signal by comparing it with the reference potential V, 10 is a latch for sampling the binarized intermediate frequency signal, and 11 is a frequency converter for converting the intermediate frequency signal into a base band. A local oscillator, 12 is a mixer for mixing the outputs of the local oscillator 11.

Further, 13 is a pseudo noise generator for generating a unique pseudo noise code for each of the plurality of satellites 1, and 14 is
For each of the plurality of satellites 1, it is a demodulator that mixes the satellite signal and the output of the pseudo noise generator 13 to obtain the correlation, and performs time integration at a fixed cycle, and includes a mixer 14a and a filter 14b. Fifteen
Is a switch for time-sequentially switching the output of the demodulator 14 time-integrated for each of a plurality of satellites, and 16 is a time-sequentially regenerated carrier for tracking a carrier, which corrects the Doppler shift and phase of the satellite signal, The numerically controlled oscillator 17 outputs a mixer for sequentially converting the output signal of the demodulator 14 into an orthogonal frequency by the numerically controlled oscillator 16 for each satellite.
18 is a switch for sequentially switching the outputs I and Q of the mixer 17,
Reference numeral 19 is an adder for cumulatively adding the output of the mixer 17, and 20 is a RAM (random access memory) for storing the intermediate result of the cumulative addition. The adder 19 and the RAM 20 constitute a cumulative adder.

Reference numeral 21 is a control unit for controlling the pseudo noise generator 13 and the numerical control oscillator 16 so as to track the satellite signal by using the cumulative addition value of the in-phase component and the quadrature component of the satellite signal output from the mixer 17. Reference numeral 22 is a reference oscillator that outputs a clock signal of 16.368 MHz that determines the reference timing of the receiver.

The operation of the GPS receiver configured as above will be described. First, the antenna 2 receives radio waves (satellite signals) from a plurality of GPS satellites 1. The received signal (satellite signal) is filtered by the filter 3 to remove unnecessary signals and then amplified by the amplifier 4. Furthermore, the frequency conversion circuit composed of the local oscillator 5, the mixer 6 and the filter 7 converts the frequency (4.092).
The frequency of the intermediate frequency signal at MHz = 1.57542GHz-1.571328GHz is a signal centered on 4.092MHz.

Next, the intermediate frequency signal is amplified and limited in amplitude by an amplifier 8 and then compared with a reference potential V by a comparator 9 to be converted into a binary logic signal. The binarized logic signal is sampled in the latch 10 by the clock signal of 16.368 MHz output from the reference oscillator 22. After that, all signals are processed as discrete values in the logic circuit or the arithmetic circuit. The sampled signal is subjected to orthogonal frequency conversion by the mixer 12 by the 4.092 MHz I signal output from the local oscillator 11 and the Q signal having a 90 ° phase difference. The frequency-converted satellite signals I and Q described above are subjected to independent signal processing for each satellite received.

Next, the pseudo noise generator 13 outputs a pseudo noise code unique to each satellite received. Here, the satellite-specific pseudo-noise code has a code rate of 1.
The code length is 1023 bits at 023 Mbps, and the cycle is 1 msec. In the demodulator 14, the mixer 14a mixes the received signal and the pseudo noise code for each satellite. The phase of the pseudo noise code is about 61 μsec at the timing of 16.368 MHz which is the clock for signal processing.
The discrete value quantized in units of is set in the pseudo noise generator 13. The demodulator 14 mixes the received signal and the pseudo noise code, and then the filter 14b smoothes the sampled frequency up to several tens of kHz by time integration.

The numerically controlled oscillator 16 oscillates a reproduction carrier signal for each satellite and outputs orthogonal I and Q signals. The mixer 17 converts the smoothed signal into an orthogonal frequency by the output of the I and Q signals. This orthogonal frequency conversion is performed on a plurality of satellites in a time division manner because the signal sampling frequency is low. The switch 18 converts the in-phase I signal component and the quadrature Q signal component output from the mixer 17 into a time-sequential signal.

A cumulative adder composed of the adder 19 and the RAM 20 cumulatively adds the I and Q signal outputs of the mixer 17 for each satellite. The period of addition is 1 msec from the beginning to the end of the C / A code. The control unit 21 receives the cumulative addition result of 1 msec and controls the numerically controlled oscillator 16 so that the amplitude of the Q signal component, which is the cumulative addition result, becomes small, thereby tracking the carrier wave of the satellite signal. Furthermore, a pseudo noise generator 1 with 1 msec as a break
By moving the phase output by 3, the change in the amplitude of the I signal component that is the cumulative addition result is examined, and by measuring the phase difference of the pseudo noise code between the pseudo noise generator 13 and the satellite signal from this change, Track the pseudo noise of satellite signals.

Further, the control unit 21 controls the I as the cumulative addition result.
Depending on the sign of the signal component, it is sent from the satellite by BPSK modulation.
Receives 50 bps data. Then, by measuring the phase of the pseudo-noise code and the timing of the data of 50 bps,
Find the time when the satellite emitted radio waves. Further, the control unit 21 calculates the antenna position of the receiver by using the orbit information and time information received for a plurality of satellites and the measured time, and outputs the antenna position to the outside.

[0013]

However, in the conventional configuration shown in FIG. 4, the frequency of the intermediate frequency signal input to the logic circuit from the local oscillator 11 is sampled in the latch 10 with the clock signal of 16.368 MHz. 4.092MHz
I chose a low frequency. This is because if the logic circuit operates too fast, power consumption increases and design becomes difficult. However, since the frequency of the intermediate frequency signal is low, if the 1.57542 GHz satellite signal received by the antenna 2 is converted to this intermediate frequency by one-step frequency conversion, the filter 3 cannot sufficiently remove the image component separated by 8.184 MHz. Therefore, there is a problem in that it is necessary to increase the number of frequency conversion stages by using a special mixer for removing the image, which allows deterioration of sensitivity.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a signal processing method for a GPS receiver capable of receiving satellite signals with high sensitivity by a simple circuit without increasing power consumption. And

[0015]

In order to achieve this object, a signal processing method for a GPS receiver according to the present invention measures the phase of a spread spectrum signal from a satellite to measure the time indicated by the satellite signal. GPS receiver that seeks position by
The frequency of sampling the intermediate frequency signal is lower than the frequency of the intermediate frequency signal, and in the sampling, the frequency component of the difference generated by the interference of the intermediate frequency signal and the period twice the sampling is In the processing as the received signal,
This is a method of measuring the pseudo noise code of the satellite signal contained in this signal or the phase of the carrier wave.

By this method, the sampled signal has a period slower than the sampling frequency required to obtain a signal having the same frequency as the intermediate frequency signal before sampling, so that the sampled signal is the original signal. The signal component of the intermediate frequency of is not included. In a normal communication device, such frequency conversion is not used due to deterioration of quality such as interference between received signals.
However, a weak spread spectrum signal such as GPS is
Most of the signal components distributed in the band are signals close to white noise, and the spectrum of the GPS signal component is not so large. Therefore, the GPS signal component does not affect positioning accuracy and reception sensitivity even in such processing. . Moreover, even though the frequency of the intermediate frequency signal is high, the signal processing cycle of the logic circuit is long, and it is possible to reduce the number of frequency conversion steps by one, which does not increase power consumption and does not increase the circuit scale. Moreover, since the image signal can be easily removed, a highly sensitive and inexpensive receiver can be easily realized.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS.

(Embodiment 1) FIG. 1 shows the NAVST of the present invention.
1 is a block configuration diagram of a first embodiment showing a signal processing method of a GPS receiver using an AR satellite. In FIG. 1, blocks having the same functions as those in FIG. 4 of the conventional example are denoted by the same reference numerals, and description thereof will be omitted.

Here, 23 is a frequency-converted amplified satellite signal to an intermediate frequency signal, for example, a local oscillator that outputs a 1.559052 GHz local oscillation signal, and 24 is a frequency-converted 1
A filter for filtering an intermediate frequency signal of 6.368 MHz (= 1.57542 GHz-1.559052 GHz) (passband width is, for example, 1 to 2 MHz). The local oscillator 23, the mixer 6 and the filter 24 constitute a frequency conversion circuit. . Reference numeral 25 is two latches that sample the intermediate frequency signal binarized by the comparator 9, and 16 is a reproduced carrier wave that corrects the Doppler shift of the satellite signal and the error of the reference oscillator 22 and tracks the phase of the carrier wave. , A numerically controlled oscillator that outputs time-sequentially for each satellite. Further, the antenna 2 has a built-in amplifier for compensating for cable attenuation and obtaining low noise characteristics.

The difference between the first embodiment and the conventional example (FIG. 4) is that the logic circuit has one latch 25 for each of the I and Q signals, which is one more than the latch 10 of FIG. However, the scale of the logic circuit is reduced by eliminating the need for the local oscillator 11 and the mixer 12 for each of the I and Q signals in FIG. The clock frequency used in the logic circuit is the same as in the conventional example, and the procedure and outline of the signal processing described below are also the same.

The operation of the GPS receiver using the NAVSTAR satellite configured as described above will be described. First, the antenna 2 receives radio waves from a plurality of GPS satellites 1 (carrier frequency 1.57542 MHz). The received signal (satellite signal) is filtered by the filter 3 to remove unnecessary signals and then amplified by the amplifier 4. Further, the frequency conversion circuit composed of the 1.559052 GHz local oscillator 23, the mixer 6 and the filter 24 performs frequency conversion (1
6.368MHz = 1.57542GHz-1.559052GHz). Filter 24
Has a pass band width of 1 MHz to 2 MHz. The frequency of the output intermediate frequency signal is a signal centered on 16.368 MHz.

Next, the intermediate frequency signal is amplified and limited in amplitude by the amplifier 8, and then compared with the reference potential V by the comparator 9 to be converted into a binary logic signal. This binarized signal is output from the reference oscillator 22 in one latch 25.
Sampling with a clock signal I of 16.368 MHz. Further, in the other latch 25, 16.368 output from the reference oscillator 22.
Sampling is performed with a clock signal Q of MHz. After that, all signals are processed as discrete values in the logic circuit or the arithmetic circuit, and the clock signal output from the reference oscillator 22 is used as the system clock for the entire processing.

The clock signals I and Q output from the reference oscillator 22 are in a quadrature relationship because their timings are shifted by 1/4 of the signal period. In this sampling, the sampling period and the intermediate frequency signal interfere with each other to generate a baseband signal component. After that, the signal component in the base band is processed as a satellite signal.
The sampled satellite signals I and Q undergo independent signal processing for each satellite received. The pseudo noise generator 13 outputs a pseudo noise code unique to each satellite received. The pseudo-noise code unique to the satellite has a code rate called C / A code of 1.023 Mbps
The code length is 1023 bits and the cycle is 1 msec.

In the demodulator 14, the received signal and the pseudo noise code are mixed by the mixer 14a for each satellite. The phase of the pseudo noise code is set in the pseudo noise generator 13 as a discrete value quantized with a timing of about 61 μsec of 16.368 MHz which is a signal processing clock. After the demodulator 14 mixes the received signal and the pseudo-noise code, the filter 14b smoothes them by cumulative addition until a time width corresponding to a sampling frequency of several tens of kHz. The smoothed satellite signal is a BPSK data signal having a carrier frequency close to zero, but is a carrier corresponding to the Doppler shift and the error of the reference oscillator 22.

The numerically controlled oscillator 16 oscillates a reproduced carrier signal for each satellite and outputs orthogonal I and Q signals. Using this output, the mixer 17 performs orthogonal frequency conversion on the smoothed signal. Since the sampling period of the input signal is long, this frequency conversion is processed in a time division manner for a plurality of satellites. The switch 18 converts the in-phase I signal component and the quadrature Q signal component output from the mixer 17 into a time-sequential signal. Then, the cumulative adder composed of the adder 19 and the RAM 20 cumulatively adds the I and Q signal outputs of the mixer 17 for each satellite. The period of addition is 1 msec from the beginning to the end of the C / A code.

The control unit 21 receives the cumulative addition result of 1 msec, and controls the numerically controlled oscillator 16 so that the amplitude of the Q signal component, which is the cumulative addition result, becomes small.
Track the satellite signal carrier. Furthermore, the phase output by the pseudo noise generator 13 is moved with 1 msec as a break,
Pseudo noise of the satellite signal is tracked by checking the change in the amplitude of the I signal component, which is the cumulative addition result, and measuring the phase difference of the pseudo noise code between the pseudo noise generator 13 and the satellite signal from this change.

Further, the control unit 21 outputs I as the cumulative addition result.
Depending on the sign of the signal component, it is sent from the satellite by BPSK modulation.
Receives 50 bps data. Then, by measuring the phase of the pseudo noise code and the timing of the data of 50 bps, the time when the satellite emits the radio wave is obtained. Further control unit
At 21, using the orbit information and time information received for multiple satellites and the measured time, the antenna position of the receiver is calculated and output to the outside.

In the first embodiment, the intermediate frequency is four times higher than that of the conventional example shown in FIG. 4, and the frequency of the image signal is 32.736.
MHz (twice the intermediate frequency of 16.368 MHz) and filter 3
It is easy to set the attenuation of the image signal to 5 dB or more. Therefore, since the image signal can be removed more easily than in the conventional example of FIG. 4, a highly sensitive receiver can be realized with an equivalent circuit scale. Further, as described above, the size of the logic circuit is increased by one compared with the case of FIG. 4, but the local oscillator 11 and the mixer 12 of FIG. 4 are not necessary, and the size of the logic circuit is reduced. . Further, the clock frequency used in the logic circuit is the same, and the signal processing procedure is also the same.

As described above, according to the first embodiment, the intermediate frequency signal is set to a frequency substantially equal to the sampling frequency, and the interference between the sampling period and the intermediate frequency signal is used to obtain the received signal in the base band. An image signal can be suppressed with a small circuit scale without increasing power consumption, and a highly sensitive and inexpensive receiver can be provided.

(Embodiment 2) FIG. 2 shows the NAVST of the present invention.
It is a block block diagram of Embodiment 2 which shows the signal processing method of the GPS receiver which utilizes AR satellite. In FIG. 2, blocks having the same functions as those in FIG. 4 of the conventional example and FIG. 1 of the first embodiment are denoted by the same reference numerals and the description thereof will be omitted.

Here, 26 is a local oscillator for frequency-converting the amplified satellite signal to an intermediate frequency different from that of FIG. It is a filter with a different center frequency for filtering the intermediate frequency signal of (GHz).

The second embodiment differs from the first embodiment in that
The oscillation frequency of the local oscillator 26 is different, and the frequency of the satellite signal changes due to sampling. It should be noted that the frequency conversion for converting to the base band at the beginning of the logic circuit is provided as in the case of FIG.

The operation of the second embodiment configured as above will be described. The general operation is similar to that of the first embodiment, and only the differences will be described. In the frequency conversion circuit composed of the local oscillator 26, the mixer 6 and the filter 27, the center frequency of the intermediate frequency signal is 20.46 MHz (= 1.59588GHz-1.57542GH
Centered on z). Similarly, the filter 27 has a pass band of 20.46M.
As Hz, the pass band width is similar to 1 MHz to 2 MHz. The signal binarized by the comparator 9 is sampled by the latch 10 with the clock signal of 16.368 MHz output from the reference oscillator 22. After this, all signals are set as discrete values,
The clock signal processed by the logic circuit or the arithmetic circuit and output from the reference oscillator 22 is used as the system clock for the entire processing.

In this sampling, the sampling period is 16.368 MH
The z and the intermediate frequency signal of 20.48 MHz interfere with each other to generate an intermediate frequency signal component of 4.092 MHz different from the first embodiment.
The intermediate frequency signal component of Hz is processed as a received signal. The sampled signal is subjected to orthogonal frequency conversion in the mixer 12 by the I signal of 4.092 MHz output from the local oscillator 11 and the Q signal having a 90 ° phase difference. The orthogonal local signal 4.092MHz is
It can be easily made from the output of the reference oscillator 22 by a shift register or a counter. With respect to the satellite signals I and Q after the frequency conversion, the same processing as in the first embodiment is performed thereafter.

As described above, the center frequency of the intermediate frequency signal before sampling and the sampling period are different from those of the first embodiment, and the frequency conversion for converting the received signal into the base band after sampling is provided. Since the frequency of the intermediate frequency signal to be sampled is far from the clock frequency of the logic circuit, it is easy to remove the influence of the clock signal leaking into the intermediate frequency signal. In addition, since the increase in the number of logic circuits is small, high performance can be realized by simply shielding the analog circuit of the receiver. When the clock signal leaks into the intermediate frequency signal, it changes to a DC component in sampling and is removed by the subsequent frequency conversion and filtering.

(Embodiment 3) FIG. 3 shows the NAVST of the present invention.
It is a block block diagram of Embodiment 3 which shows the signal processing method of the GPS receiver which utilizes AR satellite. In FIG. 3, blocks having the same functions as those in FIGS. 4 and 1 and 2 of the conventional example shown in FIGS.

Here, 28 frequency-converts the satellite signal amplified by the amplifier 4 into an intermediate frequency, for example, 1.624524GH.
z is a local oscillator that outputs a local oscillation signal of z, 29 is a filter with a different center frequency that filters the frequency-converted intermediate frequency signal of 49.104 MHz (= 1.624524 GHz-1.57542 GHz), and 30 is a 6
Latch sampling at 5.472MHz, 31 is a local oscillator that outputs a local oscillation signal of 16.368MHz for frequency conversion of interference signal of approximately 16.368MHz obtained by sampling to baseband, 4
0 is a mixer that mixes the output of the latch 30 and the output of the local oscillator 31 (16.368 MHz) with the clock at 65.472 MHz, and 32 is 65.
A filter that adds four outputs of the mixer 40 input at a clock of 472MHz and converts it to a signal sampled at 16.368MHz. 33 is a quadrupler, which is a clock (1
6.368MHz) is multiplied by 4 and used as a sampling clock and a clock for the local oscillator 31.

The operation of the third embodiment having the above configuration will be described. The general operation is similar to that of the second embodiment, and only the differences will be described. The center frequency of the intermediate frequency signal output from the mixer 6 is 49.104MHz (= 1.624524GHz-1.57542GH
z) and the filter 29 similarly have a pass band of 49.104 MHz, but have a bandwidth of 1 MHz to 2 MHz, which is the same as in FIG. 2 of the second embodiment. The signal after being binarized by the comparator 9 has the output of the reference oscillator 22 multiplied by 4 in the latch 30 in the latch 30.
Sampling with a clock signal of 65.472MHz. In this sampling, the intermediate frequency signals having sampling periods of 65.472 MHz and 49.104 MHz interfere with each other to generate an intermediate frequency signal component of 16.368 MHz different from that of FIG. 2 of the second embodiment. This intermediate frequency signal component is processed as the next intermediate frequency signal.

The local oscillator 31 outputs the sampled signal.
The mixer 40 converts the quadrature frequency by the I signal of 16.368 MHz and the Q signal having a 90 ° phase difference. The quadrature local oscillation signal of 16.368MHz can be easily generated from a clock signal of 65.472MHz by a shift register or a counter. The frequency-converted satellite signals I and Q become base-band received signals sampled by the filter 32 at the system clock of 16.368 MHz, and the subsequent processing is as shown in FIG.
Is the same as The quadrupler 33 can be realized by a PLL circuit or the like built in the semiconductor LSI, and the circuit scale and power consumption are small.

As described above, the frequency of the intermediate frequency signal to be sampled and the frequency to be sampled are higher than those of the second embodiment, and it is possible to provide a high-sensitivity GPS receiver which is less influenced by the image signal. Also, at the beginning of the logic circuit, the sampling period is lengthened, and since it is a small-scale circuit increase shared by all satellites that receive,
Since high-speed logic signals can be processed only inside the logic circuit, and the number of high-speed operations is small, the increase in power consumption is not so large. Nevertheless, the intermediate frequency can be very high. Also,
Compared to performing two-stage frequency conversion with an analog circuit,
Although the circuit scale and power consumption are small, the image signal can be further suppressed as compared with the second embodiment, and a highly sensitive receiver can be provided.

The above description of the first to third embodiments is N.
Although the signal processing method of the GPS receiver using the AVSTAR satellite has been described, the GPS receiver can be used for other GPS receivers such as GLONASS satellite that measure the time of the satellite signal by the phase of the spread spectrum signal and determine the position. it can. Further, it can be applied to a simple communication device in which interference between signal components of a received signal does not pose a problem. Although one type of satellite signal demodulation circuit and other configurations have been described, the present invention is not limited to this.

[0042]

As described above, according to the present invention, the frequency of the intermediate frequency signal input in sampling is set to a frequency higher than the Nyquist frequency corresponding to half the sampling frequency, and the intermediate frequency generated in sampling is set. By the method of making the interference component with the received signal in the subsequent processing,
It is possible to provide a high-sensitivity signal processing method for a GPS receiver which is less affected by an image signal without increasing power consumption or circuit scale.

[Brief description of the drawings]

FIG. 1 is a GPS using the NAVSTAR satellite of the present invention.
1 is a block configuration diagram of a first embodiment showing a signal processing method of a receiver.

FIG. 2 is a GPS utilizing the NAVSTAR satellite of the present invention.
It is a block block diagram of Embodiment 2 which shows the signal processing method of a receiver.

FIG. 3 is a GPS utilizing the NAVSTAR satellite of the present invention.
It is a block block diagram of Embodiment 3 which shows the signal processing method of a receiver.

FIG. 4 is a block configuration diagram showing a signal processing method of a GPS receiver using a conventional NAVSTAR satellite.

[Explanation of symbols]

1 ... GPS satellite, 2 ... Antenna, 3, 24, 27, 29,
32 ... Filter, 4, 8 ... Amplifier, 6, 12, 17, 40 ...
Mixer, 9 ... Comparator, 10, 25, 30 ... Latch, 11, 2
3, 26, 28, 31 ... Local oscillator, 13 ... Pseudo noise generator,
14 ... Demodulator, 15, 18 ... Switch, 16 ... Numerically controlled oscillator, 19 ... Adder, 20 ... RAM, 21 ... Control section, 22
… Reference oscillator, 33… Quadrupler.

Claims (3)

[Claims] 1. In a GPS receiver for measuring the phase of a spread spectrum signal from a satellite and measuring the time indicated by the satellite signal to obtain the position, the frequency at which the intermediate frequency signal is sampled is 2 of the intermediate frequency signal. A frequency lower than double the frequency, and in sampling, the frequency component of the difference caused by the interference of the intermediate frequency signal and the sampling period is used as a received signal in the subsequent processing, and the pseudo satellite signal contained in this signal is simulated. A signal processing method for a GPS receiver, which comprises measuring the phase of a noise code or a carrier wave. 2. The intermediate frequency signal generated in the sampling and the interference signal component of the sampling period are set so that the center frequency of the satellite signal becomes a frequency exceeding half the bandwidth of the satellite signal, and the sampling is performed. The GPS according to claim 1, wherein the signal is frequency-converted by a local oscillation signal.
Signal processing method of receiver. 3. A clock signal input to a logic circuit is multiplied by a multiplier, an intermediate frequency is sampled by an analog-digital converter by the multiplied signal, and the sampled signal is frequency-converted by a local oscillation signal, This conversion output is subjected to cumulative addition to increase the sampling period, and the interference signal of the intermediate frequency signal and the sampling period is converted to a slow sampling signal having a sampling period of twice or more by cumulative addition, and then this signal is included. 2. The G according to claim 1, wherein the pseudo-noise code of the satellite signal being transmitted or the phase of the carrier is measured.
Signal processing method of PS receiver.