JPH09115926A - Field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field effect transistor which has a simple constitution, uses a compound semiconductor and can improve a strain specification of a high frequency amplifier circuit. SOLUTION: A heavily doped source layer 3 and a heavily doped drain 4 are formed within an operating layer 2 made of N region. A gate 11 having a Schottky contact with the operating layer 2, a source electrode 12 and a drain electrode 13 which have ohmic contact with the heavily doped source layer 3 and the heavily doped drain layer 4 respectively are formed. Section forms of the source electrode and drain electrode in two regions at least of the regions along to the lateral direction of the gate electrode 11 are different from each other. For example distances between the heavily doped source layer 3 and the gate electrode 11 in the two regions are different and source resistances are different. A gm-Vgs characteristic of the field effect transistor is made flat because of two gm-Vgs characteristics with different peak positions each other being composed, and its strain is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a compound semiconductor, particularly a field effect transistor (MESFET: MEtal Semiconductor) using a compound semiconductor such as GaAs.
ductor Field Effect Transistor).

[0002]

2. Description of the Related Art Conventionally, a field effect transistor using a compound semiconductor such as GaAs has an excellent amplifying action and an oscillating action in a super high frequency range from microwaves to millimeter waves. Widely applied in the field dealing with. Recently, the market is expected to expand further in the future due to the spread of satellite broadcasting and mobile phones.

By the way, as a field effect transistor using such a compound semiconductor, a field effect transistor having a single gate electrode and a multi-finger field effect transistor in which a plurality of unit field effect transistors are connected in parallel are widely used. It is used. FIG. 7 (a)
(C) is a top view which shows the basic structure of the conventional field effect transistor.

The field effect transistor shown in FIG. 7 (a) has a single gate structure. Two high-concentration source layers 3 and a high-concentration drain layer 4 are formed in the operating layer 2 which is an N-type region, and further, the gate electrode 11 in Schottky contact with the operating layer 2, the high-concentration source layer 3 and A source electrode 12 and a drain electrode 13 that are in ohmic contact with the high-concentration drain layer 4 are formed.

The field effect transistor shown in FIG. 7B is a unit T-type gate field effect transistor which is frequently used in millimeter waves and the like. 2 branching into T-shape and extending into the operation layer 2
A gate electrode 11 having two gate portions 11a and 11b is formed, and source electrodes 12a and 12b and a drain electrode 13 are formed on both sides of each gate portion 11a and 11b.

The field effect transistor shown in FIG. 7 (c) is a multi-finger type field effect transistor in which four unit field effect transistors having the same structure as the field effect transistor shown in FIG. 7 (a) are connected in parallel. is there. That is, the operating layer 2 has a gate electrode 11 composed of four gate portions 11a to 11d extending in parallel to each other, and the four gate portions 11a to 11d are sandwiched therebetween.
Three high-concentration source layers 3a to 3c and source electrode 12a
12c, two high-concentration drain layers 4a and 4b, and drain electrodes 13a and 13b.

The characteristics of each of these field effect transistors are long and short, and an optimum structure is selected according to the application.

[0008]

However, in the conventional high frequency amplifier circuit using the field effect transistor, there is a problem that a distortion component which is not present in the input high frequency signal appears in the output signal due to the non-linearity of the transfer function. is there.
These distortions are mainly caused by the non-linearity of the change rate of the drain current Ids of the field-grounded transistor whose source is grounded with respect to the gate-source voltage Vgs, that is, the mutual conductance gm. In high-frequency operation, the gate
The nonlinearity of the rate of change of the source-to-source capacitance Cgs with respect to the gate-source voltage Vgs is also important. The non-linearity of the mutual conductance gm will be described below.

FIGS. 8A and 8B are views showing the amplifying action of the conventional field effect transistor. 8A shows the relationship between the gate-source voltage Vgs and the drain current Ids of the conventional field effect transistor, and FIG. 8B shows the dependency of the transconductance gm of the conventional field effect transistor on the gate-source voltage Vgs. Show. As shown in FIGS. 8A and 8B, a change ΔIds in the drain current Ids occurs with respect to a change ΔVgs in the gate-source voltage Vgs (input signal), so that the transistor exhibits an amplifying action. However,
As shown in FIG. 8A, in reality, the drain current Ids does not exhibit a linear change characteristic, and for example, the gate-source voltage V
The drain voltage Vds is saturated when gs increases. Therefore, the dependency of the transconductance gm shown in FIG. 8B on the gate-source voltage Vgs may not be constant, and may have a peak at a certain point.

Thus, the mutual conductance gm (g
If m = ΔIds / ΔVgs) is non-linear, a distortion component that is not included in the input signal occurs at the output. This distortion includes harmonic components equivalent to n times the frequency of the input signal,
It includes intermodulation distortion and the like that occurs when two or more types of frequency components interfere with each other. These distortion components mainly occur due to the non-linearity of the amplification characteristic of the amplification element as described above, and the magnitude thereof is determined by the transfer function of the amplification element.

Since the distortion of the high frequency signal caused by the non-linearity as described above causes the radio interference in the radio equipment, it is desirable to reduce it as much as possible. In particular, in an amplifier which is equipped with a field effect transistor using a compound semiconductor and amplifies a large number of carriers (carrier waves) at a high frequency at the same time, this distortion (mainly second-order and third-order distortion) overlaps with an adjacent carrier and interferes with each other. May occur. Therefore, in such an amplifier, a distortion component is reduced by using a special circuit such as a distortion compensation circuit. Although it is possible in principle to construct a high-frequency amplifier using various proposed field-effect transistors with extremely good distortion characteristics, these field-effect transistors are special and expensive, and are extremely expensive. When distortion characteristics are required. There are no longer field effect transistors that meet these requirements. Therefore,
The current situation is to deal with it by providing a distortion compensation circuit.

The present invention has been made in view of the above problems, and an object thereof is to obtain a gate-source voltage value which gives a peak of mutual conductance of a field effect transistor using a compound semiconductor as described above.・ By focusing on the point that it changes depending on the cross-sectional shape between the sources, by taking measures that can eliminate the nonlinearity of the transfer function of a field effect transistor using a compound semiconductor with a simple configuration as much as possible, low distortion is achieved. It is to provide a field effect transistor.

[0013]

Means for Solving the Problems In order to achieve the above object, the means taken by the present invention is to provide a source electrode / drain electrode between at least two regions in the entire region along the gate width direction of various field effect transistors. The flatness of the gm-Vgs characteristic curve can be realized by changing the cross-sectional shape of.

Specifically, the field effect transistor of the present invention is, as described in claim 1, a semi-insulating substrate, an operating layer formed on a part of the semi-insulating substrate, and the operating layer. A high-concentration layer formed on a part of the gate electrode, a gate electrode that is in Schottky contact with the operating layer, and a source electrode and a drain that are formed to face each other with the gate electrode sandwiched therebetween and that make ohmic contact with the high-concentration layer And at least an electrode. Two cross-sectional shapes between the source electrode and the drain electrode in at least two regions of the entire region along the width direction of the gate electrode are different from each other, and two regions obtained from the transistor structure of the two regions are formed. gm-Vgs (gm is transconductance, V
The gs has different peak positions on the gate-source voltage curve.

With the above configuration, the gm-Vgs characteristic curve of the field effect transistor has two gs having different peak positions.
The m-Vgs characteristic curve is synthesized into a flattened shape. Therefore, the occurrence of signal distortion due to the non-linearity of the transfer function is suppressed. Moreover, such a structure of the field effect transistor can be realized without drastically changing the process or using an expensive material such as an epitaxial wafer. Therefore, the linearity of the mutual conductance gm of the field effect transistor can be improved with a simple structure,
The distortion characteristic of the conventional field effect transistor is remarkably improved.

According to a second aspect of the field effect transistor of the first aspect, the cross-sectional shape between the source electrode and the drain electrode is formed in at least a part of the entire region along the width direction of the gate electrode. The gate electrode may be formed so as to continuously change in the width direction.

With this configuration, the gm-Vgs characteristic curve is flattened more, and the field effect transistor has a transfer function with particularly good linearity.

As described in claim 3, in the field-effect transistor according to claim 1 or 2, the cross-sectional shape between the source electrode and the drain electrode in the at least two regions is obtained by a transistor structure in each region. It is preferable that the region between the maximum value and the minimum value of the peak positions in at least two gm-Vgs curves to be included includes the working voltage region of the field effect transistor.

With this configuration, it is possible to reliably reduce the occurrence of signal distortion in the actually used area.

As described in claim 4, a semi-insulating substrate, an operating layer formed on a part of the semi-insulating substrate,
A high-concentration layer formed on a part of the operating layer, a plurality of gate electrodes that are in Schottky contact with the operating layer, and ohmic-contact with the high-concentration layer formed so as to face each other with the gate electrode interposed therebetween. In a multi-finger type field effect transistor including a unit field effect transistor including a source electrode and a drain electrode, at least two field effect transistors among the above unit field effect transistors are configured to have different gm-Vgs characteristics.

With this configuration, the gm-Vgs characteristic of the entire field effect transistor is flattened, and the same effect as in claim 1 is obtained.

According to a fifth aspect of the present invention, in the field effect transistor according to the fourth aspect, the at least two unit field effect transistors are configured so that cross-sectional shapes between the source electrode and the drain electrode are different from each other. You can

With this configuration, the gm-Vgs characteristics of each unit field effect transistor are different from each other, so that the operation of the above-mentioned claim 4 can be reliably obtained.

According to a sixth aspect of the present invention, in the field effect transistor according to the fourth aspect, at least one unit field effect transistor among the respective field effect transistors is provided in the entire region along the width direction of the gate electrode. home,
The cross-sectional shape between the source electrode and the drain electrode may be configured to change continuously at least in a part along the width direction of the gate electrode.

With this configuration, the same effect as that of the second aspect can be obtained.

As described in claim 7, in the field effect transistor according to claim 4 or 5, between the source electrode and the drain electrode in the entire region along the width direction of the gate electrode of each unit field transistor. The cross-sectional shape is
At least two gm-V obtained by the transistor structure of each region in all unit field effect transistors
It is preferable to form the region between the maximum value and the minimum value of the peak position in the gs curve so as to include the working voltage region of the field effect transistor.

With this configuration, the same operation as that of the third aspect can be obtained.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) First, a first embodiment will be described. FIG. 1 is a plan view of a field effect transistor (MESFET) according to the first embodiment. FIG.
1 (a) and 2 (b) are enlarged cross-sectional views taken along line IIa-IIa and line IIb-IIb shown in FIG. 1, respectively. The relationship between each code and the member name is as follows. 1 is a semi-insulating GaAs substrate, 2 is an operating layer (channel layer) formed of a low concentration N-type region selectively formed by ion implantation of impurities, 3 is a high concentration source layer, 4 is a high concentration drain layer, 1
1 is a gate electrode which is in Schottky contact with the operating layer 2;
Reference numeral 12 denotes a source electrode in ohmic contact with the high-concentration source layer 3, and 13 denotes a drain electrode in ohmic contact with the high-concentration drain layer 4.

Here, as a feature of the diameter value of the present embodiment, the distance between the source and gate electrodes of the field effect transistor is as shown in FIG.
The portion indicated by the IIa-IIa line in Fig. 1 differs from the portion indicated by the IIb-IIb line in Fig. 1. That is, IIa-IIa in FIG.
The distance between the high-concentration source layer 3 and the gate electrode 11 on the line (hereinafter referred to as the source-gate electrode distance) is wider than the source-gate electrode distance on the line IIb-IIb in FIG. . In other words, FIG. 2 (a),
As shown in (b), the cross-sectional shape between the source electrode and the drain electrode taken along line IIa-IIa in FIG. 1 and IIb-II in FIG.
The cross-sectional shape between the source electrode and drain electrode on line b is different. In these two regions, the source resistance of the transistor structure in each region is different due to such a difference in sectional shape (source-gate electrode distance). In other words, it has a structure in which two field effect transistors having different operating points are connected in parallel.

3 (a) and 3 (b) are dependence curves of the transconductance gm obtained from the shape of the transistor in the portions shown in FIGS. 2 (a) and 2 (b) on the gate-source voltage Vgs. (Hereinafter, gm-Vgs
Curve). That is, in the field effect transistor having a large source-gate electrode distance shown in FIG. 2A, the gate-source voltage Vgs becomes negative at the peak position of the gm-Vgs curve as shown in FIG. 3A. In the area. On the other hand, in the field effect transistor having a small source-gate electrode distance shown in FIG. 2B, the gate-source voltage Vgs is 0 at the peak position of the gm-Vgs curve as shown in FIG. 3B. Close to Then, as shown in FIG.
A gm-Vgs characteristic having a substantially flat portion shown by a curve obtained by combining the gm-Vgs curves shown in (a) and (b) is obtained. In other words, the field effect transistor has a gate electrode that exhibits gm-Vgs characteristics with different peak positions.
By providing at least two regions having the shape between the source electrodes, the transconductance gm is flattened in the region between the two peaks before the synthesis in the synthesized gm-Vgs curve. When the field effect transistor is used in this flattened region, the mutual conductance gm becomes almost constant. Therefore, the distortion of the high frequency signal can be remarkably reduced, and the field effect transistor having a very small distortion can be formed with a simple structure.

In this case, the ratio of each of the two types of field effect transistors having different source-gate electrode distances to the total gate width is set to, for example, the ratio at which the second-order or third-order distortion is minimized by actually performing high-frequency measurement. can do.

In this embodiment, two regions having different cross-sectional shapes between the source electrode and the drain electrode are provided in the region along the width direction of the gate electrode 11.
The present invention is not limited to such an embodiment, and the cross-sectional shapes between the source electrode and the drain electrode are different from each other.
More than one area may be provided.

In this embodiment, the high concentration source layer 3
The two regions having different distances between the gate electrode 11 and the gate electrode 11 are provided. However, depending on the structures of the high-concentration source layer and the source electrode, only the two regions having different distances between the source electrode and the gate electrode are provided. However, the effect of the present invention can be exhibited.

(Second Embodiment) Next, a second embodiment will be described. 4A and 4B are cross-sectional views of two different regions in a region along the gate width direction of the field effect transistor according to the second embodiment. As shown in FIGS. 4A and 4B, on the semi-insulating GaAs substrate 1, a buffer layer 5 made of non-doped GaAs,
Operation layer 2 made of N-type GaAs layer on buffer layer 5
And the high-concentration source layer 3 and the high-concentration drain layer 4 made of N + GaAs on the operating layer 2 are sequentially formed by the epitaxial growth method. A gate electrode 11, a source electrode 12, and a drain electrode 13 are formed on the operating layer 2, the high-concentration source layer 3, and the high-concentration drain layer 4, respectively. In the present embodiment, the distance between the gate electrode 11 and the source electrode 12 is different between the area shown in FIG. 4A and the area shown in FIG. 4B.

In the field effect transistor according to this embodiment, two regions having different distances between the gate electrode 11 and the source electrode 12 are provided. Therefore,
In the transistor structure in the two regions, the source resistances are different and two field effect transistors having different operating points are connected in parallel, so that the same effect as the first embodiment can be exhibited.

(Third Embodiment) Next, a third embodiment will be described. FIG. 5 is a plan view of the field effect transistor according to the third embodiment. Also in this embodiment, each element constituting the field effect transistor has the first
The embodiment is the same as that of Embodiment 1, and the same reference numerals as those in FIG.

In this embodiment, the source-gate electrode distance, that is, the source resistance is continuously changed along the gate width direction. Therefore, the peak position of the gm-Vgs characteristic curve changes continuously in each part along the gate width direction, so that the gm-Vgs characteristic curve of the field effect transistor as a whole is flattened, and The distortion will be reduced.

Also in this embodiment, the first and
Similar to the second embodiment, the source-gate electrode distance is set to a ratio at which the second-order or third-order distortion is minimized by actually performing high-frequency measurement, for example.

(Fourth Embodiment) FIG. 6 is a plan view of a multi-finger type field effect transistor according to the fourth embodiment. The field-effect transistor according to the present embodiment has a gate electrode 11 composed of four gate portions 11a to 11d extending in parallel in the operating layer 2, and three high electrodes so as to sandwich each gate portion 11a to 11d. Concentration source layers 3a to 3c and source electrodes 12a to 12c and two high concentration drain layers 4a and 4b and drain electrodes 13a and 1a.
3b. That is, it has a structure in which four unit electric field transistors are connected in parallel.

In the present embodiment, the source resistances of the two unit transistors at both ends are higher than those of the two unit field effect transistors on the inner side, and the operating points in the field effect transistors are different as a whole. There will be two types of unit field effect transistors. Therefore, the signal distortion of the field effect transistor can be reduced by the same operation as that of the first and second embodiments.

The ratio of each of the two types of field effect transistors to the total gate width is set to, for example, a ratio at which the second-order or third-order distortion is minimized by actually performing high-frequency measurement.

Next, the difference in operation between the conventional field effect transistor and the field effect transistor of the present invention will be described.

In the conventional field effect transistor, as shown in FIG. 8 described above, the mutual conductance gm (gm = ΔId
Since s / ΔVgs) is non-linear, a distortion component not included in the input signal occurs in the output signal. This distortion includes harmonic components equivalent to n times the frequency of the input signal,
It includes intermodulation distortion and the like that occurs when two or more types of frequency components interfere with each other. Therefore, when a field effect transistor is mounted on a tuner for CATV, for example, when amplifying signals of multiple channels (40 to 50 channels) transmitted from a broadcasting station, as shown in FIG.
For example, when there are two carriers, third-order intermodulation distortion (2f1-f2, 2f2-f1) occurs between channel 1 (frequency f1) and channel 2 (frequency f2).
When this frequency overlaps with the frequency f3 of channel 3, for example, interference occurs between radio waves.

On the other hand, when a field effect transistor having a change characteristic in which the apparent transconductance gm is flatter with respect to the gate-source voltage Vgs, that is, a linear transfer function is used as in the present invention, the quadratic is mainly used. Alternatively, since the secondary distortion component is extremely small, such interference does not occur and an extremely clear image can be obtained.

[0045]

According to the present invention, the field effect transistor is provided with regions having different cross-sectional shapes between the source electrode and the drain electrode, and the peak position in the gm-Vgs curve obtained from the transistor structure in each region. However, the strain characteristics of the field effect transistor can be remarkably improved without drastically changing the process or using an expensive material such as an epitaxial wafer.

According to the fourth to seventh aspects, the field effect transistor formed of a plurality of unit field transistors is provided with regions having different cross-sectional shapes between the source electrode and the drain electrode, and is obtained from the transistor structure of each region. gm-
Since the peak positions on the Vgs curve are made different,
The same effects as those of claims 1 to 3 can be exhibited.

[Brief description of the drawings]

FIG. 1 is a plan view of a field effect transistor according to a first embodiment.

FIG. 2 is a sectional view taken along line IIa-IIa and line IIb-IIb in FIG.

FIG. 3 is a gm-Vgs characteristic curve in two regions of the field effect transistor according to the first embodiment and a gm-Vgs characteristic curve obtained by combining the two.

FIG. 4 is a cross-sectional view in two regions of the field effect transistor according to the second embodiment.

FIG. 5 is a plan view of a field effect transistor according to a third embodiment.

FIG. 6 is a plan view of a multi-finger type field effect transistor according to a fourth embodiment.

FIG. 7 is a plan view of a conventional single gate type, T type, multi-finger type field effect transistor.

FIG. 8 is a diagram showing the dependence of the conventional drain current Ids and transconductance gm on the gate-source voltage Vgs.

FIG. 9 is a diagram for explaining a signal amplified by a high-frequency amplifier equipped with field effect transistors of the present invention and the related art.

[Explanation of symbols]

 1 semi-insulating GaAs substrate 2 working layer 3 high concentration source layer 4 high concentration drain layer 11 gate electrode 12 source electrode 13 drain electrode

Claims (7)

[Claims] 1. A semi-insulating substrate, an operating layer formed on a part of the semi-insulating substrate, a high-concentration layer formed on a part of the operating layer, and a Schottky contact with the operating layer. A gate electrode and at least a source electrode and a drain electrode that are formed to face each other with the gate electrode sandwiched therebetween and are in ohmic contact with the high-concentration layer, and at least among all regions along the width direction of the gate electrode. Two gm-Vgs obtained by the transistor structure of the two regions, which are configured so that the cross-sectional shapes between the source electrode and the drain electrode in the two regions are different from each other.
(Gm is transconductance, Vgs is gate-source voltage) A field effect transistor characterized by different peak positions in a curve. 2. The field effect transistor according to claim 1, wherein the cross-sectional shape between the source electrode and the drain electrode is at least part of the entire region along the width direction of the gate electrode in the width direction of the gate electrode. A field-effect transistor, characterized in that it is formed so as to continuously change along it. 3. The field effect transistor according to claim 1, wherein the cross-sectional shape between the source electrode and the drain electrode in the at least two regions is at least two gm-Vgs obtained by the transistor structure in each region. A field effect transistor, wherein a region between a maximum value and a minimum value of a peak position on a curve is configured to include a working voltage region of the field effect transistor. 4. A semi-insulating substrate, an operating layer formed on a part of the semi-insulating substrate, a high-concentration layer formed on a part of the operating layer, and a Schottky contact with the operating layer. Multiple gate electrodes,
And a multi-finger type field effect transistor including a unit field effect transistor formed of a source electrode and a drain electrode which are formed so as to face each other with the gate electrode interposed therebetween and are in ohmic contact with the high-concentration layer. At least two field effect transistors have different gm-Vgs characteristics from each other. 5. The field effect transistor according to claim 4, wherein the at least two unit field effect transistors have different cross-sectional shapes between a source electrode and a drain electrode. 6. The field-effect transistor according to claim 4, wherein at least one unit field-effect transistor among the field-effect transistors is at least part of the entire region along the width direction of the gate electrode. A field effect transistor, wherein a cross-sectional shape between a source electrode and a drain electrode is configured to continuously change along the width direction of the gate electrode. 7. The field effect transistor according to claim 4 or 5, wherein the cross-sectional shape between the source electrode and the drain electrode in the entire region along the width direction of the gate electrode of each unit field transistor has all units. At least 2 obtained by the transistor structure of each region in the field effect transistor
A field effect transistor, wherein a region between a maximum value and a minimum value of a peak position in one gm-Vgs curve is formed so as to include a working voltage region of the field effect transistor.