JPH09114875A - Layout design method and timing verification method of semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prepare a layout with excellent characteristic with a few kinds of cells by the both of a CMOS logic and a path transistor logic, to prepare the layout with stable characteristic in the case of the path transistor logic circuit, in particular, and to secure superiority of saving area, low power consumption and high speed operation, etc. SOLUTION: At first, an imparted logical circuit is separated into a combination circuit part and a register part in a processing 102. In a processing 104, each partial circuit with strong connectivity composing the combination circuit part separated in a processing 104 is converted into the circuit of a transistor level. Next, the layout cell of the partial circuit of the transistor level is generated in a processing 106. Subsequently, the layout cell corresponding to each register included in the register part and the layout cell for every partial circuit in the combination circuit part are defined as each unit cell, an arrangement wiring is performed in a processing 109 and the layout of a block is prepared.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout designing method by automatic cell-based layout and wiring of a semiconductor integrated circuit,
The present invention also relates to an improved timing verification method for a designed semiconductor integrated circuit, and more particularly to a layout design method and a timing verification method suitable not only for CMOS logic but also for circuits using pass transistor logic.

[0002]

2. Description of the Related Art Conventionally, a cell-based layout method has been used as a layout design method and timing verification method for semiconductor integrated circuits. This cell-based method includes methods called gate array and standard cell. For these methods, prepare a high-density layout manually created for each cell in advance,
This is a method of creating a block layout of a desired logic circuit by defining connections between these cells and performing layout and wiring at the cell level according to the connections.

Further, regarding the timing verification method for the layout created on the basis of the cell, the delay value for each cell is obtained in advance by a circuit simulator or the like, and these delay values are assigned to individual logic gates for timing. I was verifying. Regarding the above design method and verification method, for example, refer to Document 1: “Design of CMOS VLSI”
(Published by Takuo Kanno, edited by Tetsuya Iizuka, published by Baifukan) Chapter 7 Various design methods, Chapter 8 CAD tools, etc.

In the conventional cell-based design method as described above, cells based on CMOS circuits are often used. This is because in a CMOS circuit, the input signal of the cell is MO
Since it is given only to the gate terminal of the S-transistor and this gate terminal is separated from the source terminal and the drain terminal in terms of current, it is easy to handle the electrical characteristics independently on a cell-by-cell basis. This is because the electrical characteristics can be maintained even when handled in cell units.

By the way, in recent years, not a complete CMOS circuit, but a pass transistor logic circuit for applying an input signal to not only the gate terminal of a MOS transistor but also the drain terminal to perform a logical operation is used. The pass transistor logic circuit may be superior to the complete CMOS circuit in terms of area saving, low power consumption, high speed, and the like. Regarding these, Reference 2: K.Ya
no, et al., "A 2.8-ns CMOS 16 x 16-b Multiplier Using C
omplementary Pass-Transistor Logic "(IEEE J
ournal of Solid-State Circuits, Vol. 25, No.2, pp.
388-395, April 1990), and Reference 3: A. Parameswa.
r, et al., "A High Speed, Low Power, Swing Restor
ed Pass-Transistor Logic Based Multiply and
Accumulate Circuit for Multimedia Applications "
(Proceeding of IEEE 1994 Custom Integrated Ci
rcuits Conference, pp.278-281) and the like.

The layout design method of the pass transistor logic circuit is described in Reference 4: K. Yano, et al., "L.
ean Integration: Achieving a Quantum Leap inPerfor
mance and Cost of Logic LSIs "(Proceeding of IEEE 1
994 CustomIntegrated Circuits Conference, pp.603-6
06) (JP-A-7-130856) and the like. The design method proposed in this document 4 is a method using a conventional cell-based layout design method. Specifically, three types of cells of a pass transistor logic circuit having a plurality of input pins are prepared, By changing the assignment (signal application form) of each input pin in the cell of each pass transistor logic circuit, many logics are generated in the cell of each pass transistor logic circuit, and the logics of many logic circuits are given. Is assigned to these cells and these cells are placed and routed by a conventional automatic placement and routing tool to obtain a block layout.

[0007]

However, in the layout designing method of the logic circuit using the pass transistor logic, a plurality of types of unit cells, each having a small number of transistors as one cell, are used. Although various types of logic can be created by combining them and the degree of freedom of logic types can be improved, the number of unit cell types is limited to multiple types (three types), so that the circuit drive capacity and area at the time of layout completion are appropriate. In some cases, the circuit characteristics may become unstable and the advantages of the pass transistor logic such as area saving, low power consumption and high speed may be impaired.

Therefore, it is conceivable to make a large number of transistors into one cell in order to stabilize the circuit characteristics and secure the superiority of the pass transistor logic. In this case, however, the degree of freedom in logic type is high. In order to do so, the disadvantage arises that a large number of cell types must be prepared in advance. Incidentally, the disadvantage that preparation of many kinds of cells is required is not limited to the logic circuit using the pass transistor logic, and the same applies to the logic circuit using the complete CMOS circuit. That is, even in the cell-based layout design of the logic circuit using the complete CMOS circuit, unless many kinds of cells are prepared with respect to the driving capability and the logic type,
Cannot create an optimal layout.

Further, in the logic circuit using the pass transistor logic, when the load capacitance in the circuit changes due to the state of the cell of its own, the delay characteristic of the circuit changes, and the source terminal and the drain terminal of the transistor respectively receive signals. When connected to a plurality of other cells via a path, the delay characteristics of the circuit change depending on the states of the other plurality of cells. Therefore, in the logic circuit using the pass transistor logic, when verifying whether the desired timing characteristics are satisfied for the created block layout,
Even if the delay characteristics of each cell were given to the conventional gate-level logic timing verification circuit for verification, correct timing verification could not be performed. On the other hand, when verifying the entire created layout by circuit simulation, a very large amount of calculation time and storage area are required, which is not realistic.

The present invention has been made in view of the above points, and a first object thereof is to obtain an optimum delay with respect to not only CMOS logic but also pass transistor logic logic circuits with a small number of cell types. Providing a layout design method that can realize a layout having characteristics, especially for a logic circuit of pass transistor logic, the layout characteristics are stable, and a layout layout method that can secure the advantages of area saving, low power consumption, and high speed To provide a method.

A second object of the present invention is to provide a gate-level timing verification method capable of processing the created layout of the pass transistor logic circuit with high accuracy, precision and speed. It is in.

[0012]

In order to achieve the above object, in the present invention, a combinational circuit portion which constitutes a semiconductor integrated circuit is divided into a plurality of circuit portions which are connected to a signal path and have a high degree of connection. The first object is achieved by generating a layout for each circuit portion and generating a block layout of a logic circuit using each layout as a unit cell.

Further, according to the present invention, a plurality of types of subcells having a smaller number of transistors than the cells of the pass transistor logic circuit described in the above-mentioned prior art document 4, for example, are prepared, and these subcells are combined to form a pass cell. By providing a cell of a transistor logic circuit or the like, an appropriate layout is designed with a smaller number of types of cells to achieve the first object.

Further, according to the present invention, the delay characteristic is obtained for each of a plurality of circuit portions of the combinational circuit portion which are connected with signal paths and have a high degree of connection, so that an appropriate delay characteristic can be obtained even in a pass transistor logic circuit. To achieve the second object.

In addition, in the present invention, in the pass transistor logic circuit, in view of the fact that the delay characteristic changes, the minimum delay value and the maximum delay value are obtained, and the minimum delay value and the maximum delay value are given and used. The second timing objective is achieved by examining the timing condition.

That is, the semiconductor integrated circuit layout designing method according to the first aspect of the present invention includes a circuit separation process for separating a given logic circuit into a combinational circuit section and a register section, and in the separated combinational circuit section. Grasping a partial circuit in which the signal paths are connected to each other when the signal path connected to the output of the separated register section is excluded, and converting this partial circuit into a transistor-level circuit for each partial circuit. Transistor circuit conversion processing, partial circuit layout generation processing for generating layout cells of individual partial circuits for each converted transistor-level partial circuit, and individual layout generated for each partial circuit of the combinational circuit unit The cells and the individual registers included in the separated register section are used as unit cells, and the cell-based layout is arranged. And performs a wire, and performing a layout wiring processing for creating a block layout of the given logic circuit.

According to a second aspect of the present invention, there is provided a layout design method for a semiconductor integrated circuit, wherein a layout of a plurality of subcells composed of at least one transistor is prepared in advance as a subcell library, and the plurality of subcells are prepared. Main cell generation processing for creating a new cell layout by arranging and wiring some of the sub cells adjacent to each other and registering the created new cell layout in the main cell library as a main cell; A layout and wiring process is performed for arranging and wiring a cell-based layout using the cell library and the main cell library as a cell library to create a block layout of a given logic circuit.

Further, the invention according to claim 3 is the layout design method for a semiconductor integrated circuit according to claim 2, wherein the sub-cell library comprises two transistors of the same polarity having source terminals coupled to each other. It is characterized by including subcells.

According to a fourth aspect of the present invention, in the layout design method for a semiconductor integrated circuit according to the first aspect, at least one partial circuit layout generation process is performed in advance.
Prepare a layout of a plurality of sub-cells composed of more than one transistor as a sub-cell library, and place and wire some of the plurality of sub-cells adjacent to each other to create a new cell layout, The main cell generation process of registering the created new cell layout in the main cell library as the main cell, and the placement and wiring of the cell-based layout using the sub cell library and the main cell library as the cell libraries are performed. It is characterized in that layout layout and wiring processing is performed for generating layout cells of individual partial circuits for each converted transistor-level partial circuit.

In addition, the invention according to claim 5 is the layout design method for a semiconductor integrated circuit according to claim 4, wherein the sub-cell library includes two transistors of the same polarity whose source terminals are coupled to each other. It is characterized in that it includes a plurality of sub-cells configured.

According to a sixth aspect of the present invention, there is provided a semiconductor integrated circuit timing verification method comprising a combinational circuit section and a register section, wherein the combinational circuit section comprises a plurality of partial circuits, each partial circuit being the register. Is a circuit in which the signal paths are connected to each other when the signal paths connected to the output of the unit are excluded, and the layout cells generated for each of the partial circuits and the individual registers included in the register unit are each a unit. A method for verifying a timing of a semiconductor integrated circuit in which a layout is created as a cell, wherein delay characteristics of individual registers included in the register unit are previously obtained and stored in a first delay characteristic library, and the generation is performed. The layout cells of the individual subcircuits
After the layout of the semiconductor integrated circuit is generated, a circuit analysis is performed based on the individual layouts generated for the individual partial circuits, delay characteristics are obtained, and the partial circuit delay analysis processing is stored in the second delay characteristic library, Based on the first delay characteristic library and the second delay characteristic library,
The individual registers and the individual partial circuits are each used as a unit gate, and a timing verification process is performed to verify the timing of the entire semiconductor integrated circuit in which the layout is created.

Further, in the timing verification method for a semiconductor integrated circuit according to the present invention, the timing of the semiconductor integrated circuit includes a gate whose load capacitance of an input pin changes according to the state of another input pin or the internal state. In the verification method, for each input pin of each gate, the minimum capacitance value and the maximum capacitance value to be taken in all the states are obtained in advance, and the output pin of each gate is assigned to each gate. The minimum delay value and the maximum delay value are obtained based on the minimum capacitance value and the maximum capacitance value of the input pins of all the connected gates, and the minimum delay value and the maximum delay value are defined for each gate, and the static timing It is characterized in that it is checked at the gate level whether the given timing conditions are satisfied by analysis.

In addition, the invention according to claim 8 is the timing verification method for a semiconductor integrated circuit according to claim 7, wherein some of the gates are of a pass transistor logic whose input signal is applied to a gate terminal and a source terminal. It is characterized by being composed of a logic circuit.

In addition, the invention according to claim 9 is the method for verifying timing of a semiconductor integrated circuit according to claim 6, wherein the partial circuit has a load capacitance of an input pin which is in a state of another input pin or an internal state. Including a plurality of gates that change according to the partial circuit delay analysis process, for each input pin of each gate, the minimum capacitance value and the maximum capacitance value to be taken in all the states are obtained in advance, For each of the gates, a minimum delay value and a maximum delay value are obtained based on the minimum capacitance value and the maximum capacitance value of the input pins of all the gates connected to the output pins, and the second delay characteristic library is obtained. In the timing verification process, the minimum delay value and the maximum delay value are defined for each gate, and static timing analysis is performed to obtain the timing verification of the entire semiconductor integrated circuit in which the layout is created. And performing at Toreberu.

With the above structure, in the invention according to claim 1, first, a given logic circuit is separated into a combinational circuit section and a register section, and a portion having a high degree of connection which constitutes the separated combinational circuit section. Each circuit is converted into a transistor level circuit, and then a layout cell of the transistor level partial circuit is generated. After that, a layout cell corresponding to each register included in the register section,
A layout of blocks is created by arranging and wiring the layout cells for each of the partial circuits in the combinational circuit unit as unit cells.

In the combinational circuit section, a layout cell is generated once for each partial circuit having a high degree of connection, and the layout cell of each partial circuit is used as a unit cell.
A layout with good characteristics can be created with a small number of types of cells in both the OS logic circuit and the pass transistor logic circuit. In particular, in the case of a pass transistor logic circuit, a circuit having a high degree of connection is laid out in one cell, so that an optimal driving ability can be obtained, a layout with stable characteristics can be created, and area saving, low power consumption, and It is possible to secure superiority such as high-speed operation.

Further, in the inventions according to claims 2 and 4, a plurality of subcells prepared in advance in the subcell library are arranged and wired adjacent to each other to form a new cell (main cell).
After creating the layout and registering it in the main cell library,
A block layout is created using the sub cell library and the main cell library as cell libraries.

Since the sub-cells are combined to form the main cell, the composite gate and the circuit portion of the pass transistor logic can be formed by combining the sub-cells. Therefore, many kinds of cell layouts need not be prepared in advance. , A block layout with good characteristics is created with a small number of types of cells.

Further, in the inventions according to claims 3 and 5, as subcells, two transistors of the same polarity (that is, two N transistors) in which source terminals which are basic constituent elements of the pass transistor logic are coupled to each other. A given logic circuit is represented by a binary tree because it includes a cell composed of a channel transistor or two P-channel transistors, and one node of the binary tree and two parallel branches connected to the node. If and are associated with one sub cell, the layout of the pass transistor logic can be easily realized.

In addition, according to the sixth aspect of the invention, with respect to the register section that requires a lot of calculation time and storage area for delay analysis, the delay characteristic is obtained in advance for each individual register. On the other hand, in each partial circuit of the combinational circuit unit, that is, in a circuit part having a high degree of connection including a circuit such as a pass transistor logic, each partial circuit is generated by one layout cell, and circuit analysis is performed on each layout cell. Since the delay characteristic is obtained by performing the above procedure, the delay characteristic can be obtained correctly and the timing verification can be performed with high accuracy.
Moreover, since the delay characteristic is obtained for each layout, the verification can be performed at a higher speed than in the case of performing the timing verification for the entire layout of the required logic circuit.

According to the inventions of claims 7 to 9,
As the capacitance value of the input pin of each gate, the minimum capacitance value and the maximum capacitance value that can be taken in all the states are used instead of a predetermined fixed value, and the minimum delay value and the maximum delay value are based on these capacitance values. Since both delay values are defined in the gate and the timing verification is performed by static timing analysis, accurate timing verification is possible in consideration of the limit delay values in all possible combinations. Moreover, since verification is performed at the gate level, high-speed timing verification is possible.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The layout design method and timing verification method for semiconductor integrated circuits according to the embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) An embodiment of the invention described in claims 1 and 6 will be described below.

FIG. 1 is a flow chart showing the flow of a layout design method and a timing verification method for a semiconductor integrated circuit.

In the figure, 101 is a gate-level netlist of a given logic circuit, 102 is circuit separation processing, and the gate-level netlist 101 is shown.
Is separated into a combinational circuit section and a register section, and then the separated combinational circuit section is separated into a plurality of partial circuits, and a cell level netlist is generated with each partial circuit as one cell. To do. Reference numeral 103 is a cell-level netlist generated by the circuit separation processing 102.

Reference numeral 104 denotes the circuit separation processing 102.
Transistor circuit conversion processing for converting each partial circuit into a transistor-level circuit for each partial circuit separated by
Reference numeral 105 denotes a transistor-level netlist for each partial circuit generated by the transistor circuit conversion processing 104,
Reference numeral 106 denotes a partial circuit layout generation process for generating a layout from the net list 105 of the transistor level partial circuit, and 107 denotes a partial circuit layout cell generated by the partial circuit layout generation process 106.

Further, 108 is a given register layout cell library, and 109 is a layout placement / wiring process, which inputs the cell-level netlist 103, the partial circuit layout cells 107, and the register layout cell library 108. Then, the cell-based placement and routing is performed to generate the layout. 110 is layout data generated by the layout and wiring process 109.

In addition, 111 is a register delay characteristic library (first delay characteristic library) for storing the delay characteristic of the register portion, and 112 is a partial circuit delay for performing the delay analysis of the partial circuit from the layout cell 107 of the partial circuit. Analysis processing, 113 is a partial circuit delay characteristic library (second delay characteristic library) for storing the delay characteristics analyzed by the partial circuit delay analysis processing 112, 114 is timing verification processing, and the register section delay characteristic library 111, the partial circuit delay characteristic library 11
3 and the cell-level netlist 103, the timing of a given logic circuit is verified. Reference numeral 115 is a determination process for returning to the transistor circuit conversion process 104 when the result of the timing verification process 114 does not satisfy the desired timing.

Detailed description of the layout designing method of the semiconductor integrated circuit and the timing verification according to the present embodiment will be described below with reference to the flowchart of FIG.
This is performed using the examples of FIGS. 3, 4, 5, and 6.

FIG. 2 shows an example of a logic circuit corresponding to the gate-level netlist 101 of FIG. 1 which is an input of this embodiment. In FIG. 2, 200 is a register unit, 2
01 is a register cell that constitutes the register unit 200,
202 is a clock input terminal to the register cell 201, 2
Reference numeral 03 is a data input terminal of the register cell 201, 204 is a data output terminal of the register cell 201, 205 is a combinational circuit section, and 206 and 207 are the combinational circuit section 205, respectively.
Is a plurality of (two in the figure) partial circuits constituting the.

The respective partial circuits 206 and 207 are respectively
This is a circuit portion in which the signal paths are connected to each other when the signal paths connected to the output of the register unit 200 are excluded.

In this embodiment, the circuit separation processing 102 separates the netlist representing the logic circuit of FIG. 2 into a register unit 200 and a combination circuit unit 205, and further, the combination circuit unit 205 has a plurality of parts. Circuits 206 and 207
Is separated into Next, the circuit separation processing 102 is performed as shown in FIG.
A netlist corresponding to the cell-level circuit shown in FIG. 3 is also generated from the netlist corresponding to the gate-level circuit shown in FIG.

FIG. 3 shows a cell-level logic circuit in which the partial circuits 206 and 207 separated by the circuit separation processing 102 are each replaced by one cell. In the figure,
Reference numeral 301 denotes a cell corresponding to the partial circuit 206, and 302 denotes a cell corresponding to the partial circuit 207.

The partial circuits 206 and 207 separated by the circuit separation processing 102 are converted into the transistor level circuits shown in FIG. 4 for each partial circuit by the transistor level circuit conversion processing 104. A transistor-level netlist 105 for each circuit is generated.

In FIG. 4, in the transistor level circuit generation processing 104, the partial circuits 206 and 207 are replaced by BDD (B
FIG. 6 is a circuit diagram of a transistor level realized by an N-channel pass transistor logic, respectively, by using an inward Decision Diagram). Partial circuit 20
Reference numerals 6 and 207 correspond to FIGS. 4A and 4B, respectively.

Next, partial circuit layout cell generation processing 1
At 06, the netlist 105 for each partial circuit is input to generate a layout cell for each partial circuit 206, 207. The method to generate the layout cell of the partial circuit is
There is a method of automatically synthesizing layouts by cell generation that inputs the netlist 105 of the partial circuit. 5 (a) and 5 (b) are shown in FIGS. 4 (a) and 4 (b), respectively.
A layout in which the transistor-level partial circuits shown in (1) are combined by cell generation is shown. Although an example using cell generation is shown here, the method of creating a layout cell is not limited to this, and other sub-cells are used as in the second and third embodiments of the present invention described below. The method of generating a layout cell of a partial circuit using this subcell is the invention according to claim 4, and the library of the subcell includes two identical source terminals. A fifth aspect of the present invention is a configuration including a sub cell including a transistor having a polarity.

In FIG. 5A and FIG. 5B, 50
1 is a cell frame, 502 is a diffusion region forming an N-channel transistor, 503 is a first metal wiring layer, 504 is a contact connecting the diffusion region 502 and the first metal wiring layer 503, 505 is a second metal wiring layer, 506 is a diffusion region 502
A contact for connecting the second metal wiring layer 505 with the second metal wiring layer 505,
Reference numeral 7 is a polysilicon wiring forming the gate of the transistor, and 508 is an input / output terminal of the layout cell.

Next, the placement and routing processing 109 inputs the cell-level netlist 103, the register layout cell library 108, and the layout cells 107 of the partial circuits, and generates the layout data 110 of the block.
The placement and routing processing 109 is realized by a cell-based automatic placement and routing system used for normal layout design.

FIG. 6 shows a layout diagram corresponding to the layout data 100 of the block generated in the layout and wiring processing 109. The figure shows a layout diagram corresponding to the circuit diagram of FIG.

In the figure, 601 is a layout block outer frame, 602 is a register cell, 603 is a block external clock terminal, 604 is a block external power supply terminal, and 605.
5 is a block external ground terminal, 606 is a block external signal input / output terminal, and 607 corresponds to the partial circuit 206.
The layout cell shown in (a), 608 is the partial circuit 2
The layout cell shown in FIG. 5B corresponding to 07,
610 is a first metal wiring layer, 611 is a second metal wiring layer, 6
Reference numeral 09 is a contact that connects the first metal wiring layer 610 and the second metal wiring layer 611.

After the block layout is generated as described above, the partial circuit delay analysis processing 112 performs the circuit delay analysis on the layout cell 107 corresponding to each partial circuit 206, 207, and the partial circuits 206, 207. The respective delay characteristics of are obtained. For example, the delay model obtained by performing the circuit delay analysis on the partial circuit layout of FIG. 5A generated from the partial circuit 206 is shown in the following form.

[0052] In the above, “→” represents the time from the time when the input signal changes to the time when the output signal changes.

When the partial circuits 206 and 207 have a circuit of pass transistor logic, the calculation of the delay characteristic thereof is performed by the fourth embodiment described later.

Next, in the timing verification processing 114, based on the partial circuit delay characteristic library prepared by preparing the delay model as described above for each partial circuit 206 and 207 and the individual register delay characteristic 111, Using a register and each partial circuit as a unit gate, the simulator verifies the timing of a given logic circuit.
In the timing verification by simulation, if a timing error occurs, the transistor circuit conversion processing 104 re-optimizes the transistor, and the circuit is generated again.

As described above, according to the first embodiment of the present invention, the combinational circuit section is separated for each partial circuit having a high degree of connection in which the signal paths are connected to each other, and the partial circuit is used as a unit. Since the cell is used, the layout design using the existing automatic placement and routing processing can be performed without developing many layout cell libraries in both the complete CMOS circuit and the circuit using the pass transistor logic. Further, since the delay characteristic is calculated for each layout of each of the partial circuits, the delay characteristic is correctly calculated, which enables highly accurate timing verification, and is compared with the case where the timing verification is performed for the entire layout of the required logic circuit. Thus, high-speed timing verification is possible.

(Second Embodiment) The second embodiment of the present invention will be described below with reference to the drawings.

FIG. 7 shows a flow chart of the layout design method of the semiconductor integrated circuit of the present invention.

In the figure, 701 is a sub-cell layout library (sub-cell library), 702 is a logic circuit netlist, 703 is a main cell layout generation process (main cell generation process), and 704 is the main cell layout generation process 70. It is a layout library (main cell library) of the main cell generated by. Further, reference numeral 705 denotes an automatic placement / routing process (layout placement / wiring process) for converting the logical circuit netlist 702 into layout data from the sub cell layout library 701 and the main cell layout library 704, and 706 the automatic placement / routing process 70.
It is the layout data generated in 5.

Details of the layout designing method shown in FIG. 7 will be described below with reference to FIGS. 8, 9, 10, and 11. In addition, in FIGS. 8, 10 and 11, the inside of the cell is drawn by a symbol, but in reality, the mask pattern is drawn.

FIG. 8 shows the subcell layout library 70.
1 shows an example. Sub-cell layout library 7 in the figure
In 01, the layouts of a plurality of subcells are stored in advance. Each of the sub-cells is composed of at least one or more transistors, and for example, inverter gates 801, 802, 803 having different driving capabilities as shown in FIG.
NAND gates 804, 805, 80 having different driving capabilities
6, and NOR gates 807, 808 having different driving capabilities,
809 and register 810. Incidentally, since one normal cell is composed of one logic having a predetermined driving ability, it is divided into a logic portion and a driving ability portion, and various kinds of subcells are stored in the driving ability portion. You may stay.

FIG. 9 shows an example of the input netlist 702. 901 is a NOR gate, 902 is an inverter gate, 903 is a NAND gate, and 904 and 905 are OR gates. Also, 906, 907, 908, 90
Reference numerals 9 and 910 are input registers, and reference numerals 911 and 912 are output registers.

In the netlist shown in FIG. 9, the layout of each gate 901, 902, 903 is prepared in the subcell library 701 of FIG.
04 and 905 do not exist in the sub cell layout library 701. Therefore, the main cell layout generation processing 70
3 selects each subcell of the subcell layouts 802, 803, 807, and 808 required to generate the OR gates 904 and 905 that do not exist in the subcell library from the subcell layout library 701 and selects the subcells. The adjacent sub-cells 802 and 807 generate a layout corresponding to the OR gate 904, and the adjacent sub-cells 803 and 808 generate a layout corresponding to the OR gate 905.

FIG. 10 shows an example of the layout generated in this way. 1001 is a layout corresponding to the OR gate 904, and 1002 is a layout corresponding to the OR gate 905. These generated layouts are
The main cell layout is registered and stored in the main cell layout library 704.

The automatic placement and routing processing 705 creates layout data 706 corresponding to the given netlist 702 of FIG. 9 based on the subcell layout library 701 and the main cell layout library 704 generated as described above. Output. FIG. 11 shows an automatic placement / routing process 70.
5 shows an example of the layout data 706 output according to No. 5. In the figure, 1101 is a cell row, and cell row 1
Subcells 801, 805, 807, 810 and main cells 1001, 1002 are arranged and wired at 101.

As described above, in the layout design using the flowchart of the present embodiment, the circuit portion including the composite gate is created by combining the subcells, so that many types of layout cells are not prepared in advance. It is possible to perform layout design using the automatic placement and routing process of.
Further, in the newly created main cell, since the sub cells are arranged adjacent to each other, it is possible to suppress the delay due to the wiring and reduce the power consumption.

(Third Embodiment) The third embodiment of the present invention will be described below. The embodiment of the present invention shows a layout design method in the case of including the basic portion of the pass transistor gate as a subcell in the second embodiment.

This embodiment will be described with reference to FIGS. 12, 13, 14 and 15 along the flowchart of FIG. In addition, in FIG. 12, FIG. 14, and FIG. 15, the inside of the cell is drawn by a symbol, but in reality, the mask pattern is drawn.

FIG. 12 shows the subcell layout library 7
01 shows an example. The sub-cell shown in the figure includes a cell composed of two transistors of the same polarity whose source terminals are coupled to each other. That is, in the sub-cell layout library 701 shown in FIG.
Reference numeral 3 is an N-channel pass transistor gate subcell having a different driving capability, 1204 is an inverter gate subcell, and 1205 is a register subcell.

FIG. 13 shows an input netlist 702.
An example is shown, showing a full adder assembled using pass transistor logic. In the figure, 1301,
1302 is an inverter gate, 1303, 1304, 1
Reference numeral 305 is an input register, 1306 and 1307 are output registers, and 1311 and 1312 are partial circuits.

The main cell layout generation process 703 is performed by the process shown in FIG.
3 partial circuits 1311 and 1312 are respectively generated as main cells. The main cell layout generation processing 703 generates a layout corresponding to the partial circuits 1311 and 1312 when the sub cell layout 120 is generated.
Subcells 1, 1202, 1203, 1204 are selected from the subcell layout library 701, and the selected subcells are placed and wired to generate main cell layouts corresponding to the partial circuits 1311, 1312. FIG. 14 shows an example of the main cell layout generated in this way. In the figure, reference numeral 1401 is a main cell corresponding to the partial circuit 1311, and is composed of subcells 1201, 1202, 1204. Further, 1402 is a main cell corresponding to the partial circuit 1312, and is a subcell 1201, 1202, 120.
3, 1204. The main cell layout generated in this way is stored in the main cell layout library 7
It is stored in 04.

The automatic placement and routing processing 705 is based on the sub cell layout library 701 and the main cell layout library 704 generated as described above, and the layout data 7 corresponding to the given netlist 702.
06 is output. An example of the layout data 706 output by the automatic placement and routing processing 705 in this manner is shown in FIG.
Shown in In the figure, reference numeral 1501 denotes a cell row, and the cell row 1501 includes a sub cell 1205 and a main cell 1401.
1402 is arranged and wired.

As described above, in the layout design using the flowchart of the present invention, the circuit portion assembled by using the pass transistor logic is also prepared by combining the subcells, so that many kinds of layout cells are prepared in advance. Without this, a layout design using the existing automatic placement and routing processing becomes possible. Further, in the newly created main cell, since the sub cells are arranged adjacent to each other, it is possible to suppress the delay due to the wiring and reduce the power consumption.

Although the present embodiment uses two N-channel transistors, the same processing can be performed by using a subcell formed by connecting two P-channel transistors, and the same effect can be obtained. Of course, it is possible to obtain

(Fourth Embodiment) A timing verification method for a semiconductor integrated circuit according to an embodiment of the present invention will be described below with reference to FIGS. 16 and 17.

FIG. 16 shows an example of a cell (gate) whose input capacitance changes according to the input signal of the terminal. In the figure, 1601 is a cell boundary, and 1602, 1603, 16
04 is an input terminal (input pin), 1605 is an output terminal, 1
Reference numeral 606 is an N-channel transistor, and 1607 is an inverter gate.

In FIG. 16, when the input level of the input terminal 1603 is low level, the N-channel transistor 16
06 is in an off state, and the input load capacitance of the input terminal 1602 is only the drain capacitance of the N-channel transistor 1606 when the wiring capacitance is ignored.
When the input level of 03 is high, the N-channel transistor 1606 is turned on and the input terminal 160
When the wiring capacitance is ignored, the input load capacitance of 2 becomes a capacitance obtained by adding the drain capacitance of the N-channel transistor 1606, its source capacitance, and the gate capacitance of the inverter gate 1607.

FIG. 17 shows an example of a circuit using the cell of FIG. In the figure, 1701 is the cell shown in FIG. 16, 1702 is another cell, 1703 is the output terminal of the cell 1702, 1704 is the input terminal of the cell 1702, 170
Reference numerals 5, 1706, 1707, and 1708 are terminals for connecting to the outside. The input terminal 1602 of the cell 1701 is connected to the output terminal 1703 of another cell 1702. In addition, the input terminal 1704 of the cell 1702 is connected to the external connection terminal 1705, and the terminal 1603 of the cell 1701,
Reference numerals 1604 and 1605 denote connection terminals 1706 for external connection,
It is connected to 1707 and 1708.

When performing the timing verification of the circuit of FIG. 17, it is necessary to obtain the delay value of the output terminal 1703 of the cell 1702, and for that purpose, the load capacitance of the input terminal 1602 of the cell 1701 connected to the output terminal 1703 is required. Need to be calculated. Here, as described above, the input capacitance of the input terminal 1602 of the cell 1701 is the input terminal 1603.
Is minimum when the input level is low and maximum when the input level of the input terminal 1603 is high. Therefore, the minimum input capacitance value and the maximum input capacitance value are obtained in advance, and the delay value is set for each case. Ask for. These two types of minimum delay value and maximum delay value are stored in the cell 1701.
And pass it to the simulator, and verify by static timing analysis whether the desired timing is satisfied in the case of both delay values.

When a netlist has a plurality of cells each having a terminal whose input capacitance changes according to the input signal or the internal state as shown in FIG. 16, the delay value of each output terminal of each cell is changed. Several kinds of verifications are performed by using a delay value that is an appropriate combination of the maximum value and the minimum value to verify whether or not the desired timing is satisfied.

A cell having a terminal whose input capacitance changes depending on an input signal or an internal state is a cell having the logic circuit of the pass transistor logic shown in FIG. 14 in addition to the cell having the configuration shown in FIG. This structure is the structure of the invention according to claim 8. Further, when the partial circuit 206, 207 shown in FIG. 2 of the first embodiment is configured by the logic circuit of the pass transistor logic, the partial circuit delay analysis processing 112 of the first embodiment. And timing verification process 114 (see FIG. 1)
In the above, the fourth embodiment may be applied, and this configuration is the configuration of the invention according to claim 9.

As described above, according to the timing verification method of the fourth embodiment of the present invention, a netlist including cells having terminals whose input capacitance changes according to an input signal or an internal state may occur. The minimum and maximum delay values taken in all combinations can be taken into consideration, and it is possible to accurately verify whether or not the desired timing constraint can be satisfied.

The present invention can be realized by the hardware configuration shown in FIG. In the figure, 1
Reference numeral 801 is a display device, 1802 is an input keyboard, 1803 is a central processing unit, and 1804 is a storage device in which each information is stored.

[0083]

As described above, according to the semiconductor integrated circuit layout designing method of the present invention, a layout cell is generated once for each partial circuit having a high degree of connection in the combinational circuit section. Since the layout cell of each partial circuit is used as a unit cell, not only a complete CMOS circuit but also a circuit including a pass transistor logic,
A layout with good characteristics can be created with a small number of types of cells. In particular, in the case of a pass transistor logic circuit, a circuit with a high degree of connection is laid out in one cell, so that an optimal drive capability can be obtained, a layout with stable characteristics can be created, and area saving and low power consumption can be achieved. Also, superiority such as high-speed operation can be secured.

According to the semiconductor integrated circuit layout designing method of the present invention as defined in claims 2 to 5, since the main cell is generated by using the sub-cell, the circuit includes a composite gate and a pass transistor logic. However, it is possible to create a block layout having optimum characteristics with a small area by using a small number of types of cell libraries. Moreover, since the cell-based placement and routing is performed, the block layout can be created at high speed.

Further, according to the timing verification method for a semiconductor integrated circuit of the present invention, one layout cell is generated for each circuit portion having a high degree of connection including a circuit such as a pass transistor logic and the like. Since the delay characteristic is obtained for each layout cell, the timing verification can be performed with high accuracy, precision and high speed.

In addition, according to the method of verifying a timing of a semiconductor integrated circuit according to any one of claims 7 to 9, both the minimum delay value and the maximum delay value of the gate level that can be taken in all possible states are determined. Since the timing verification is performed in consideration, accurate and high-speed timing verification is possible even in a circuit including a gate and a pass transistor whose input load capacitance changes.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a flow of a layout design method for a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of a gate-level netlist of a logic circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram showing an example of a cell-level netlist of a logic circuit according to the first embodiment of the present invention.

FIG. 4 is a diagram showing an example in which a partial circuit according to the first embodiment of the present invention is converted into a transistor-level circuit.

FIG. 5 is a diagram showing an example of a layout of partial circuits generated by cell generation according to the first embodiment of the present invention.

FIG. 6 is a diagram showing an example of a layout of a logic circuit generated by a layout and wiring process according to the first embodiment of the present invention.

FIG. 7 is a flowchart showing a flow of a semiconductor integrated circuit layout designing method according to second and third embodiments of the present invention.

FIG. 8 is a diagram showing an example of a sub cell library according to the second embodiment of the present invention.

FIG. 9 is a diagram showing an example of a net list of a logic circuit according to the second embodiment of the present invention.

FIG. 10 is a diagram showing an example of a main cell layout according to the second embodiment of the present invention.

FIG. 11 is a diagram showing an example of a block layout output by an automatic placement and routing process according to the second embodiment of the present invention.

FIG. 12 is a diagram showing an example of a sub cell library according to the third embodiment of the present invention.

FIG. 13 is a diagram showing an example of a net list according to the third embodiment of the present invention.

FIG. 14 is a diagram showing an example of a main cell layout according to the third embodiment of the present invention.

FIG. 15 is a diagram showing an example of a block layout output by automatic placement and routing processing according to the third embodiment of the present invention.

FIG. 16 is a diagram showing an example of a cell according to a fourth embodiment of the present invention.

FIG. 17 is a diagram showing an example of a circuit using the cell of FIG. 16 in the fourth embodiment of the present invention.

FIG. 18 is a diagram showing a hardware configuration for realizing the layout design method and the timing verification method of the semiconductor integrated circuit of the present invention.

[Explanation of symbols]

101 Gate Level Netlist 102 Circuit Separation Process 103 Cell Level Netlist 104 Transistor Circuit Conversion Process 105 Transistor Level Netlist for Each Partial Circuit 106 Partial Circuit Layout Generation Process 107 Partial Circuit Layout Cell 108 Register Layout Cell Library 109 Placement Wiring processing 110 Layout data 111 Register delay characteristic library (first delay characteristic library) 112 Partial circuit delay analysis library 113 Partial circuit delay characteristic library (second delay characteristic library) 114 Timing verification processing 115 Judgment processing 200 Register section 205 Combination circuit unit 701 Sub-cell layout library (sub-cell library) 702 Logic circuit netlist 703 Main cell layout generation processing (main cell generation Processing) 704 Main cell layout library (main cell library) 705 Automatic placement and routing processing (layout placement and routing processing) 706 Layout data 801 to 810, 1204, 1205 Sub cells 1001, 1002 Main cells 1602, 603, 1604 Input terminals (input) Pin) 1605 Output terminal 1606 N-channel transistor 1607 Inverter gate

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Toshiyuki Moriwaki 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (9)

[Claims] 1. A circuit separation process for separating a given logic circuit into a combination circuit section and a register section, and a signal path connected to an output of the separated register section in the separated combination circuit section. If the partial circuits in which the signal paths are connected to each other are excluded, the partial circuit for converting the partial circuit into a transistor level circuit is grasped for each partial circuit, and the converted transistor level partial circuit. A partial circuit layout generation process for generating a layout cell for each partial circuit, an individual layout cell generated for each partial circuit of the combinational circuit unit, and an individual register included in the separated register unit. Each cell is a unit cell, and a cell-based layout is arranged and wired to perform block layout of the given logic circuit. A layout design method for a semiconductor integrated circuit, comprising: 2. A layout of a plurality of subcells composed of at least one or more transistors is prepared in advance as a subcell library, and some of the plurality of subcells are arranged and wired adjacent to each other. A cell layout in which a new cell layout is created and the created new cell layout is registered in the main cell library as a main cell; and a cell-based layout in which the sub cell library and the main cell library are used as cell libraries A layout designing method for a semiconductor integrated circuit, comprising: arranging and arranging a plurality of lines to create a block layout of a given logic circuit. 3. The layout design method for a semiconductor integrated circuit according to claim 2, wherein the subcell library includes a subcell composed of two transistors of the same polarity whose source terminals are coupled to each other. . 4. The partial circuit layout generation process prepares a layout of a plurality of subcells composed of at least one transistor in advance as a subcell library, and some of the plurality of subcells are adjacent to each other. A main cell generation process of creating a new cell layout by arranging and wiring and registering the created new cell layout as a main cell in the main cell library, and the sub cell library and the main cell library The layout and wiring of a cell-based layout is performed as a cell library, and layout layout and wiring processing is performed to generate layout cells of individual partial circuits for each converted transistor-level partial circuit. A method for designing a layout of a semiconductor integrated circuit as described. 5. The semiconductor integrated circuit according to claim 4, wherein the sub-cell library includes a plurality of sub-cells each including two transistors having the same polarity and having source terminals coupled to each other. Layout design method. 6. A combinational circuit section and a register section,
The combinational circuit section is composed of a plurality of partial circuits, and each of the partial circuits is a circuit in which signal paths are connected to each other when a signal path connected to the output of the register section is excluded. A method for verifying a timing of a semiconductor integrated circuit in which a layout is created by using a layout cell generated for each and individual registers included in the register unit as unit cells. , The delay characteristic is calculated and stored in the first delay characteristic library, and the layout cells of the generated partial circuits are individually generated for each of the partial circuits after the layout of the semiconductor integrated circuit is generated. Circuit delay analysis processing that performs circuit analysis based on the layout of the Based on the first delay characteristic library and the second delay characteristic library, timing verification of the entire semiconductor integrated circuit in which the layout is created by using the individual registers and the individual partial circuits as unit gates is performed. A timing verification method for a semiconductor integrated circuit, comprising: performing a timing verification process. 7. A timing verification method for a semiconductor integrated circuit including a gate, wherein a load capacitance of an input pin changes in accordance with a state of another input pin or an internal state, wherein each input pin of each gate includes: In advance, the minimum capacitance value and the maximum capacitance value to be taken in all the states are obtained, and for each of the gates, the minimum capacitance value and the maximum capacitance value of the input pins of all the gates connected to each output pin thereof. Obtain the minimum delay value and the maximum delay value based on the capacitance value, define the minimum delay value and the maximum delay value for each gate, and determine whether the given timing conditions are satisfied at the gate level by static timing analysis. A method for verifying a timing of a semiconductor integrated circuit, which comprises examining. 8. The timing verification method for a semiconductor integrated circuit according to claim 7, wherein a part of the gates comprises a logic circuit of a pass transistor logic in which an input signal is applied to a gate terminal and a source terminal. 9. The partial circuit includes a plurality of gates in which a load capacitance of an input pin changes according to a state of another input pin or an internal state, and the partial circuit delay analysis process includes an individual input of each gate. Regarding the pins, the minimum capacitance value and the maximum capacitance value to be taken in all the states are obtained in advance, and for each of the gates, the minimum capacitance of the input pins of all the gates connected to each output pin thereof. The minimum delay value and the maximum delay value are calculated based on the value and the maximum capacitance value and stored in the second delay characteristic library. In the timing verification process, the minimum delay value and the maximum delay value are defined for each gate, and 7. The timing verification method for a semiconductor integrated circuit according to claim 6, wherein the timing verification of the entire semiconductor integrated circuit in which the layout is created is performed at the gate level by dynamic timing analysis.