JPH09114730A - Memory controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently transfer the one of a linear array such as font data or the like to a rectangular area. SOLUTION: The font data are stored in a font ROM 25 in a linear array form. A RAM control part 23 performs normal write and read control by a request from a CPU 21 to a RAM 24 and is provided with a function capable of specifying the leading address of a transfer origin, the offset for respective lines of the transfer origin, the width of an X direction (horizontal direction,) a Y direction height (the line number of a vertical direction,) the leading address of a transfer destination, the offset for the respective lines of the transfer destination, bit shift within a data transfer unit width in write to the memory of the transfer destination and a logical operation and the function for adding the respective leading addresses and offset addresses of the transfer origin and the transfer destination so as to transfer data of the bit unit of the rectangular area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device,
More specifically, it relates to a printer controller in a facsimile device or the like.

[0002]

2. Description of the Related Art BitBLT (Bit aligned BLock Tran)
sfer is for performing bit unit data transfer of the rectangular area), and in the memory area shown in FIG. 3 (one cell indicates 1 byte: 8 bits), the data in the rectangular area B is transferred to the rectangular area C. It is to be transferred.

Normally, the access unit of the memory is matched to the bus size of the CPU because of its performance (recently 32 bits is the mainstream). It is most efficient in terms of memory capacity to store font data in units of bytes (8 bits), but transfer font data (usually stored in ROM) to frame memory using BitBLT (depending on hardware). For transfer), the storage unit of the font data was adjusted to the access unit of the memory.

[0004]

Therefore, if the number of typefaces is small and only the Roman characters are used, the storage capacity is not so problematic. However, in the case of Chinese characters, the total capacity required by the storage unit is enormous. Becomes Also, a one-dimensional array cannot be efficiently transferred to a rectangular area.

The present invention has been made in view of the above situation, and enables BitBLT from a rectangular area to a rectangular area effectively, and also enables transfer of a one-dimensional array such as font data to the rectangular area. This is for efficiently performing BitBLT even when the access unit of the transfer destination and the access unit of the transfer source are different.

[0006]

[Means for solving the problem] BitBLT (Bit alig
ned BLock Transfer: transfer source start address, transfer source line offset, X direction (horizontal direction) width, Y direction height (vertical line) Number), the start address of the transfer destination,
It has a function to specify the offset for each line of the transfer destination, a bit shift within the data transfer unit width in writing to the memory of the transfer destination, and a logical operation, and a start address and offset address addition function for each of the transfer source and transfer destination. In the memory controller, the byte shift function of the read data makes it possible to perform BitBLT even when the access unit of the transfer destination and the access unit of the transfer source are different.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the configuration of a laser printer which is an embodiment of the present invention. In the figure, 11 is a host computer for sending character information or image information, and 12 is a space between the host computer and a controller. RS232C, Centronics I / F, etc. are well known. Reference numeral 13 is a print controller that receives character information and image information from the host computer 11 and generates image image information. Reference numeral 14 is an L connecting the print controller and print engine.
PVI (laser printer video interface), 15
Is a print engine for printing the image image information generated by the print controller 13 on a sheet.

FIG. 2 is a diagram showing a hardware configuration of the print controller 13 shown in FIG. 1. The print controller 13 includes a CPU 21, a program ROM 22, a RAM control section 23, a RAM 24, a font ROM 25, a non-volatile RAM 26, and a rotation processing section. 27, host interface 2
8, operation panel 29, optional interface 30,
It comprises a video control unit 32 and an engine interface 33, which are connected by a CPU bus 22.

The CPU 21 is a central processing unit for controlling the entire controller, and uses a general-purpose 16-bit or 32-bit CPU. Program ROM2
2 stores a microcode for controlling the CPU 21. The RAM control unit 23 sends a CP to the RAM 24
In addition to performing normal writing and reading control in response to a request from U21, it performs logical operation and bit shift operation on a region secured as a frame memory, and performs DMA (Direct Memory Access) operation.

The RAM 24 is a large-capacity random access memory controlled by the RAM control unit 23, and its bus width is generally the same as that of the CPU. The RAM 24 is mainly used for the following purposes. (A) System memory (b) Input buffer (c) Page buffer (frame memory) (d) Font file (e) Macro file (f) Image file (g) Print control file (h) Video buffer

The present invention relates to the RAM control unit 23 and the rotation processing unit 27, and the present invention will be described below focusing on these. First, in order to perform BitBLT, the following registers in the RAM control unit 23 are set. XW: X-direction Width Register Set the number of Words to be transferred in the X direction (access unit: 32 bits are 1 Word in this embodiment). YHIG: Y-direction High in line Register Specifies the number of lines in the Y direction. SA: Source start Address Register Specifies the start address of the transfer source in byte units. SOFF: Source Offset address Register Set the start address offset between the transfer source lines. DA: Destination start Address Register Specifies the start address of the transfer destination in byte units. DOFF: Destination Offset Address Register Set the start address offset between the transfer destination lines.

EWMR: End Word Mask data Register This is a bit unit mask designation of the final Word data in the transfer in the X direction, and this register and the transfer source data are A
ND and transferred. BSR: Bit Shift Register Specifies the bit shift amount of the transfer source data when the transfer source data is written to the transfer destination after the logical operation. TMBP0,1: Temporary Buffer 0, 1 word (4 bytes) long temporary buffer. tmpSA: Temporary Source start Address
Register Transfer source start address temporary buffer. tmpDA: Temporary Destination start Addr
ess Register Transfer destination start address temporary buffer.

Next, when the data (font data) of the one-dimensional array shown in FIG. 7 is logically OR-transferred to the area A in the memory area shown in FIG. 3 (one cell indicates 1 byte: 8 bits). The operation will be described. FIG.
The two-dimensional array data shown in (1) is replaced with a one-dimensional array. Usually, the font data is stored in the font ROM 25 in the one-dimensional array format. FIG. 7 illustrates reading of data from the transfer source, shift, and writing of data to the transfer destination. FIG. 8 shows the temporary buffers TMPB0,1 depending on the lower 2 bits (adr1, adr0) of the address.
It shows how to combine the contents of 4 to form 4-byte write data.

A RAM for performing BitBLT will be described below.
The operation of the control unit 23 will be described. (1). Set registers. XW: 2 YHIJ: 10 SA: (A1) SOFF: (B1)-(A1) DA: (a1) DOFF: (b1)-(a1) EWMR: BSR: 0 (2) shown in FIG. tmpSA = SA, tmpDA = DA.

(3). SA (Source Start Address Reg
1st word (A1, A2, A3,
A4 (total of 4 bytes) is read (FIG. 7 (1)) and stored in the temporary buffer TMPB0 (not shown).
In this case, since adr1 and adr0 are both "0",
No shift occurs (see FIG. 8).

(4). The result obtained in (3) above (TMPB0 remains unchanged in this case) is the BSR (Bit Shift Re
gister) bit-shift to the right by the value. The shift value is "0"
So it doesn't change. Therefore, the content of TMPB0 is DA
It is written after being logically operated with the contents of the memory locations (a1 to a4) indicated by (Destination Start Address Register). When the shift amount BSR is other than "0", the result spans two words and is written twice (in the explanation example, BSR = "0" is set for simplicity). (5). SA = SA + 4, DA = DA + 4. (6). The second word (4 bytes in total of A5, B1, B2, B3) corresponding to SA (Source Start Address Register) is read out and stored in TMPB0. Also in this case, as in (2), adr1 and adr0 are both "0", so byte
No shift occurs.

(7). The 2nd word is the final data of this line, so EWMR (End Word Mark data Reg)
AND) and TMPB0 are logically ANDed with the contents of the memory location indicated by DA to be written. This completes the data transfer of the first line. (8). Register settings for second line data transfer. SA = tmpSA + SOFF, DA = tmpDA + DO
FF, tmpSA = SA, tmpDA = DA. (9). 1st word corresponding to SA (A5, B1, B
A total of 4 bytes of 2 and B3) are read (FIG. 7 (3)) and stored in the temporary buffer TMPB0. In this case, SA indicates B1 (adr1 = 0, adr0 = 1), but adr1, ad
Both r0 are set to "0" and the word data is read.

(10). If the lower 2 bits (adr1, adr0) of the address indicated by SA are not both "0", SA = SA +
After the calculation of 4, the contents (B4, B5, C
4 bytes (1 and C2 in total) are read out and stored in the temporary buffer TMPB1. In this case, SA is B5 (adr
1 = 0, adr0 = 1) but both adr1 and adr0 are '
Word data is read as 0 '. (11). TMP based on the contents of adr0 and adr1 based on Fig. 8
The combination of B0 and TMPB1 is changed in byte units, and as a result, byte unit shift is performed D (31:
0) is obtained. This is subjected to a logical operation with the content of the address indicated by DA and then written to the address indicated by DA. (12). DA = DA + 4 (SA = SA + 4 has been executed in (10)). (13). 2nd word corresponding to SA (B4, B5, C
4 bytes (1 and C2 in total) are read out and stored in the temporary buffer TMPB0. In this case, SA is B5 (adr1
= 0, adr0 = 1), but both adr1 and adr0 are '
Word data is read as 0 '.

(14). Since the lower 2 bits (adr1, adr0) of the address indicated by SA are not both "0", SA = SA +
After performing the calculation of 4, the content (C3, C4, C
(4 bytes in total of 5 and D1) are read out and stored in the temporary buffer TMPB1. In this case, SA is C4 (adr1
= 0, adr0 = 1), but both adr1 and adr0 are '
Word data is read as 0 '. (15). TMP based on the contents of adr0 and adr1 based on Fig. 8
Change the combination of B0 and TMPB1 in byte units,
As a result, D (31: 0) shifted byte by byte
Get. At the 2nd word, the data on this line ends, so the logical product operation of EWMR and D (31: 0) is performed and the logical operation is performed with the content of the memory location indicated by DA to write. This completes the data transfer for the second line. (16). SA = tmpSA + SOFF, DA = tmpD
A + DOFF, tmpSA = SA, tmpDA = DA. Similarly, the logical sum transfer of the data of the one-dimensional array to the area A is completed by performing the processing up to the 10th line.

[0020]

As is apparent from the above description, according to the present invention, a one-dimensional array such as font data can be transferred to a rectangular area, and the access unit of the transfer destination and the access unit of the transfer source are different. However, BitBLT can be performed efficiently.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a laser printer which is an embodiment of the present invention.

FIG. 2 is a diagram showing a hardware configuration of a controller shown in FIG.

FIG. 3 is a diagram showing transfer of data in rectangular area B to rectangular area C,
FIG. 6 is a diagram for explaining an operation of logically transferring data of a one-dimensional array to a memory area A.

FIG. 4 is a diagram showing an example of two-dimensional array data.

5 is a diagram in which the two-dimensional array data shown in FIG. 4 is replaced with one-dimensional array data.

[Figure 6] EWME (End Word Mark data Register)
It is a figure showing the example of.

FIG. 7 is a diagram for explaining reading of data of a transfer source, shift, and writing of data to a transfer destination.

FIG. 8 is a diagram showing the contents of temporary buffers TMPB0, 1 by the lower 2 bits of an address.

[Explanation of symbols]

11 ... Host computer, 12 ... Host interface, 13 ... Controller, 14 ... LPVI (laser printer video interface), 15 ... Engine, 21 ...
CPU, 22 ... Program ROM, 23 ... RAM control section, 24 ... RAM, 25 ... Font ROM, 26 ... Non-volatile RAM, 27 ... Rotation processing section, 28 ... Host interface, 29 ... Operation panel, 30 ... Option interface , 32 ... Video control unit, 33 ... Engine interface.

Claims (1)

[Claims] 1. In order to perform BitBLT (bit-unit data transfer of a rectangular area), a start address of a transfer source, an offset for each line of the transfer source, a width in the X direction (horizontal direction), and a height in the Y direction (vertical). Number of lines in each direction), start address of transfer destination, offset of each line of transfer destination, function that can specify bit shift and logical operation within data transfer unit width when writing to transfer destination memory, transfer source, transfer destination In the memory control device having the function of adding the respective start address and offset address, the bit BLT is performed by the byte shift function of the read data even when the access unit of the transfer destination and the access unit of the transfer source are different. Memory controller.