JPH09107080A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a large capacitance, by using a lower electrode having a hole with a diameter of a minimum exposure size or below in a DRAM memory cell having a stacked capacitor. SOLUTION: A silicon oxide film 21 has a recessed part with a slanted circumferential edge. After an aluminum film 25 is formed on the silicon oxide film 21, a photoresist 26 is applied. With a mask of reticle pattern 28 on the recessed part, other than the slanted circumferential edge part, the photoresist is exposed. Then, an halation effect is caused to obtain a cylindrical photoresist 26 with a recessed part 30. An etching step is carried out to make the aluminum film 25 and the photoresist 26 cylindrical, and with a mask of aluminum film 25 anisotropic etching is carried out for the silicon oxide film 21 and a polysilicon film 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a DRAM (Dynamic Randam Access Me
It is suitable for use in manufacturing a semiconductor device having a capacitor such as mory).

[0002]

2. Description of the Related Art Recently, in semiconductor devices such as DRAMs,
With the increase in storage capacity and higher integration, the memory cell 1
The flat area per piece has become smaller. As a result, for example, in a 1-transistor / 1-capacitor type DRAM memory cell, in order to secure a capacitor capacity necessary for holding a memory, a stacked type capacitor is used from the viewpoint of increasing the effective surface area of the capacitor.

DR having this stack type capacitor
A method of manufacturing the AM memory cell will be described with reference to FIG.

First, as shown in FIG. 13A, a field oxide film 102 is formed on a P-type silicon substrate 101 by the LOCOS method. Then, a gate electrode 104 covered with an insulating film 103 such as a gate oxide film is patterned, and an N-type impurity diffusion layer 105 serving as a source / drain is formed on the surface of the silicon substrate 101 on both sides of the gate electrode 104. As a result, the MOS transistor forming the memory cell is formed. Then, a silicon oxide film 106 is formed on the entire surface.

Next, as shown in FIG. 13B, CVD
After the polycrystalline silicon film 107 is formed on the entire surface by the
A contact hole 110 reaching the impurity diffusion layer 105 is opened in the polycrystalline silicon film 107 and the silicon oxide film 106 by etching using a photoresist 108 patterned by photolithography as a mask.

Next, as shown in FIG. 13C, after removing the photoresist 108, a polycrystalline silicon film 112 is deposited on the entire surface including the contact holes 110 by the CVD method, and then the patterned photoresist is formed. The polycrystalline silicon films 112 and 107 are etched using 113 as a mask, and processed into the shape of the lower electrode of the capacitor.

Next, as shown in FIG. 13D, after removing the photoresist 113, a capacitor dielectric film 114 is formed on the entire surface by the CVD method. After that, CVD
Polycrystalline silicon film 115 to be an upper electrode on the entire surface by
Is deposited and then patterned to form the shape of the upper electrode. As a result, the capacitors forming the memory cells are formed, and the DRAM memory cell is completed.

Further, the lower electrode of the stack type capacitor has a structure in which a plurality of plate-like blades (fins) are laminated, and a so-called fin structure in which each fin is widened in the lateral direction is adopted to further increase the effective surface area of the capacitor. Spread out
Increasing the capacitance of capacitors is also being carried out. FIG.
4 shows a sectional view of a DRAM memory cell having a fin structure.
In FIG. 14, a gate electrode 123 of a MOS transistor surrounded by a silicon oxide film 122 is formed on a silicon substrate 121, and one of the impurity diffusion layers 127 is electrically connected to a lower electrode 124 made of a polycrystalline silicon film. It is connected to the. The lower electrode 124 has a structure in which disk-shaped polycrystalline silicon films connected at the trunk portion are arranged at intervals, and the capacitor dielectric film 1 is formed on the surface thereof.
25 is deposited. Then, an upper electrode 126 of a polycrystalline silicon film is formed so as to cover the whole.

On the other hand, in the DRAM memory cell, the effective surface area of the capacitor is increased by making the capacitor a trench type in addition to making it a stack type, and the capacitance of the capacitor necessary for storing data is secured. It is also proposed. However, the trench type capacitor has a problem that insulation between trenches tends to be insufficient and a manufacturing process is complicated. Therefore, in a DRAM memory cell, it is important to increase the effective surface area of the stack type capacitor to increase the accumulated charge capacity.

[0010]

However, due to the miniaturization of DRAM memory cells in recent years, even the conventional stacked type capacitor as shown in FIG. 13 can secure the capacitor capacity required for storing data. It's gone. Therefore, it is conceivable to form a comparatively high (thick film) lower electrode and increase the capacitance of the capacitor on its side surface. However, in this case, the step between the capacitor portion and its peripheral portion becomes significantly large. It becomes difficult to flatten the surface in the subsequent steps. As a result, there has been a problem that the wiring formed in the upper layer is broken.

On the other hand, in addition to increasing the film thickness of the lower electrode, it is conceivable to form irregularities on the surface of the lower electrode to increase the capacitance of the capacitor. However, due to the miniaturization of the memory cell, it is already reduced to near the minimum exposure dimension. It has been extremely difficult to process the lower electrode that has become uneven and to form irregularities on its surface.

Further, even when the stack type capacitor has a fin structure, each fin cannot be made sufficiently wide due to the miniaturization of the memory cell, and at the same time, as shown in FIG. Since the ratio of the electrode stem diameter b determined by the above to the fin diameter a becomes large, it has become impossible to secure the capacitor capacity necessary for memory retention. As a countermeasure against this, it is possible to increase the number of fins, but if this is done, the height of the lower electrode becomes high, and the step between the capacitor part and its peripheral part becomes large, which is the same as the stack type capacitor. Problem will occur.

Therefore, an object of the present invention is to secure a large capacitor capacity even in a small plane area by forming a structure having a size equal to or smaller than the minimum exposure dimension in a DRAM memory cell having a stack type capacitor. It is possible to provide a method for manufacturing a semiconductor device that is capable of achieving the above-described steps and does not cause a large step.

[0014]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming a concave portion having an inclination in a peripheral portion on a surface of a base film, and a step of forming a recess on the base film. A step of forming a reflective film on the reflective film, a step of forming a resist film on the reflective film, and by exposing the resist film using the reticle pattern arranged above the recess other than the peripheral portion as a mask. While removing the resist film except under the reticle pattern,
A step of leaving the resist film having a concave portion formed on the surface under the reticle pattern; a step of etching the entire surface of the resist film until the underlying film is exposed from the concave portion; thereafter, the resist film and Etching the base film using at least one of the reflective films as a mask.

In another aspect of the method for manufacturing a semiconductor device of the present invention, a step of forming a conductive film on a semiconductor substrate, a step of forming an insulating film on the conductive film, and a first step on the insulating film. Patterning the resist film, and performing isotropic etching on the insulating film by using the patterned first resist film as a mask to form a concave portion having a peripheral slope on the surface of the insulating film. A step of forming, a step of forming a reflective film on the insulating film after removing the first resist film, a step of forming a second resist film on the reflective film, and the peripheral portion. The second resist film is exposed by using the reticle pattern arranged above the recesses other than the above as a mask to remove the second resist film other than under the reticle pattern and to form recesses on the surface. A step of leaving the formed second resist film under the reticle pattern; a step of etching the entire surface of the second resist film until the insulating film is exposed from the concave portion; 2. A step of etching the insulating film using at least one of the resist film and the reflective film as a mask, and thereafter, at least one of the insulating film, the second resist film and the reflective film. A step of forming a capacitor lower electrode made of the conductive film by etching the conductive film using the mask as a mask; and a step of forming a capacitor dielectric film on the capacitor lower electrode.
Forming a capacitor upper electrode facing the capacitor lower electrode on the capacitor dielectric film.

According to another aspect of the method for manufacturing a semiconductor device of the present invention, at least two or more first conductive films and insulating films are alternately formed, and the uppermost layer is the insulating film. And a step of patterning a first resist film on the uppermost insulating film, and isotropic etching is performed on the uppermost insulating film using the patterned first resist film as a mask. Thereby, a step of forming a concave portion having an inclination in the peripheral portion on the surface of the uppermost insulating film is performed, and after removing the first resist film, a reflective film is formed on the uppermost insulating film. A step of forming a second resist film on the reflective film, and exposing the second resist film with the reticle pattern arranged above the recess other than the peripheral portion as a mask, The reticle The step of removing the second resist film except under the turn and leaving the second resist film having a recess formed on the surface under the reticle pattern, and removing the second resist film from the recess of the second resist film. A step of etching the entire surface until the upper insulating film is exposed, and then a third step of forming an opening end on the reflective film
Patterning the resist film, and forming a groove by anisotropically etching the laminated structure of the insulating film and the first conductive film using the third resist film and the reflective film as a mask. And a step of forming a second conductive film filling the groove after removing the third resist film, and anisotropically etching the second conductive film, the insulating film, and the first conductive film. A step of selectively removing the layered structure of the film, and the etching removal of the insulating film to remove the second conductive film and at least 2
Forming a fin-structured capacitor lower electrode made of the first conductive film, forming a capacitor dielectric film on the capacitor lower electrode, and forming the capacitor lower electrode on the capacitor dielectric film. Forming a facing capacitor upper electrode.

According to the present invention, the diameter of the concave portion formed on the surface of the base film (or the insulating film) is formed to be, for example, about the same as the minimum exposure size, so that the reflective film is formed on the base film. The resist film thus formed remains with a concave portion smaller than the minimum exposure dimension due to the halation effect during exposure. Therefore, by transferring the recesses smaller than the minimum exposure dimension to the base film, it becomes possible to form a structure smaller than the minimum exposure dimension on the base film. As a result, it is possible to form a contact hole having a finer diameter than that of a conventional one, a capacitor having fine unevenness, and the like.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

1 to 3 are sectional views showing a first embodiment in which the present invention is applied to the manufacture of a DRAM in the order of steps. In order to manufacture the DRAM of this embodiment, first, as shown in FIG. 1A, a field oxide film 17 is formed on the P-type silicon substrate 11 by the LOCOS method, and then surrounded by the field oxide film 17. A gate electrode 13 having a film thickness of about 100 to 200 nm and a cap oxide film 14 having a film thickness of about 30 to 50 nm are patterned on a P-type silicon substrate 11 with a gate oxide film 12 interposed therebetween. Then, N-type impurities such as phosphorus are ion-implanted to form the impurity diffusion layer 16, and then the sidewall oxide film 15 is formed on the gate electrode 13 and the cap oxide film 14. After that, ion implantation may be further performed to form a high concentration impurity diffusion layer. Through the above steps, the MOS that constitutes the DRAM memory cell
The transistor 18 is formed. The gate electrode 13 formed on the field oxide film 17 belongs to an adjacent memory cell.

Next, as shown in FIG.
CVD of a polycrystalline silicon film 20 of about 0 to 1000 nm
It is formed on the entire surface by the method. After that, the film thickness 100 to 70
A silicon oxide film 21 of about 0 nm is formed on the entire surface by the CVD method.

Next, as shown in FIG. 1C, a photoresist 22 having a thickness of about 50 to 100 nm is applied on the entire surface. Then, this photoresist 22 is partially exposed to form a pattern having an opening on one impurity diffusion layer 16 of the MOS transistor. Then, using the photoresist 22 as an etching mask, isotropic etching such as wet etching is performed on the silicon oxide film 21 at an aspect ratio of 1: 2. As a result,
In the etched portion of the silicon oxide film 22, the taper angle of the peripheral inclined portion (the inclination angle of the silicon oxide film 21 at the portion where the photoresist 22 and the silicon oxide film 21 are in contact with each other) is about 10 ° to 60 ° and is circular. The recess 23 is formed. Thus, in the present embodiment, the polycrystalline silicon film 2
The reason why the silicon oxide film 21 is formed on the silicon oxide film and isotropically etched is that it is relatively difficult to form the inclined concave portion in the peripheral portion by isotropically etching the polycrystalline silicon film 20. .

Next, as shown in FIG. 2A, after removing the photoresist 22, an aluminum film 25 having a thickness of about 100 nm is formed as a metal film having reflectivity on the entire surface by a sputtering method. Aluminum film 25 at this time
The conditions for forming are: Ar gas pressure about 8 mTorr, sputtering temperature about 150 ° C., and sputtering power about 5 kW.
Other metal films may be used in addition to the aluminum film 25, but aluminum is preferably used because of its excellent reflectivity. After that, thickness 1-2 on the entire surface
An i-line positive photoresist (for example, IP3300 (trade name) manufactured by Tokyo Ohka) 26 having a thickness of about μm is spin-coated.

The reticle pattern 28, which is slightly smaller than the concave portion 23 and has substantially the same shape as that of the concave portion 23 and is arranged on the upper portion of the concave portion 23 other than the peripheral portion, is used as a mask.
250mJ / cm ² ~ 500mJ using wire stepper
The photoresist 26 is partially exposed with an energy density of about / cm ² . Then, the photoresist 26 existing outside the region directly below the reticle pattern 28 is removed by exposure, and the photoresist 26 remains in a cylindrical shape.
At the same time, due to the halation effect due to the light radiated to the peripheral portion of the concave portion 23 being obliquely reflected by the aluminum film 25, as shown in FIG. 2B, the circle left in the region immediately below the reticle pattern 28. A diameter (for example, 0.
A cylindrical recess 30 having a thickness of about 2 μm is formed.
As a result, the photoresist 26 is processed into a cylindrical shape whose bottom is closed. In addition, in FIG.
In order to make it easier to understand the situation, the cylindrical portion is shown in a perspective view. The same applies to the following drawings.

Whether the halation effect is generated or not is determined by the recess 2
3 depends on the taper angle of the peripheral portion and the film thickness of the photoresist 26. That is, if the focal point of the reflected light from the peripheral portion of the recess 23 is near the surface of the photoresist 26, halation occurs. Therefore, the halation effect can be controlled by changing the film thickness of the photoresist 26 or changing the taper angle of the peripheral portion of the recess 23.

Next, as shown in FIG. 2C, the aluminum film 25 other than the portion covered with the photoresist 26 is formed.
Are selectively removed by anisotropic dry etching at a flow rate ratio of BCl ₃ : Cl ₂ = 2: 3. At this time, since the selection ratio of aluminum to the photoresist is as low as about 2 to 3, the aluminum film 25 and the photoresist 26 are simultaneously formed.
Is also etched, and the concave portion 30 of the photoresist 26 becomes an opening reaching the aluminum film 25. Following this, the aluminum film 25 in the recess 30 is removed by etching. As a result, the photoresist 26 and the aluminum film 25 are processed into a cylindrical shape.

Then, after removing the photoresist 26, the silicon oxide film 21 is removed by etching in the Ar gas atmosphere at a flow rate ratio of CHF ₃ : CF ₄ = 11: 13 using the aluminum film 25 as a mask. As a result, the silicon oxide film 21 is also processed into the same cylindrical shape as the aluminum film 25. The photoresist 26 is not removed, and the silicon oxide film 21 is used as an etching mask.
May be etched.

Next, as shown in FIG. 3A, the polycrystalline silicon film 20 is removed by etching in the He gas atmosphere at a flow rate ratio of HBr: Cl ₂ = 3: 20 using the aluminum film 25 as a mask. As a result, the polycrystalline silicon film 20 is also processed into a substantially cylindrical shape like the aluminum film 25 and the silicon oxide film 21. Note that the photoresist 2
6 or the silicon oxide film 21 may be used as an etching mask.

Next, as shown in FIG. 3B, a photoresist (not shown) having the same height as the surface of the silicon oxide film 21 is applied, and then the cap oxide film 14 on the field oxide film 17 is applied. The entire surface is etched back to expose the aluminum film 20 and the silicon oxide film 21.
Is removed. Then, the remaining photoresist is removed by ashing to form a cylindrical polycrystalline silicon film 20 having an outer diameter of about 0.5 nm and an inner diameter of about 0.2 nm.
A lower electrode of the capacitor is formed. At this time, the etching is performed for a predetermined time so that the polycrystalline silicon film 20 does not reach the impurity diffusion layer 16 inside the cylinder. The cap oxide film 14 covering the gate electrode 13 and the sidewall oxide film 15 are formed.
If a silicon nitride film or the like is formed on the aluminum film 20 and the silicon oxide film 21, the aluminum film 20 and the silicon oxide film 21 can be removed without using a photoresist.

Next, as shown in FIG. 3C, ONO (silicon oxide film / silicon nitride film / silicon oxide) as a capacitor dielectric film is formed on the entire surface including the inner wall and the outer wall of the cylindrical polycrystalline silicon film 20. The film 32 is formed by the CVD method and the oxidation diffusion method, and then the polycrystalline silicon film 34 as the capacitor upper electrode is formed on the entire surface by the CVD method.
Are patterned so as to face the polycrystalline silicon film 20. As a result, the capacitor 3 including the polycrystalline silicon film 20, the ONO film 32, and the polycrystalline silicon film 34 is formed.
6 is formed, and a bit line (not shown) and the other impurity diffusion layer 16 are connected to complete the DRAM memory cell including the MOS transistor 18 and the capacitor 36.

As described above, according to the present embodiment, it is possible to form a cylindrical capacitor lower electrode having an inner diameter smaller than the minimum exposure dimension by using the halation effect. Even when the polycrystalline silicon film 20 forming the structure has an outer diameter of only the minimum exposure dimension, the effective surface area of the capacitor is larger than that when a cylindrical lower electrode is simply formed and the side surface of the lower electrode is used to increase the effective surface area of the capacitor. Can be increased about twice. Therefore, even if the height and the width of the lower electrode are reduced with the miniaturization of the memory cell, a sufficiently large capacitor capacitance can be secured. As a result, the step between the capacitor portion and its peripheral portion does not become large, the surface is easily flattened in a later step, and the wiring formed in the upper layer is not broken.

In this embodiment, the polycrystalline silicon film 2 is used.
Although 0 was processed into a cylindrical shape, the present invention is not limited to this, and various design changes such as forming a plurality of openings in the polycrystalline silicon film 20 are possible.

Next, a second embodiment of the present invention will be described with reference to FIGS. 4-6 illustrate the present invention DR
It is sectional drawing which shows 2nd Embodiment applied to manufacture of AM in order of a process.

In order to manufacture the DRAM of this embodiment, first, as shown in FIG. 4A, the field oxide film 17 is formed on the P-type silicon substrate 11 by the LOCOS method, and then the field oxide film 17 is formed. A film thickness of 100 to 200 is provided on the enclosed P-type silicon substrate 11 with a gate oxide film 12 interposed therebetween.
The gate electrode 13 having a thickness of about nm and the cap oxide film 14 having a thickness of about 30 to 50 nm are patterned. And
Impurity diffusion layer 1 by ion-implanting N-type impurities such as phosphorus
After forming 6, the sidewall oxide film 15 is formed on the gate electrode 13 and the cap oxide film 14. After that, ion implantation may be further performed to form a high concentration impurity diffusion layer. Through the above steps, the MOS transistor 18 forming the DRAM memory cell is formed. The gate electrode 1 formed on the field oxide film 17
3 is for an adjacent memory cell.

Next, as shown in FIG. 4B, the film thickness 50
An interlayer insulating film 37 made of a BPSG film or the like is formed on the entire surface with a thickness of about 0 to 1000 nm by a CVD method, and then a contact hole 38 reaching one of the impurity diffusion layers 16 is formed in the interlayer insulating film 37. Then, a polycrystalline silicon film 20 containing impurities such as phosphorus and having a film thickness of about 300 to 500 nm.
Are formed on the entire surface by the CVD method, and the contact hole 38 is buried.

Next, as shown in FIG. 4C, a photoresist 22 having a thickness of about 50 to 100 nm is applied on the entire surface. A silicon oxide film may be formed before the photoresist 22 is applied, as in the first embodiment. Then, the photoresist 22 is partially exposed to expose the one impurity diffusion layer 16 of the MOS transistor.
Process into a pattern with holes on top. Then, using the photoresist 22 as an etching mask, isotropic etching such as wet etching is performed on the polycrystalline silicon film 20 at an aspect ratio of 1: 2. As a result, in the portion to be etched of the polycrystalline silicon film 20, the taper angle of the peripheral inclined portion (the inclination angle of the polycrystalline silicon film 20 at the portion where the photoresist 22 and the polycrystalline silicon film 20 are in contact) is 10 °. A circular recess 23 is formed at about 60 °.

Next, as shown in FIG. 5A, after removing the photoresist 22, an aluminum film 25 having a thickness of about 100 nm is formed as a reflective metal film on the entire surface by a sputtering method. Aluminum film 25 at this time
The conditions for forming are: Ar gas pressure about 8 mTorr, sputtering temperature about 150 ° C., and sputtering power about 5 kW.
Thereafter, an i-line positive photoresist (for example, IP3300 (trade name) manufactured by Tokyo Ohka Kabushiki Kaisha) 26 having a thickness of about 1 to 2 μm is spin-coated on the entire surface.

Then, the reticle pattern 28, which is slightly smaller than the recess 23 and has substantially the same shape as that of the recess 23 and is disposed on the upper portion of the recess 23 except the peripheral portion, is used as a mask.
250mJ / cm ² ~ 500mJ using wire stepper
The photoresist 26 is partially exposed with an energy density of about / cm ² . Then, the photoresist 26 existing outside the region directly below the reticle pattern 28 is removed by exposure, and the photoresist 26 remains in a cylindrical shape.
At the same time, due to the halation effect due to the light radiated to the peripheral portion of the concave portion 23 being obliquely reflected by the aluminum film 25, as shown in FIG. 5B, the circle left in the region directly below the reticle pattern 28 is left. A diameter (for example, 0.
A cylindrical recess 30 having a thickness of about 2 μm is formed.
As a result, the photoresist 26 is processed into a cylindrical shape whose bottom is closed.

Next, as shown in FIG. 5C, the aluminum film 25 other than the portion covered with the photoresist 26 is formed.
Are selectively removed by anisotropic dry etching at a flow rate ratio of BCl ₃ : Cl ₂ = 2: 3. At this time, since the selection ratio of aluminum to the photoresist is as low as about 2 to 3, the aluminum film 25 and the photoresist 26 are simultaneously formed.
Is also etched, and the concave portion 30 of the photoresist 26 becomes an opening reaching the aluminum film 25. Following this, the aluminum film 25 in the recess 30 is removed by etching. As a result, the photoresist 26 and the aluminum film 25 are processed into a cylindrical shape.

Then, after removing the photoresist 26, the polycrystalline silicon film is exposed until the interlayer insulating film 37 is exposed at a flow rate ratio of HBr: Cl ₂ = 3: 20 in a He gas atmosphere using the aluminum film 25 as a mask. 20 is removed by etching. As a result, the polycrystalline silicon film 20
Has a cylindrical shape whose lower part fills the contact hole 38 and whose upper part has an outer diameter of about 0.5 nm and an inner diameter of 0.2 nm.
It is processed into a cylindrical capacitor lower electrode of the order of magnitude. The polycrystalline silicon film 20 may be etched by using the photoresist 26 as an etching mask without removing it.

Next, as shown in FIG. 6, after the aluminum film 25 is removed, the ONO as a capacitor dielectric film is formed on the entire surface including the inner wall and the outer wall of the polycrystalline silicon film 20.
(Silicon oxide film / silicon nitride film / silicon oxide film)
The film 32 is formed by the CVD method and the oxidation diffusion method, and then the polycrystalline silicon film 34 as the capacitor upper electrode is patterned on the entire surface by the CVD method so as to face the polycrystalline silicon film 20. As a result, the polycrystalline silicon film 20, the ONO film 32, and the polycrystalline silicon film 34 are formed.
Is formed, and a DRAM memory cell including the MOS transistor 18 and the capacitor 36 is completed by further performing a process of connecting a bit line (not shown) to the other impurity diffusion layer 16 and the like. .

As described above, according to this embodiment, the effective surface area of the capacitor can be doubled by forming the lower electrode of the capacitor by using the halation effect. Further, since the capacitor is formed on the interlayer insulating film 37, the degree of freedom in designing the capacitor can be improved and the silicon substrate 11 is prevented from being damaged when the polycrystalline silicon films 20 and 34 are patterned. be able to.

Next, a third embodiment of the present invention will be described with reference to the drawings.

7 to 11 are sectional views showing a third embodiment in which the present invention is applied to manufacture of a DRAM in the order of steps. To manufacture the DRAM of this embodiment, first, referring to FIG.
, A field oxide film 47 is formed on the P-type silicon substrate 41 by the LOCOS method, and then the P-type silicon substrate 41 surrounded by the field oxide film 47 is provided with a film thickness of 100 to 100 nm via the gate oxide film 42. The gate electrode 43 having a thickness of about 200 nm and the cap nitride film 44 having a thickness of about 30 to 50 nm are patterned. Then, an N-type impurity such as phosphorus is ion-implanted to form an impurity diffusion layer 46, and then a sidewall nitride film 45 is formed on the gate electrode 43 and the cap nitride film 44. Through the above steps, D
A MOS transistor 48 forming a RAM memory cell is formed. Further, the cap nitride film 44 and the sidewall nitride film 45 may be a laminated structure film of a silicon oxide film and a silicon nitride film.

Thereafter, a polycrystalline silicon film 51 having a film thickness of about 500 nm is formed on the entire surface, and then silicon oxide films 54, 55, 56 having a film thickness of about 50 nm and a film thickness of 100 n are formed.
Polycrystalline silicon films 52 and 53 of about m are alternately laminated by the CVD method.

Next, as shown in FIG. 7B, a photoresist 57 having a thickness of about 50 to 100 nm is applied on the entire surface. Then, the photoresist 57 is partially exposed to form a pattern having an opening on one impurity diffusion layer 46 of the MOS transistor. Then, using the photoresist 46 as an etching mask,
Wet etching with a 0.1% HF solution is applied to the silicon oxide film 56. As a result, in the etched portion of the silicon oxide film 56, the taper angle of the peripheral inclined portion (the inclination angle of the silicon oxide film 56 at the portion where the photoresist 57 and the silicon oxide film 56 are in contact) is 10 ° to 60 °. A circular recess 58 is formed to some extent. As described above, in the present embodiment, the silicon oxide film 56 is formed on the uppermost layer of the laminated structure of the polycrystalline silicon film and the silicon oxide film and isotropically etched by the isotropic etching of the polycrystalline silicon film. This is because it is relatively difficult to form a concave portion having a slope in the peripheral portion.

Next, as shown in FIG. 7C, after removing the photoresist 57, a metal film having a thickness of 20 is formed on the entire surface.
An aluminum film 59 of about 0 nm is formed by the PVD method.

Next, as shown in FIG. 8A, a positive photoresist 61 for i-line having a thickness of about 1 μm is spin-coated on the entire surface. An energy density of about 250 mJ / cm ² is obtained by using an i-line stepper with the reticle pattern 62, which is slightly smaller than the recess 58 and has substantially the same shape as that of the recess 58 and is disposed on the upper portion of the recess 58 other than the peripheral portion, as a mask. Then, the photoresist 61 is partially exposed. Then, the photoresist 61 existing outside the region directly below the reticle pattern 62 is removed by exposure, and the photoresist 61 remains in a cylindrical shape. Along with this, the recess 58
Due to the halation effect of the light radiated to the peripheral portion of the aluminum film 59 being obliquely reflected, the central exposure portion of the cylindrical photoresist 61 remaining in the region immediately below the reticle pattern 62 has a minimum exposure dimension or less. 0.2μ
A recess 63 having a diameter of about m is formed. Whether or not the halation effect is generated depends on the taper angle of the peripheral portion of the recess 58 and the film thickness of the photoresist 61, as in the first embodiment. In this embodiment, the photoresist 61
The film thickness is preferably 2 μm or less.

In the present embodiment, the reticle pattern 62 may not be used, and the photoresist 61 may be partially exposed with an energy density such that the photoresist 61 of 120 mJ / cm ² or less is not exposed on the entire surface. In this case, only the photoresist 61 existing in the central region of the concave portion 58 is exposed to light due to the halation effect due to the light irradiated to the peripheral portion of the concave portion 58 being obliquely reflected by the aluminum film 59, and the developing treatment is performed. A recess 63 is also formed in the photoresist 61 which is removed later and remains on the entire surface.

Next, as shown in FIG. 8B, the aluminum film 59 other than the portion covered with the photoresist 61 is formed.
Are selectively removed by anisotropic dry etching at a flow rate ratio of BCl ₃ : Cl ₂ = 2: 3. At this time, since the selection ratio between aluminum and the photoresist is as low as about 2 to 3, the aluminum film 59 and the photoresist 61 are simultaneously formed.
Is also etched, and the recess 63 of the photoresist 61 becomes an opening reaching the aluminum film 59. Following this, the aluminum film 59 in the recess 63 is removed by etching. As a result, the photoresist 61 and the aluminum film 59 are processed into a cylindrical shape.

Next, as shown in FIG. 8C, after removing the photoresist 61, as shown in FIG. 9A, a photoresist 64 is applied on the aluminum film 59, and the photoresist 64 is applied. An opening having a minimum exposure dimension of about 0.5 μm is formed by photolithography. At this time, the end portion of the opening of the photoresist 64 is the aluminum film 5.
9 is formed.

Next, as shown in FIG. 9B, the aluminum film 59 and the photoresist 64 are used as a mask.
Silicon oxide films 56, 55, 54 and polycrystalline silicon film 5
Anisotropic dry etching is performed on 3, 52 to form a circular groove portion 65 reaching the polycrystalline silicon film 51 and having a diameter of about 0.2 μm. At this time, the surface of the polycrystalline silicon film 51 is slightly over-etched. The groove 65
May be formed so as to reach the impurity diffusion layer 46.

Next, as shown in FIG. 9C, the photoresist 64 is removed by etching or ashing. The aluminum film 59 may be removed by etching.

Next, as shown in FIG. 10A, the groove 6
Film thickness of 100 nm doped with phosphorus so that
A polycrystalline silicon film 66 of a certain degree is formed by the CVD method. Polycrystalline silicon film 66 with the groove 65 buried therein
Will later become the trunk portion of the fin-type capacitor lower electrode.

Next, as shown in FIG. 10B, the polycrystalline silicon films 66, 53, 52, 51 and the silicon oxide films 56, 5 are formed using a photoresist (not shown) as a mask.
By anisotropically etching 5 and 54, the polycrystalline silicon films 66, 53, 52 and 51 and the silicon oxide films 56, 55 and 54 are processed into a cylindrical shape.

Next, as shown in FIG.
By performing wet etching with a% HF solution, the remaining silicon oxide films 56, 55, 54 are sandwiched between the polycrystalline silicon films 66, 53, 52, 51.
Remove only. As a result, the polycrystalline silicon film 66,
A fin-type capacitor lower electrode 67, which is composed of 53, 52 and 51 and has a trunk portion with a diameter of about 0.2 μm, is formed. At this time, the cap nitride film 44 and the sidewall nitride film 45 serve as an etching stopper.

Next, as shown in FIG. 11A, an ONO film 68 as a capacitor dielectric film is formed on the entire surface of the capacitor lower electrode 67 including the upper and lower surfaces of each fin by the CVD method and the oxidation diffusion method.

Next, as shown in FIG. 11B, a polycrystalline silicon film 69 as a capacitor upper electrode is patterned on the entire surface by a CVD method so as to face the lower electrode 67. As a result, the polycrystalline silicon films 66, 53,
52, 51 (lower electrode 67), an ONO film 68, and a capacitor 70 made of a polycrystalline silicon film 69 are formed,
Further, a bit line (not shown) and the other impurity diffusion layer 46
The DRAM memory cell composed of the MOS transistor 48 and the capacitor 70 is completed through the steps such as connecting and.

As described above, according to the present embodiment, since the fin-shaped capacitor lower electrode having the diameter of the trunk portion smaller than the minimum exposure dimension can be formed by using the halation effect, the number of fins and the flat area can be reduced. As compared with the conventional case, the effective surface area of the capacitor can be further increased. Therefore, even if the height and the width of the lower electrode are reduced with the miniaturization of the memory cell, a sufficiently large capacitor capacitance can be secured. As a result, the step between the capacitor portion and its peripheral portion does not become large, the surface is easily flattened in a later step, and the wiring formed in the upper layer is not broken.

In this embodiment, the capacitor lower electrode 67 is formed directly on the silicon substrate 41. However, as shown in FIG. 12, for example, the interlayer insulating film 90 covering the MOS transistor 48 on the silicon substrate 41 is formed. Then, the capacitor lower electrode 67, the ONO film 68, and the polycrystalline silicon film (upper electrode) 69 may be sequentially formed on the interlayer insulating film 90 as shown in FIGS. In this case, if a silicon nitride film (not shown) is formed on the interlayer insulating film 90, the silicon oxide film 56,
The silicon nitride film can function as an etching stopper when removing 55 and 54 by wet etching.

Further, according to the present invention, a contact hole having a hole diameter smaller than the minimum exposure size can be obtained by using it for forming a contact hole other than forming a capacitor. This can be easily implemented by forming a BPSG film or the like instead of the laminated structure of the polycrystalline silicon film and the silicon oxide film in the third embodiment.

[0061]

As described above, according to the present invention,
A concave portion having an inclination in the peripheral portion is formed on the surface of the underlying film, and a resist film formed on this underlying film via a reflective film is formed so that the concave portion is formed on the surface by the halation effect during exposure. Let it remain. Therefore, by forming the diameter of the recess formed in the base film to be approximately the same as the minimum exposure dimension, for example, a recess smaller than the minimum exposure dimension can be formed on the surface of the resist film. Therefore, it is possible to form a structure such as a contact hole smaller than the minimum exposure size in the base film by transferring the concave portion smaller than the minimum exposure size to the base film.

When a DRAM having a stack type capacitor is manufactured according to the present invention, a conductive film such as a polycrystalline silicon film can be processed into, for example, a cylindrical capacitor lower electrode having an inner diameter smaller than the minimum exposure dimension. .
Therefore, the effective surface area of the capacitor can be increased to about twice as large as that of the conventional one. Therefore, even if the height and the width of the lower electrode are reduced with the miniaturization of the memory cell, a sufficiently large capacitor capacitance is secured. be able to. Therefore, the step between the capacitor portion and its peripheral portion does not become large, the surface can be easily flattened in a later step, and the wiring formed in the upper layer can be prevented from being broken. Become.

In addition, according to the present invention, when a DRAM having a fin-type stacked capacitor is manufactured, a fin-shaped capacitor lower electrode having a trunk portion diameter smaller than a minimum exposure dimension can be formed. The effective surface area of the capacitor can be further increased when compared with the conventional case with the same number and the same plane area. Therefore, even if the height and the width of the lower electrode are reduced with the miniaturization of the memory cell, a sufficiently large capacitor capacitance can be secured. Therefore, the step between the capacitor portion and its peripheral portion does not become large, and the surface can be easily flattened in a later step, and it is possible to prevent disconnection of the wiring formed in the upper layer. Become.

[Brief description of the drawings]

FIG. 1 shows a DRA having a stacked capacitor according to the present invention.
FIG. 6 is a cross-sectional view showing the manufacturing method of the first embodiment applied to manufacturing M in the order of steps.

FIG. 2 shows a DRA having a stacked capacitor according to the present invention.
FIG. 6 is a cross-sectional view showing the manufacturing method of the first embodiment applied to manufacturing M in the order of steps.

FIG. 3 shows a DRA having a stacked capacitor according to the present invention.
FIG. 6 is a cross-sectional view showing the manufacturing method of the first embodiment applied to manufacturing M in the order of steps.

FIG. 4 shows a DRA having a stacked capacitor according to the present invention.
FIG. 8 is a cross-sectional view showing the manufacturing method of the second embodiment applied to manufacturing M in the order of steps.

FIG. 5 shows a DRA having a stacked capacitor according to the present invention.
FIG. 8 is a cross-sectional view showing the manufacturing method of the second embodiment applied to manufacturing M in the order of steps.

FIG. 6 shows a DRA having a stacked capacitor according to the present invention.
FIG. 8 is a cross-sectional view showing the manufacturing method of the second embodiment applied to manufacturing M in the order of steps.

FIG. 7 is a cross-sectional view showing, in the order of steps, a manufacturing method of a third embodiment in which the present invention is applied to manufacture of a DRAM having a fin-type stacked capacitor.

FIG. 8 is a cross-sectional view showing the manufacturing method of the third embodiment in which the present invention is applied to the manufacture of a DRAM having a fin-type stacked capacitor in the order of steps.

FIG. 9 is a cross-sectional view showing the manufacturing method of the third embodiment in which the present invention is applied to the manufacture of a DRAM having a fin-type stacked capacitor in the order of steps.

FIG. 10 is a cross-sectional view showing the manufacturing method of the third embodiment in which the present invention is applied to the manufacture of a DRAM having a fin-type stacked capacitor, in the order of steps.

FIG. 11 is a cross-sectional view showing the manufacturing method of the third embodiment in which the present invention is applied to the manufacture of a DRAM having a fin-type stacked capacitor, in the order of steps.

FIG. 12 is a cross-sectional view showing a modified example of the third embodiment of the present invention.

FIG. 13 is a cross-sectional view showing a method of manufacturing a conventional stack type DRAM in the order of steps.

FIG. 14 is a sectional view of a conventional stack type capacitor having a fin structure.

[Explanation of symbols]

 13 Gate Electrode 18 MOS Transistor 20 Polycrystalline Silicon Film (Lower Electrode) 21 Silicon Oxide Film 22 Photoresist 23 Recess 25 Aluminum Film (Reflective Film) 26 Photoresist 28 Reticle Pattern 30 Recess 32 ONO Film (Capacitor Dielectric Film) 34 Polycrystalline silicon film (upper electrode)

Claims (3)

[Claims] 1. A step of forming a concave portion having an inclination in a peripheral portion on a surface of a base film, a step of forming a reflective film on the base film, and a step of forming a resist film on the reflective film. And exposing the resist film using the reticle pattern arranged above the recess other than the peripheral portion as a mask to remove the resist film other than under the reticle pattern and form a recess on the surface. A step of leaving the resist film under the reticle pattern, and a step of etching the entire surface of the resist film from the concave portion until the underlying film is exposed, and thereafter, at least one of the resist film and the reflective film And a step of etching the base film using one of them as a mask. 2. A step of forming a conductive film on a semiconductor substrate, a step of forming an insulating film on the conductive film, a step of patterning a first resist film on the insulating film, and a pattern forming process. Isotropic etching is performed on the insulating film using the first resist film as a mask to form a concave portion having a slope in the peripheral portion on the surface of the insulating film; and removing the first resist film. After that, a step of forming a reflective film on the insulating film, a step of forming a second resist film on the reflective film, and a reticle pattern arranged on the recesses other than the peripheral portion are formed. By exposing the second resist film as a mask, the second resist film other than under the reticle pattern is exposed.
Removing the resist film and leaving the second resist film having a recess formed on the surface under the reticle pattern, and the entire surface of the second resist film until the insulating film is exposed from the recess. And a step of etching the insulating film using at least one of the second resist film and the reflective film as a mask, and then etching the insulating film and the second resist. Forming a capacitor lower electrode made of the conductive film by etching the conductive film using at least one of a film and the reflective film as a mask; and forming a capacitor dielectric film on the capacitor lower electrode. And forming a capacitor upper electrode facing the capacitor lower electrode on the capacitor dielectric film. The method of manufacturing a semiconductor device characterized by a step. 3. A step of forming a laminated structure in which at least two or more first conductive films and insulating films are alternately formed, and the uppermost layer is the insulating film, and a second structure is formed on the uppermost insulating film. Patterning the first resist film, and performing isotropic etching on the uppermost insulating film using the patterned first resist film as a mask to form a concave portion having a slope in the uppermost layer. And a step of forming a reflective film on the uppermost insulating film after removing the first resist film, and a second resist on the reflective film. A step of forming a film, and exposing the second resist film by using the reticle pattern arranged above the concave portion other than the peripheral portion as a mask, thereby exposing the second resist film other than under the reticle pattern.
Removing the resist film and leaving the second resist film having a recess formed on the surface under the reticle pattern; and exposing the uppermost insulating film from the recess of the second resist film. Etching the entire surface, and then patterning a third resist film having open end portions on the reflective film, and masking the third resist film and the reflective film. A step of anisotropically etching the laminated structure of the insulating film and the first conductive film to form a groove, and a second conductive film filling the groove after removing the third resist film. A step of forming, a step of selectively removing the second conductive film, the insulating film, and a laminated structure of the first conductive film by anisotropic etching; and a step of etching away the insulating film. By the second
Forming a fin-structured capacitor lower electrode composed of the conductive film and at least two of the first conductive films; forming a capacitor dielectric film on the capacitor lower electrode; and forming a capacitor dielectric film on the capacitor dielectric film. And a step of forming a capacitor upper electrode facing the capacitor lower electrode.