JPH09106370A - Device and method for controlling memory and information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect the number of waits suitable for a mounted memory and to access the memory corresponding to the detected number of waits. SOLUTION: When initializing a system, 2nd and 3rd RAM 107 and 108 are accessed while changing the number of waits to be set to a wait control part 102 by a CPU 101 and the number of waits to be inserted in the case of accessing each RAM is detected. This detected number of waits is set in the wait control part 102. When accessing the 2nd or 3rd RAM 107 or 108 from the CPU 101, waits are inserted as many as the set number of waits by the wait control part 102.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device and method for controlling memory access. In particular, the present invention relates to a memory control device and method suitable for a device in which a memory can be added or replaced, and an information processing device including the memory control device.

[0002]

2. Description of the Related Art Conventionally, a control system capable of adding or replacing a memory has been known. In this type of system, it is necessary to determine a memory satisfying an access speed predetermined by the system at the time of designing the system. Therefore, although it is possible to add or replace the memory, it is not possible to use a memory that does not satisfy the access speed set for the system.

[0003]

However, if the generation change of the memory is fast as in today's world, the memory decided at the time of design will be out of stock soon, or a memory with lower cost will be developed, and as a result, It often happens that you have to use a memory that is costly.

Further, once the control system is designed, it is possible to select a high-speed memory with access speed priority or a low-speed memory with cost priority, depending on the function to be operated by using the control system. You can't do it.

The present invention has been made in view of the above problems, and a memory control device capable of detecting the number of weights suitable for the mounted memory and accessing the memory with the detected number of weights. Another object of the present invention is to provide an information processing apparatus including the memory control apparatus and the method thereof.

Further, in a system in which a memory is attachable / detachable, a memory to be attached is selected according to a function to be operated (for example, a high speed memory is used with priority on access speed or a low speed memory is used with priority on cost). )
The purpose is to make it possible.

[0007]

A memory control device according to the present invention for achieving the above object has the following configuration. That is, a memory control device for controlling access to the memory, the detecting means for detecting the number of weights to be inserted when the memory is accessed, and the setting means for setting the number of weights detected by the detecting means. And an inserting means for inserting the number of weights set by the setting means when accessing the memory.

Further, preferably, the detecting means and the setting means are executed during initialization processing of a system including the memory control device. For example, the number of waits to be used for accessing the memory is detected and set during system initialization processing such as power-on. For example, in a system in which the memory can be attached and detached, the memory is attached and detached by turning off the power supply. Therefore, when the system is in operation, appropriate settings are always made according to the mounted state of the memory.

Further, preferably, the detection means performs access to the memory with a plurality of types of weights, determines success or failure, and detects the minimum accessible number of weights. Since the number of waits is controlled to the minimum, the memory access speed can be fully exerted.

Further, preferably, there is further provided a capacity detecting means for accessing the memory space including the memory with the number of waits set by the setting means, and detecting the accessible memory capacity based on the success or failure of the access. Since the accessible memory capacity is detected, it is possible to determine whether or not there is a sufficient memory capacity when loading data, for example.

Further, preferably, there is further provided notifying means for notifying the number of weights detected by the detecting means and the memory capacity detected by the capacity detecting means to the outside.

According to another aspect of the present invention, there is provided a memory control device for controlling access to a memory, wherein an accessible memory space is divided into a plurality of blocks. Management means for dividing and managing, detection means for detecting the number of weights to be inserted at the time of memory access for each of the plurality of blocks, and detection means for each of the plurality of blocks Setting means for setting the number of weights,
When an access to the memory occurs, it is detected which of the plurality of blocks the access destination is,
Insertion means for inserting the number of waits set by the setting means into the access cycle corresponding to the detected block.

Further, preferably, the detecting means and the setting means are executed during initialization processing of a system including the memory control device.

Further, preferably, the detecting means makes access to the memory for each of the plurality of blocks with a plurality of types of weights to determine the success or failure of the access.
Detect the minimum number of accessible weights. Since the minimum number of weights is set for each block, an appropriate number of weights can be set for each block even when a different memory is mounted for each block.

Further, it is preferable that a capacity detecting means for executing an access with respect to each of the plurality of blocks with the number of waits set by the setting means, and detecting an accessible memory capacity based on success or failure of the access. Further prepare.

Also, preferably, the capacitance detecting means is
For each of the plurality of blocks, access is executed with the number of weights set by the setting means, and it is determined whether the block is accessible based on the success or failure of the access.

Further, preferably, there is further provided notifying means for notifying outside of the number of weights of each of the plurality of blocks detected by the detecting means and the usable blocks detected by the capacity detecting means.

Further, preferably, the detecting means detects the number of weights to be inserted in a block corresponding to a memory space of a removable memory among the plurality of blocks.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the accompanying drawings.

In the embodiments described below, the ISDN communication control system is used as an example of the information processing apparatus, but it goes without saying that the application of the present invention is not limited to this.

FIG. 1 is a block diagram showing the configuration of an ISDN communication control system according to this embodiment. In FIG. 1, 101 is a CPU, which controls various operations in the ISDN communication control system. A weight control unit 102 controls the weight of the memory access of the CPU 101. A ROM 103 stores the operation program of the ISDN communication control system. Reference numeral 104 denotes a first RAM, which is a memory capable of writing and reading data. Reference numerals 105 and 106 are sockets for additional memory. 107 and 108 are the second RAM,
The third RAM is an additional memory mounted in the ISDN communication control system. Second RAM 107, third RA
M108 is the socket 105, 106,
It can be attached to and detached from the ISDN communication control system.

Reference numeral 109 denotes an ISA interface unit (hereinafter, ISAi / f unit) for connecting the ISDN communication control system to an external device such as a personal computer. 110 is IS
An interface unit (communication i / f unit) for connecting to a DN communication line. Also, 120 is a system bus, 1
Reference numeral 21 is an ISA bus, and 122 is an ISDN communication line. The ISA bus 121 is an expansion bus for a personal computer (hereinafter, personal computer), and is connected to a control unit of a personal computer (not shown).

In the above structure, the ROM 103 stores a control program for basic operation of the ISDN communication control system. The first RAM 104 is the RO
It is composed of a memory having a capacity necessary for the basic operation program of the M103 to operate, and provides a work area of the CPU 101.

A second RAM 107 and a third RAM which are expansion memories
The RAM 108 is a memory for downloading the program, and is used for downloading the program from the personal computer according to the function to be operated by the communication control system and for accumulating the data used by the function. Here, the required memory capacity and memory access speed differ depending on the function to be operated. Therefore, it is configured so that it can be replaced with an additional memory according to the function, and the socket 10 can be replaced each time.
It can be connected to or disconnected from 5, 106. Also, the program required for the function is sent from the personal computer via the ISA bus 121 to the second RAM of the ISDN communication control system.
107 or C downloaded to the third RAM 108
This is executed by the PU 101.

The weight controller 102 controls the access weight when the CPU 101 accesses the memory. The detailed configuration of the weight control unit 101 will be described later.

The communication i / f section 110 is an i / f section for connecting the ISDN communication control system to the ISDN communication line. The data written in the communication i / f unit 110 by the CPU 101 is transmitted to the ISDN 122, and ISDN1
The data received from 22 is read from the communication i / f unit 110 by the CPU 101.

Next, in the ISDN communication control system of this embodiment having the above configuration, the second RAM 1
A description will be given of a configuration that makes it possible to mount memories having different access speeds as 07 and the third RAM 108.

First, the relationship between the access cycle of the CPU 101 and the access weight will be described with reference to the timing chart of FIG. FIG. 2 is a timing chart showing the access timing to the memory of the CPU in this embodiment. 2A shows the CPU 10 when there is no weight.
1 access cycle, FIG. 2B is an access cycle of the CPU 101 at 1 wait, FIG. 2C is an access cycle of the CPU 101 at 2 wait, and FIG. 2D is an access of the CPU 101 at 3 wait. It is a timing chart which showed each cycle.

In each timing chart,
SYSCLK is the system clock of CPU 101, / W
AIT is a weight control signal input to the CPU 101. Further, / BCYL is a bus cycle signal indicating a bus cycle of the CPU 101, which is output from the CPU 101. / RD and / WR are read signals and write signals output from the CPU 101, respectively. / BC
Although YL, / RD, and / WR are independent signals, the timings of the signals are the same, and therefore, a common timing chart is shown here for simplicity. Note that C
When the PU 101 is accessed, only one of / RD and / WR generates a low level pulse, and neither of them simultaneously becomes a low level. The above-mentioned signals are marked with / to indicate that the signals have negative logic.

As shown in FIG. 2, the CPU 101 executes S
It operates in synchronization with YSCLK. The access cycle starts from the T1 cycle, performs the T2 cycle process, and ends at the T3 cycle. The CPU 101 repeats the cycle from T1 to T3 to repeat the memory and I
/ O is being accessed. Further, the CPU 101
By inserting as many TW cycles as the T2 cycle and delaying the T3 cycle, which is the end cycle of access, it is possible to access a memory or I / O having a slow response speed.

First, as shown in FIGS. 2A to 2D, the / WAIT signal is sampled at the falling edge of SYSCLK in the T2 cycle. If the / WAIT signal is at a high level as a result of sampling in the T2 cycle, the wait cycle is not inserted and the T3 cycle is started. This timing is shown in FIG.

As a result of sampling at the T2 cycle, / W
When the AIT signal is low level, a TW cycle which is a wait cycle is inserted after the T2 cycle.
In the TW cycle, the / WAIT signal is sampled again at the falling edge of SYSCLK. If the / WAIT signal is at the high level as a result of sampling in the TW cycle, the wait cycle ends and shifts to the T3 cycle. FIG. 2B shows the timing when the wait cycle is inserted only for this one cycle.

As a result of sampling in the TW cycle, /
When the WAIT signal is low level, another TW cycle is subsequently inserted. Since the TW cycles are inserted one after another until the / WAIT signal becomes high level, as a result, wait cycles are inserted by the number of cycles in which the / WAIT signal is made low level. FIG. 2C shows the case where two wait cycles are inserted, and FIG. 2D shows the case where three wait cycles are inserted.

Next, the weight controller 102 will be described. The weight controller 102 is a circuit that generates the aforementioned / WAIT signal.

FIG. 3 is a block diagram showing the configuration of the weight controller 102. In FIG. 3, 301 is a first register, 302 is a second register, 303 is a WAIT pulse generation circuit, 304 to 311 are a first WAIT pulse selection circuit to an eighth WAIT pulse selection circuit, 312 is an OR gate,
313 and 314 are AND gates. OR gate 31
2 and AND gates 313 and 314 having input and output portions with circle marks indicate that they are negative logic inputs and negative logic outputs. Reference numeral 315 is an address decoder that decodes the address of the system bus 120 and determines the address area being executed.

Reference numeral 320 is a / WAIT signal, 321 is a data bus in the system bus 120, 322 is a data write signal from the CPU 101, / WR signal, 323 is a selection signal of register 1 / CS1 signal, 324 is register 2 The / CS2 signal, 325, which is a selection signal of, is an address bus in the system bus 120.

The weight control unit 102 having the above configuration
According to the WA, the memory space accessible by the CPU 101 is divided into eight blocks, and the WA to be inserted in each block.
It is possible to set the number of IT (0 to 3 in this example). Then, a / WAIT signal for inserting a preset number of WAITs is output according to the block (address signal) accessed by the CPU 101. The details will be described below.

FIG. 4 is a diagram showing a detailed circuit configuration of the WAIT pulse generation circuit 303. Further, FIG. 5 shows the first WAI.
3 is a diagram showing a detailed circuit configuration of a T pulse selection circuit 304. FIG. The second to eighth WAIT selection circuits 305 to 311
Is the same as the first WAIT selection circuit 304, the description thereof will be omitted.

In FIG. 4, 401 to 404 are flip-flops, 405 to 407 are AND gates, and 408 is an inverter. 411 is SYSCLK which is a system clock signal output from the CPU 101, and 412 is C
/ B which is a bus cycle signal output from the PU 101
CYL and 413 are W that outputs a pulse for one wait period
An AIT signal, 414 is a WAIT2 signal that outputs a pulse in a 2 wait period, and 415 is a WAIT3 signal that outputs a pulse in a 3 wait period.

Further, in FIG. 5, 501 to 504 and 50
6 is an AND gate, and 505 is an OR gate. Also,
Signals 513 and 51 input from terminals W1 to W3
Reference numerals 4 and 515 denote a WAIT1 signal, a WAIT2 signal, and a WAIT3 signal, respectively, which are input from the WAIT pulse generation circuit shown in FIG. The S0 and S1 signals 511 and 512 are select signals for selecting which of WAIT1 to WAIT3 is to be used. According to the configuration of FIG. 5, when (S0, S1) is (0, 0), WA
In case of no IT, (1,0), WAIT1 signal is
In the case of (0, 1), the WAIT2 signal is output, and in the case of (1, 1), the WAIT3 signal is output as the Wout signal 516. The WAS signal 517 is a select signal from the address decoder 315, and while this signal is on, the WAIT signal is output from the WAIT select circuit.

Next, an outline of the operation of the weight control circuit 102 shown in FIG. 3 will be described.

In this weight control circuit, the address decoder 315 divides the address space into eight blocks.
Then, the weight value for the address area of each block is set by the first register 301 and the second register 302. The set wait value corresponds to the first to eighth WAIT selection circuits 304 to 31 corresponding to the blocks of each address.
1 is input as S0 and S1. When the CPU 101 accesses a certain address, the address decoder 315 determines the WAS according to the block to which the address belongs.
Any of 1 to 8 becomes high level, and 1st to 8th WA
One of the IT selection circuits 304 to 311 becomes active.

First to eighth WAIT selection circuits 304 to 31
1 is the first register 301 or the second register 302
In accordance with the weight values S0 and S1 set to, the W of the wait pulse output from the WAIT pulse generation circuit 303
Any one of AIT1 to WAIT3 is selected, and is output as a / WAIT signal 302 when the CPU 101 accesses the address area in the corresponding block.

In the present embodiment, the address space of the CPU 101 is displayed in hexadecimal notation 00000000h to FFFFFFFFFFh, and the address decoder 31
5 divides this space into blocks every 20000000h.

That is, 1FF from address 00000000h
FFFFFh address is block 1, 200000000h
Addresses 3FFFFFFFh are blocks 2,400
Block 3 from address 00000h to 5FFFFFFFh, 7FFFFFFFh from address 60000000h
Address is Block 4, 9FF from 80000000h
FFFFFh address is block 5, A0000000h to BFFFFFFFh address is block 6, C000
The block from address 0000h to DFFFFFFFh is block 7, and the block from address E0000000h to FFFFFFFFh is block 8. As a result of decoding the address, the selection signals corresponding to blocks 1 to 8 are WA
S1 to WAS8.

Therefore, if the address accessed by the CPU 101 is the address 00800000h, the WAS
1 signal is output, and if the address is 98000000h, W
AS5 is output.

FIG. 6 is a diagram showing an address map in the ISDN communication control system of this embodiment. As shown in FIG. 6, the first RAM 104 has a block 1 of 00000.
Mapped to the area from address 000h to address 0FFFFFFFh, the ROM 103 stores F0000000 in block 8.
Mapped to the area from address h to FFFFFFFFh. Also, communication i / f unit 110 and ISA i / f (10
9) and the I / O of the weight control unit 102 are block 7
Is mapped from the address D0000000h to the address DFFFFFFFh.

The second RAM 107 is mapped from addresses 40000000h to 7FFFFFFFh in blocks 3 and 4, and the third RAM 108 is mapped from addresses 80000000h in blocks 5 and 6 to BFFFFFFF.
Mapped to address h. The address area of the second RAM 107 and the third RAM 108 is the maximum capacity value of the memory mountable in the socket 105 and the socket 106.

As described above, in this embodiment, the first register 301 and the second register 302 allocate the 2-bit weight setting value register for one block. In the first register 301, the bits D0 and D1 are in block 1, D2 and D3 are in block 2, and D2 and D3 are in block 2.
4 and D5 are assigned to block 3, and D6 and D7 are assigned to block 4. Similarly, in the second register 302, D0
The bits D1 and D1 are assigned to block 5, D2 and D3 to block 6, D4 and D5 to block 7, and D6 and D7 to block 8.

For example, when the weight of the block 1 is 0 weight, (D1, D0) = (0, 0), and when it is 1 weight, (D1, D0) = (0, 1), 2 When the weight is set, (D1, D0) = (1, 0) is set, and when the weight is set, (D1, D0) = (1, 1) is set. In the other blocks, the number of waits is similarly set by setting 2 bits.

First to eighth WAIT selection circuits 304 to 31
WAIT pulse generation circuit 3 is input to W1 to W3
The WAIT1 to WAIT3 signals from 03 are input. Therefore, from the configuration shown in FIG. 5, when the weight value of each block set in the first register 301 and the second register 302 is 0 (S0 = 0, S1 = 0), the AND gate 501 is selected and the OR gate is selected. Output goes low. Further, when the weight value is 1 (S0 = 1, S
1 = 0), the AND gate 502 is selected and the WAI
The signal of T1 is output from the OR gate 505. Also,
AN when the weight value is 2 (S0 = 0, S1 = 1)
The D gate 503 is selected and the signal of WAIT2 is output from the OR gate 505. And the weight value is 3
In the case of (S0 = 1, S1 = 1), the AND gate 504
Is selected and the signal of WAIT3 is output from the OR gate 505.

The output of the OR gate 505 is the WAS 1-8 signals from the address decoder 315 and the AND gate 506.
Is controlled by Therefore, when the CPU 101 accesses a block at an arbitrary address, the address decoder 3
A wait signal according to the wait value set in the first register 301 or the second register 302 is output from the WAIT selection circuit selected by the output signal 15 and is output as the / WAIT signal 320 via the OR gate 312 of negative logic. Is output.

Next, the operation of the weight control unit 102 will be described with a specific example. Here, the case where the block 1 of the address map is set to 0 weight, the blocks 3 and 4 are set to 1 weight, the blocks 5 and 6 are set to 2 weights, and the blocks 7 and 8 are set to 3 weights will be described. Note that block 2 is not used in this example.

In the above case, the setting of the first register 301 is [D7, D6, D5, D4, D3, D2, D1, D0].
= [0,1,0,1,0,0,0,0] and the setting of the second register 302 is [D7, D6, D5, D4, D
3, D2, D1, D0] = [1, 1, 1, 1, 1, 0,
1, 0]. Since the block 2 is unused, it is set to 0 weight here. In the case of the register setting as described above, the first to eighth WAIT selection circuits 304 to 311 operate as follows.

First WAIT selection circuit 304 and second WAIT
In the T selection circuit 305, since [S1, S0] = [0, 0], the AND gate 501 is selected, and the OR gate 50 is selected.
The output of 5 is always low level. Therefore, when the WAIT selection circuit is selected by the WAS signal 517, Wout
A low level is output to.

Third WAIT selection circuit 306 and fourth WAI
In the T selection circuit 307, since [S1, S0] = [0, 1], the AND gate 502 is selected, and the OR gate 50 is selected.
The W1 input signal (that is, the WAIT1 signal) is output to 5. Therefore, when the WAIT selection circuit is selected by the WAS signal 517, the WAIT1 signal is output to Wout.

The fifth WAIT selection circuit 308 and the sixth WAIT
Since [S1, S0] = [1, 0] in the T selection circuit 309, the AND gate 503 is selected and the OR gate 505 is selected.
The W2 input signal is output to. Therefore, the WAS signal 51
When the WAIT selection circuit is selected in 7, the WAIT2 signal is output to Wout.

The seventh WAIT selection circuit 310 and the eighth WAIT
In the T selection circuit 311, since [S1, S0] = [1, 1], the AND gate 504 is selected and the OR gate 505 is selected.
The W3 input signal is output to. Therefore, the WAS signal 51
When the WAIT selection circuit is selected in 7, the WAIT3 signal is output to Wout.

CPU 101 is the first RAM 1 of block 1.
When 04 is accessed, the address decoder 325 outputs W
The AS1 signal is output. Since the first WAIT selection circuit 304 is selected by this WAS1 signal, / WAI
A high level signal is output as the T signal. Therefore, as shown in FIG. 2A, the high level of the / WAIT signal is sampled in the T2 cycle, and C
The PU 101 shifts to the T3 cycle which is the end of access. Therefore, the access to the first RAM 104 is 0 wait.

Further, the CPU 101 makes the second R of the block 3
When accessing the AM 107, the address decoder 325
Outputs a WAS3 signal. Since the WAIT selection circuit 306 is selected by this WAS3 signal, / W
A negative logic WAIT1 signal is output as the AIT signal.

The operation of the WAIT pulse generating circuit 303 at this time will be described with reference to the circuit configuration of FIG. 4 and the timing chart of FIG.

When the CPU 101 starts the access, T
The / BCYL signal is set to the low level in the middle of one cycle to indicate that the access cycle is in progress.

The flip-flops 401 to 404 are / B
When CYL is high level, the clear input is active, so the output Q of the flip-flops 401 to 404 until the middle of the T1 cycle when / BCYL becomes low level.
All go low, and the WAIT1 output goes low.
Become a level.

In this state, in the T1 cycle / BC
When the YL signal becomes low level, the flip-flops 401 to 404 sequentially output the level of the D input to Q in synchronization with the rising edge of SYSCLK.

The D input of the flip-flop 401 is high
Since it is fixed to the level, the Q output of the flip-flop 401 becomes high level at the rising edge of SYSCLK at the boundary between the T1 cycle and the T2 cycle. Then, the Q output continues to maintain the high level until the / BCYL signal becomes the high level and is cleared, that is, until the middle of the T3 cycle.

The Q output of the flip-flop 401 is connected to the D input of the flip-flop 402. Therefore, the Q output of the flip-flop 402 becomes low level until the rising edge of SYSCLK in the cycle next to the T2 cycle, and becomes high level after the rising edge.
Level. The high level of the Q output of the flip-flop 402 is held until the / BCYL signal goes high and the flip-flop 402 is cleared.

The AND gate 405 outputs a high level when the Q output of the flip-flop 401 is at a high level and the Q output of the flip-flop 402 is at a low level. That is, the WAIT1 signal outputs a high level only during the T2 cycle, and outputs a low level during the other periods. Therefore, in this case / WA
The waveform of the IT signal is as shown in FIG.

As described above, the CPU 101 samples the low level of the / WAIT signal at the falling edge of the SYSCLK in the T2 cycle, so that the TW cycle is inserted after the T2 cycle. Then, since the high level of the / WAIT signal is sampled at the falling edge of SYSCLK in the TW cycle, the CPU 101 shifts to the T3 cycle which ends the access cycle. In this case, the / BCYL signal goes low between T2 and TW, goes high during the middle of the T3 cycle, and the flip-flops (401 to 404) are cleared.

The CPU 101 is the second RAM 1 of block 4.
When 07 is accessed, the access timing is 1 wait shown in FIG. 2B, as in the case of the block 3 described above.

The CPU 101 is the third RAM 1 of block 5.
08 access to W from the address decoder 325
The AS5 signal is output, and the WAS5 signal causes the fifth WA
Since the IT selection circuit 308 is selected, a negative logic WAIT2 signal is output as the / WAIT signal.

WAIT pulse generation circuit 303 in this case
Will be described with reference to the circuit configuration of FIG. 4 and the timing chart of FIG.

The operations of the flip-flops 401 and 402 are the same as those described above. Flip-flop 403
The Q output of the flip-flop 402 is connected to the D input of the. Therefore, the Q output of the flip-flop 403 becomes high level with a delay of one clock from the Q output of the flip-flop 402 at the rising edge of SYSCLK. Therefore, the WAIT2 signal goes high from the T2 cycle and goes low at the rising edge of the cycle following the first TW cycle. Therefore, WAIT
The / WAIT signal selected from the two signals has the timing chart shown in FIG.

The CPU 101 first sets / W in the T2 cycle.
A low level of the AIT signal is sampled and a TW cycle is inserted. In the next TW cycle, the / WAIT
, The second TW cycle is inserted. In the second TW cycle, since the high level of the / WAIT signal is sampled, the access cycle is ended by moving to the T3 cycle. CPU101 / BCY in the middle of T3 cycle
Since the L signal is set to the high level, the flip-flops 401 to 404 are cleared.

The CPU 101 is the second RAM 1 of block 6.
When 07 is accessed, the 2-wait access timing shown in FIG. 2C is obtained, as in the case of the block 5 described above.

When the CPU 101 accesses the I / O area of the block 7, the address decoder 325 causes the WAS 7
Since the signal is output and the WAS7 signal selects the seventh WAIT selection circuit 310, a negative logic WAIT3 signal is output as the / WAIT signal.

The operation of the WAIT pulse generating circuit 303 at this time will be described with reference to the circuit configuration of FIG. 4 and the timing chart of FIG.

Flip-flops 401, 402 and 403
The operation of is the same as the operation described above. Since the Q output of the flip-flop 403 is connected to the D input of the flip-flop 404, the Q output of the flip-flop 404 is more SYSCL than the Q output of the flip-flop 403.
It goes high with a delay of one clock at the rising edge of K.

Therefore, the WAIT3 signal becomes high level from the T2 cycle and becomes low level at the rising edge of the cycle following the second TW cycle. Therefore, the / WAIT signal for which the WAIT3 signal is selected becomes the timing chart shown in FIG.

The CPU 101 first sets / W in the T2 cycle.
Since the low level of the AIT signal is sampled and the TW cycle is inserted and the low level of / WAIT is sampled again in the next TW cycle, the second TW cycle is inserted. In addition, even in the second TW cycle / W
Since the low level of AIT is sampled, the third TW cycle is inserted. In the third TW cycle, since the high level of the / WAIT signal is sampled, the access cycle is ended by moving to the T3 cycle. CPU101 / BCY in the middle of T3 cycle
Since the L signal is set to the high level, the flip-flops 401 to 404 are cleared.

The CPU 101 is the ROM 103 of the block 8.
2 is accessed in the same manner as in the case of the block 7, the access timing of 3 waits shown in FIG.

Next, the initialization operation of the ISDN communication control system will be described. This ISDN communication control system
A test is performed to confirm the access speed and capacity of the mounted RAM at the start-up (for example, when the power is turned on). Describing based on the above configuration, the CPU 101 first determines the second RAM 107 and the third RAM.
A memory test is executed on the memory spaces of the blocks 3, 4, 5, and 6 which are the memory areas of 108. The test contents check the memory access speed and the installed memory capacity.

The CPU 101 notifies the personal computer of the result of the memory test, and the personal computer downloads an executable processing program to the ISDN communication processing system according to the result of the memory test. The processing program is downloaded not only at the time of initialization, but also at any time when processing is required and according to the result of the memory test. The host manages the memory capacity notified by the result of the memory test and the capacity of the downloaded processing program, and always stores the free capacity of the downloadable memory. When the processing program is no longer needed, the personal computer adds the capacity of the processing program that is no longer needed as free memory space.

FIG. 7 is a flow chart showing the procedure of the memory test at the time of initialization of the ISDN communication control system of this embodiment.

The parameter N used in FIG. 7 is this ISD.
It is a parameter of the execution region when the N communication processing system divides the address space for testing. More specifically, in the present embodiment, the N = 3 memory test means a memory test of the address area of the block 3 shown in FIG. In this embodiment, the second RAM 107 and the third RAM
The access speed is fixed except for the area 108. Therefore, the memory test is performed only for blocks 3 through 6.

First, the parameter N is initialized to 3 (step S702). Then, a memory test of the memory block N, that is, the block 3 is performed (step S7).
03). Details of the memory test for the block N (that is, the processing procedure of step S703) will be described later.

When the memory test on the memory of the block 3 is completed, the test result is judged (step S7).
04). When it is determined that a valid memory exists as a result of the test in block 3, 1 is set as a flag indicating OK in the table 3 indicating the determination result, and the access speed (the number of waits in this case) of the memory is set (step S705). ). The table N shows the memory test determination result of the block N.

Next, it is judged whether or not the tested block is the block 6 of the last block (step S7).
06), if it is not the last block, 1 is set to the parameter N.
Is added (step S707), and the memory test of the next block N is executed. In this way, the memory tests of the blocks 3 to 6 are sequentially performed, the test results are stored in the tables 3 to 6, and the test ends (step S708).

Details of the memory test executed in step S703 will be described below with reference to FIG. FIG. 8 is a flowchart illustrating the procedure for executing the memory test.

First, wait, which is a parameter of the weight value of the block to be tested, is set to the maximum value. The setting is performed by the first register 301 or the second register 302 described above.
, S0, S of the WAIT selection circuit of the block to be tested
It is performed for the bit corresponding to 1. In the present embodiment, since the setting range of the number of weights is 0 to 3, the maximum value 3 is set as the parameter wait (step S8).
02).

Next, a memory at a specific address in the block
A test (step S803) is performed. In this embodiment, the specific address is the start address of the block to be tested. Therefore, the memory test is performed on the head address of the block to be tested (40000000h in the case of block 3). In this memory test, data is written in and read from the head address to check whether or not data can be normally accessed.

As a result of the memory test, when the access is normally possible, it is determined whether the parameter wait has the minimum value, that is, 0 in the present embodiment (step S805). The wait is decremented by 1 (step S806). Then, the memory test in step S803 is repeated for the specific address. Thus, the process of reducing the parameter wait is repeated until the memory test cannot be performed normally (steps S803 to S806).

If the memory access cannot be performed normally, the process proceeds from step S804 to step S807. Then, it is checked whether the parameter wait has the maximum value (step S807). In this embodiment, the maximum value is 3
It is. If the parameter wait is not the maximum value, the parameter wait is incremented by 1 (step S80
8) Then, a memory test for the same specific memory as described above is performed (step S809). As a result of the memory test, if the access cannot be normally performed, the parameter wait is increased by 1 again and the process returns to the memory test (step S810). In this way, the process of increasing the parameter wait is performed until the memory access can be normally performed (steps S807 to S81).
0). As a result, the minimum weight value for the memory block is obtained.

On the other hand, when the parameter wait has the minimum value in step S805, the process proceeds to step S809.

When the memory test in step S809 is completed normally, it is checked whether data can be written and read normally in all areas in the same block (step S811). As a result of this memory test, if the access to the block is normally performed, the test determination of the block is determined to be OK (step S81).
3) The memory test for this block is completed.

As a result of the memory test in step S811, if the access to the block is not normally performed, the test determination of the block is determined to be NG (step S814), and the memory Finish the test.

Furthermore, when the maximum value of the parameter wait is judged to be the maximum value in step S807, the parameter wait is set to the minimum value 0 (step S8).
15), it is determined that there is no memory in the block (step S816), and the memory test ends.

As described above, the present ISDN communication control system can perform a memory test of each block when the system is started up, determine a valid block, and optimize the memory access speed. The determination of the valid block is the determination of the valid memory area, which means that the second RAM 107 and the third RAM 10 are determined.
8 is to determine the capacity of the mounted memory.

The ISDN communication control system notifies the control unit of the personal computer via the ISAi / f109 the memory capacity determined from the effective block and the memory access speed. The control unit of the personal computer selects a program to be downloaded to the ISDN communication control system and its load destination from the memory capacity and access speed, and executes the download. For example, as a program requiring a high access speed, H.264 of ITU-T recommendation is available. 22
An ISDN communication program that realizes one protocol is included. Further, as a program that can be used at a low speed, there is an ISDN telephone program that transmits and receives voice data.

As described above, according to this embodiment, the access speed and capacity of the mounted RAM are
It is detected every time the system is initialized. Therefore, the CPU 101 of the system can access the RAM with an appropriate number of weights according to the access speed of the mounted RAM. Therefore, even if the memory that was decided at the time of design was quickly discontinued, or if a cheaper memory was developed, it is possible to replace it with a new memory and use a relatively cheap memory. Will be possible.

Furthermore, even after designing the control system,
Depending on the function to be operated by using it, it becomes possible to select whether to use a high-speed memory with access speed priority or to use a low-speed memory with cost priority.

The exchangeable memory is PCMCIA.
Memory card or SIMM memory module.

Further, in the above embodiment, step S803.
In the memory test of step S806 from step S806, the value with which the number of waits becomes smaller and the access becomes NG is identified, but conversely, the value where the number of waits becomes larger and the access becomes OK is identified. You may do it.

In the above embodiment, the entire address area of the CPU 101 is divided into blocks so that the weight can be set. However, only the expandable memory area may be set in the weight.

In the above embodiment, the bus cycle is identified by the / BCYL signal. However, depending on the type of the CPU 101, a plurality of status signals indicating the bus cycle status are decoded to generate a signal for identifying the bus cycle. You may. Of course, a signal corresponding to / BCYL may be generated by a logical sum signal of the / RD signal and the / WR signal.

Further, the present invention may be applied to a system composed of a plurality of devices or an apparatus composed of one device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus. In this case, the storage medium storing the program according to the present invention constitutes the present invention. Then, by reading the program from the storage medium to the system or device, the system or device operates in a predetermined manner.

[0106]

As described above, according to the present invention,
It is possible to detect the number of weights suitable for the mounted memory and access the memory with the detected number of weights. For this reason, when the memory decided at the time of design is soon out of stock, or when a cheaper memory is developed, it is possible to replace it with a new memory and use a relatively cheap memory. It becomes possible to do.

Further, according to the present invention, in a system in which the memory can be attached and detached, the memory to be attached is selected according to the function to be operated (for example, access speed is prioritized, high speed memory is used, or cost is prioritized). It is possible to use slow memory).

[0108]

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an ISDN communication control system according to the present embodiment.

FIG. 2 is a timing chart showing a timing at which a CPU accesses a memory according to the present embodiment.

FIG. 3 is a block diagram showing a configuration of a weight control unit 102.

FIG. 4 is a diagram showing a detailed circuit configuration of a WAIT pulse generation circuit 303.

5 is a diagram showing a detailed circuit configuration of a first WAIT pulse selection circuit 304. FIG.

FIG. 6 is a diagram showing an address map in the ISDN communication control system of the present embodiment.

FIG. 7 is a flowchart showing a memory test procedure at the time of initialization of the ISDN communication control system of the present embodiment.

FIG. 8 is a flowchart illustrating an execution procedure of a memory test.

[Explanation of symbols]

 101 CPU 102 Weight Control Unit 103 ROM 104 First RAM 105, 106 Socket 107 Second RAM 108 Third RAM 109 ISAi / f 110 Communication i / f

Claims (15)

[Claims] 1. A memory control device for controlling access to a memory, wherein the detecting means detects the number of weights to be inserted when the memory is accessed, and the number of weights detected by the detecting means is set. A memory control device, comprising: setting means for setting and a inserting means for inserting the number of weights set by the setting means when accessing the memory. 2. The memory control device according to claim 1, wherein the detection unit and the setting unit are executed during initialization processing of a system including the memory control device. 3. The detecting means performs access to the memory with a plurality of types of wait numbers to determine success or failure thereof,
The memory control device according to claim 1, wherein the minimum number of accessible weights is detected. 4. A capacity detecting means for accessing the memory space including the memory with the number of weights set by the setting means, and detecting the accessible memory capacity based on the success or failure of the access. Claim 1
The memory control device according to 1. 5. The memory control device according to claim 4, further comprising notifying means for notifying the number of weights detected by the detecting means and the memory capacity detected by the capacity detecting means to the outside. 6. A memory control device for controlling access to a memory, which manages an accessible memory space by dividing it into a plurality of blocks, and managing means for inserting each of the plurality of blocks at the time of accessing the memory. Detection means for detecting the number of waits to be performed; setting means for setting the number of waits detected by the detection means for each of the plurality of blocks; and Detect which one of multiple blocks,
A memory control device comprising: an insertion unit for inserting the number of waits set by the setting unit, corresponding to the detected block, into the access cycle. 7. The memory control device according to claim 6, wherein the detection unit and the setting unit are executed during initialization processing of a system including the memory control device. 8. The detecting means detects, for each of the plurality of blocks, a minimum number of accessible weights by accessing the memory with a plurality of types of weights to determine success or failure. The memory control device according to claim 6. 9. The apparatus further comprises: a capacity detecting means for executing an access to each of the plurality of blocks with the number of weights set by the setting means, and detecting an accessible memory capacity based on success or failure of the access. 7. The memory control device according to claim 6, wherein: 10. The capacity detecting means performs access to each of the plurality of blocks with the number of weights set by the setting means, and determines whether or not the block is accessible based on the success or failure of the access. The memory control device according to claim 9, wherein the determination is performed. 11. An informing means for informing the outside of the number of weights of each of the plurality of blocks detected by the detecting means and the usable blocks detected by the capacity detecting means. The memory control device according to claim 10. 12. The detection means detects the number of weights to be inserted in a block corresponding to a memory space of a removable memory among the plurality of blocks. Memory controller. 13. A memory control method for controlling access to a memory, comprising: a detecting step of detecting the number of weights to be inserted when the memory is accessed; and a number of weights detected in the detecting step. And a inserting step of inserting the number of weights set in the setting step when the memory is accessed. 14. A memory control method for controlling access to a memory, the managing step of dividing an accessible memory space into a plurality of blocks for management, and accessing the memory for each of the plurality of blocks. Sometimes a detection step of detecting the number of weights to be inserted, a setting step of setting the number of weights detected in the detection step for each of the plurality of blocks, and an access destination when a memory access occurs Is for any of the blocks,
And a step of inserting the number of waits corresponding to the detected block set in the setting step into the access cycle. 15. An information processing apparatus comprising the memory control device according to claim 1. Description: